Lab # 01: Introduction To Basic Logic Gates & DLD Trainer: Objectives

Lab # 01: Introduction to Basic Logic Gates & DLD Trainer
Objectives
To know about the basic logic gates, their truth tables, input output characteristics and analyzing their
functionality. Introduction to logic gate IC’s, Integrated Circuits pin configurations and their use.
Equipment Required
DLD Trainer, logic IC’s
Lab Instructions
 This lab activity comprises of two parts: In Lab Exercises and Lab report.
 The students should perform and demonstrate each lab task for step-wise evaluation.
 Only those tasks that completed during the allocated lab time will be credited to the
students. Students are however encouraged to practice on their own in spare time for
enhancing their skills.
 The instructor will provide a brief description of the various sections, of the
oscilloscope and function generator.
Lab Report Instructions
All questions should be answered precisely to get maximum credit. Lab report must ensure
following items:
 Lab objectives
 Results (graphs) duly commented and discussed
 Conclusion
Background Theory:
The Digital Logic Circuits can be represented in the form of (1) Boolean Functions, (2) Truth Tables,
and (3) Logic Diagram. Digital Logic Circuits may be practically implemented by using electronic
gates. The following points are important to understand.
 Electronic gates are available in the form of Integrated Circuits (IC’s) and they require a power.
 Supply Gate inputs are driven by voltages having two nominal values, e.g. 0V and 5, 12V
representing logic 0 and logic 1 respectively.
 The output of a gate provides two nominal values of voltage only, e.g. 0V and 5, 12V representing
logic 0 and logic 1 respectively. In general, there is only one output to a logic gate except in some
special cases.
 Truth tables are used to help show the function of a logic gate in terms of input values combination
with desired output.
 Logic Diagram is used to represent the Digital Logic Circuit in the form of symbols connected with
each other.
Part 1. Familiarize yourself with AM 2001 logic trainer:

The first part of this lab experiment is an exercise to have a general introduction to the AM 2001 logic
trainer and gather information about the trainer, how the logic trainer works and how we can use this
trainer for hardware implementation of our experiments. AM 2001 logic trainer has diﬀerent hardware
components that can be categorized as follows:
 Logic switches
 Breadboard
 State monitors/LEDs
 7 Segment Display
Figure 1.1 AM 2001 logic trainer
Logic Switches:
There are 8 logic switches present on AM 2001 trainer starting from S2 to S9. When a switch is in
upward direction it is representing a logic 0 and when a switch is in downward direction it is
representing a logic 1.
Breadboard:
A breadboard is also present on the trainer. The breadboard contains serial and parallel connected
interfaces. With the help of bread board, we can easily connect logic switches and other peripherals on
the trainer.
State Monitors / LEDs:

There are 16 logic state monitors or LEDs present on the trainer. The state monitors are LEDs are used
to monitor results. When a logic state monitor or led is on it is representing a logic 1 and when a logic
state monitor or LED is oﬀ it is representing a logic 0.
7 Segment Display:
There 3 seven segment displays present on the AM 2001 trainer. The seven-segment display is are used
to monitor results in decimal format. The 7-segment display contains 9 input connections and 4 output
connections. When a BCD coded number is provided to these input lines the corresponding digital
number appears on the seven segment.
Lab Tasks-Part 2
Study and verify the truth table of the logic gates
A logic gate is a basic building block of a digital circuit that has two inputs and one output. The
relationship between the i/p and the o/p is based on a certain logic. These gates are implemented using
electronic switches like transistors, diodes. But, in practice basic logic gates are built using CMOS
technology, FETS and MOSFET(Metal Oxide Semiconductor FET)s. Logic gates are used in
microprocessors, microcontrollers, embedded system applications and in electronic and electrical
project circuits. The basic logic gates are categorized into seven: AND, OR, XOR, NAND, NOR,
XNOR and NOT.
Procedure
1. Place the IC on the Bread board as shown in the figure 1.2
Figure 1. 2
2. Using the power supply available at digital Logic Lab, connect pin7 (Ground) and pin14 (Vcc) to
power up IC.
3. Give number of possible combinations of inputs using the slide switches SW0-SW3 and note down
the output with help of LED for all gate ICs.
Lab Task 1: Inputs Outputs
IC 7408 AND gate A B Desired Observed
0 0
0 1
1 0
Figure 1.3
1 1
Table 1.1
IC 7404 NOT gate
A Desired Observed
1
Figure 1.4
Table 1.2

IC 7402 NOR gate
A B Desired Observed
0 0
0 1
1 0
Figure 1.5
1 1
Table 1.3
Inputs Outputs
Lab Task 4:
IC 7432 OR gate A B Desired Observed
0 0
0 1
1 0
Figure 1.6 1 1
Table 1.4
Inputs Outputs
Lab Task 5:
IC 7486 XOR gate A B Desired Observed
0 0
0 1
1 0
1 1
Figure 1.7
Table 1.5
Integrated Circuits pin configurations
OR Gate IC (7432)
AND Gate IC (7408) XOR Gate IC (7486)
NAND Gate IC (7400)
NOT Gate IC (7404)

Sample Viva Questions
1. Explain what are the universal logic gates?
2. Define 0 and 1 in items of voltage values.
3. Explain what is a truth table?
Critical Analysis / Conclusion

(By Student about Learning from the Lab)
Lab # 02: Introduction to proteus
Objectives
Learn to use Proteus Software for Simulation of Digital Logic Circuits.
Lab Instructions
following items:
 Lab objectives
 Results (graphs) duly commented and discussed
Part 1 - Proteus (Simulation Software)

Proteus has many features to generate both analogue and digital results over a virtual environment.
However, this lab will focus on only tools that will be used in digital schematic designs and verification
of basic logic gates.
Procedure
Right click on the ISIS icon present on desktop and open it.
Figure 2.1 ISIS icon

After right click on the ISIS this window will be shown
Figure 2.2 Interface of Proteus software window
Parts Browsing:
Proteus has many models of electronic equipment such as logic gates, many kinds of switches and basic
electronic devices. The equipment can be founded by clicking on and then a new window will pop-up
and wait for the parts information as shown in figure 2.3
Finding Steps:
1. Type information of device such as “OR gate” in box 1.
2. If some specific category is known, the device can narrow on focusing by selecting catalogue in the
box 2.
3. After the information is entered, the list of related devices will appear in the box 3, so that needed
device can be chosen and then click “OK” button to confirm selection in figure 2.3.
Figure 2.3 Pick Devices window in Proteus

Figure 2.4 Pick selected Devices window in Proteus
Power supply and input signal Generator

All of the electrical circuits require power supplies. The power supplies for logic circuits are represented
in digital system design on Proteus because the schematic may be too complicated to understand for
simulation section. Therefore, power supplies will be needed as input power for a system. Moreover,
all of the input generators, such as ac generator, dc and pulse are contained in this category and it will
be shown when is clicked. In addition, “Ground” will not be contained in this group. Because it is not
an input signal it is just a terminal junction. Therefore, it will be grouped in terminal category as shown
in figure 2.5 & 2.6.
Figure 2.5 Power supplies window in Proteus Figure 2.6 Terminals window in Proteus
Logic State:
In addition, there is another input that usually be used in digital circuit designed circuit but it does not
exist in real world as an equipment it is called as “LOGIC STATE”. It can be found in the picking part
section (type logic state and pick it figure 2.7).
Figure 2.7 Logic State in Proteus

Placing Equipment:
Selecting all devices needed to be placed on the circuit window (Grey window) and wiring it. It can be
done by following these steps:
1. Click on and select the first device that will be placed.
2. Place mouse wherever the device is preferred to be place and then click the left button of the mouse.
The device will be placed, if it is needed to be moved, click the right button of the mouse on the
device symbol to select the mouse. Then hold this device with the left mouse button and move it to
any desired place. (figure 2.8)
Figure 2.8 Placing the devices in Proteus
To wire devices together, click at the source pin of device and then move mouse cursor to destination
pin of the device. In this step the pink line will be appeared and it will be wire of circuit after clicking
the mouse on the destination pin of the circuit (as shown in figure 2.9).
Figure 2.9 Wiring devices to make a circuit

After wiring all devices and connect all inputs according to the circuit, the simulation is ready to be run
by clicking on Play button to run and stop button to stop. Logic probe or LED can be used to observe
output state.
Lab Task 1:
Implementation of AND gate on Proteus
Inputs Outputs
0 0 0
0 1 0
1 0 0
Figure 2.10
1 1 1
Table 2.1
Take the components from Library by pressing the tab “Library”
Figure 2.11 Pick parts from library
Search the Components by name and then click OK to adding them in Devices Panel
Figure 2.12 Pick parts from library

Connect the components and the design by specific name
Figure 2.13 Connection the components
Press the “start” button to execute the design and verify the results
Figure 2.14 Design of logic AND gate
Lab Task 2:
Implementation of OR gate on Proteus
Inputs Outputs
0 0 0
0 1 1
Figure 2.15
1 0 1
1 1 1
Table 2.2
Figure 2.16 Design of logic OR gate
Lab Task 3:
Implementation of NOT gate on Proteus
Inputs Outputs
A Desired Observed
Figure 2.17 0 1
1 0
Table 2.3
Figure 2.18 Design of logic NOT gate
Lab Task 4:
Implementation of NAND gate on Proteus
Inputs Outputs
0 0 1
Figure 2.19
0 1 1
1 0 1
1 1 0
Table 2.4
Figure 2.20 Design of logic NAND gate
Lab Task 5:
Implementation of XOR gate on Proteus
Inputs Outputs
0 0 0
0 1 1
Figure 2.21
1 0 1
1 1 0
Table 2.5
Figure 2.22 Design of logic XOR gate

Lab Task 6:
Draw the schematic for following logic circuit in Proteus and fill in the table. Answer the questions at
the end.
A B C D F1 F2
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table 2.6
Lab Task 7:
Construct XOR and XNOR circuits using AND, NOT and OR gates.
1. Write Boolean Logic equation for function F1 in terms of the inputs A, B, C, D.
2. Write Boolean Logic equation for function F2 in terms of the inputs A, B, C, D.
3. Verify the functionality of F1 and F2 on Proteus by comparing F1 and F2 in truth

Table with the outputs in the Proteus.
Analysis / Conclusion
( By Student about Learning from the Lab)

Lab # 3: Verification of basic theorems and universal gates
implementation on digital trainer using gate integrated circuits
Objectives
 To simulate and implementation of any logic function by using universals gates (NAND/NOR).
 To build the understanding of how to construct any combinational logic function using NAND or
NOR gates only.
 To verify theorems of Boolean algebra through logic gates
Equipment Required
 Logic gates (IC) trainer kit.

 Connecting patch chords.
 IC 7400 and IC 7402.
Lab Instructions
 Only those tasks that completed during the allocated lab time will be credited to the students.
Students are however encouraged to practice on their own in spare time for enhancing their skills.
All questions should be answered precisely to get maximum credit. Lab report must ensure following
items:
 Lab objectives
 Results (graphs) duly commented and discussed
 Conclusion
Background theory
Digital circuits are more frequently constructed with universal gates. NAND and NOR gate are called
universal gates. Any Boolean logic function can be implemented using NAND only or NOR only
gates. NAND and NOR gates are easier to fabricate with electronic components than basic gates.
Because of the prominence of universal gates in the design of digital circuits, rules and procedures
have been developed for conversion from Boolean function given in terms of AND, OR, and NOT into
its equivalent NAND and NOR logic diagram.
In-Lab:
 This lab has three parts. In first part, implementation of any logic expression by using only NAND
is done. In second part, the same procedure is done by using NOR gate only. In third part, verify
theorems of Boolean algebra is done by logic gates.
Lab Tasks-Part-1
Lab Task 1: Implementing any logic expression by using only NAND gates
If we can show that the logical operations AND, OR, and NOT can be implemented with NAND gates,
then it can be safely assumed that any Boolean function can be implemented with NAND gates.
Procedure:
 Implementation AND, OR and NOT gates by using only NAND gates. Verify their truth tables.
 Insert the IC on the trainer’s breadboard.
 Use any one or more of the NAND gates of the IC for this experiment.
 Any one or more Logic Switches of the trainer (S1 to S9) can be used for input to the NAND gate.
 For output indication, connect the output pin of the circuit to any one of the LEDs of the trainer
(L0 to L15).
Lab Task 1: Verification of NOT function
 Connect the circuit as per Figure 3.1.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to that of an
AND gate. Record your observation in the table3.1 below.
A F=A’
Figure 3.1 NOT gate
Input Output
A F
Table 3.1
Lab Task 2: Verification of AND function

AND gate. Record your observation in the table 3.2 below.
A (AB)’ F=AB
B
Figure 3.2 AND gate
Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 3.2
Lab Task 3: Verification of OR function

A A’
F=A+B
B
B’
Figure 3.3 OR gate
Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 3.3
Lab Task 4: Verification of XOR function

AND gate. Record your observation in the table 3.4 below
A (A(AB)’)’
F=A’B+AB’
(AB)’
B (B(AB)’)’
Figure 3.4 XOR gate
Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 3.4
Lab Task 5: Verification of XNOR function

A (A(AB)’)’
F=AB+A’B’
(AB)’
B (B(AB)’)’
Figure 3.5 XNOR gate

Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 3.5
Part 2 - Implementing any logic expression by using only NOR gates
If we can show that the logical operations AND, OR, and NOT can be implemented with NOR gates,
then it can be safely assumed that any Boolean function can be implemented with NOR gates.
Procedure
 Simulate AND, OR and NOT gates in proteus software, by using only NOR gates. Verify their truth
tables.
 Insert the IC on the trainer’s breadboard.
 Use any one or more of the NOR gates of the IC for this experiment.
 Any one or more Logic Switches of the trainer (S1 to S9) can be used for input to the NOR gate.
 For output indication, connect the output pin of the circuit to any one of the LEDs of the trainer (L0
to L15).
Lab Tasks-Part-2
Lab Task 6: Verification of NOT function

Figure 3.6 NOT gate
Input Output
A F
0
Table 3.6
Lab Task 7: Verification of AND function
 Connect the circuit as per Figure 3.7

Figure 3.7 AND gate
Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 3.7
Lab Task 8: Verification of OR function

Figure 3.8 OR gate
Inputs Output
A B F
0 0
0 1
1 0
1 1
Table 3.8
Lab Task 8: Verification of absorption theorem
Verify absorption theorem 𝑨 + (𝑨. 𝑩) = 𝑨
Draw circuit diagram
Truth table:
Inputs Outputs
A B Observed
0 0
0 1
1 0
1 1
Table 3.9
Lab Task 9: Verification of absorption theorem
Verify absorption theorem 𝑨. (𝑨 + 𝑩) = 𝑨
Truth table:
Inputs Outputs
A B Observed
0 0
0 1
1 0
1 1
Table 3.10
Post Lab:
Lab Task 10: Verify De Morgan’s law. Show truth table and circuit diagram
1. 𝑿.𝒀 = 𝑿 + 𝒀

𝑿.𝒀
𝑿+𝒀
Truth table:
Inputs Outputs
Inputs Outputs
X Y Observed
X Y Observed
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
𝟐. 𝑿+𝒀 = 𝑿. 𝒀

𝑿+𝒀
𝑿. 𝒀
Truth table:
Inputs Outputs
Inputs Outputs
X Y Observed
X Y Observed
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
1. Write two characteristics of combinational circuits.
2. Explain what is the specialty of NAND and NOR gates?
( By Student about Learning from the Lab)

LAB # 4: Realization of adder operations
Objectives
The objective of this experiment is to realize the half adder and full adder by using basic gates and
universal NAND gate
Equipment Required
 IC 7400
 IC 7408
 IC 7486
 IC 7432
 IC Trainer Kit
Lab Instructions
 This lab activity comprises of three parts: Lab Exercises, Post-Lab and lab report.
 The students should perform and demonstrate each lab task separately for step- wise evaluation
(please ensure that course instructor/lab engineer has signed each step after ascertaining its
functional verification).
Students are however encouraged to practice on their own in spare time for enhancing their skills

items:
 Lab objectives
 Results
 Conclusion
Part 1 -Familiarize yourself with Half Adder & Full Adder

Half Adder:
A combinational logic circuit that performs the addition of two data bits, A and B, is called a half-adder
. Addition will result in two output bits; one of which is the sum bit, S , and the other is the carry bit, C.
The Boolean functions describing the half-adder are:
S =A © B
C=AB
Full Adder:
The half-adder does not take the carry bit from its previous stage into account .This carry bit from its
previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and B, and
a carry-in bit, Cin , is called a full-adder . The Boolean functions describing the full-adder are:
S = (x © y) ©Cin
C = xy + Cin (x © y)
Lab Task 1:
Implement half adder by using basic gates and verify the results
Fig 4 .1: Half adder
Truth Table:
INPUTS OUTPUTS
Desired Observed
Value Value
A B S C S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Table:4.1
Procedure:
1. Collect the components necessary to accomplish this experiment.
2. Plug the IC chip into the breadboard.
3. Connect the supply voltage and ground lines to the chips. Pin 7 = Ground and Pin 14 = +5V.
4. According to the pin diagram of each IC mentioned above, make the connections according to
circuit diagram.
5. Connect the inputs of the gate to the input switches.
6. Connect the output of the gate to the output LEDs.
7. Once all connections have been done, turn on the power switch of the breadboard
8. Operate the switches and fill in the truth table (Write "1" if LED is ON and "0" if LED is OFF
Apply the various combination of inputs according to the truth table and observe the condition of
Output LEDs.
Lab Task 2:
Implement half adder by using NAND gates and verify the results.
Fig 4.2: Half adder using NAND gate
Truth Table:
INPUTS OUTPUTS
Desired Value Observed Value
A B S C S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Table: 4.2
Lab Task 3:
Implement full adder by using basic gates and verify the results
Fig 4.3: Full adder

Truth Table:
INPUTS OUTPUTS
A B Cin S Cout S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table 4.3
Lab Task 4:
Implement full adder by using NAND gates and verify the results
Fig:4.4
Post lab exercise:
1. Perform all the Lab Tasks that is mention in part 1 by using Proteus ISIS Professional and verify
the results.
2. Implementation of 2 bit binary parallel adder and verify results.
Sample viva questions:
1. Write the applications of adders?
2. Draw the block diagram of 4-bit full adder by using full adder?

LAB # 5: Realization of subtractor operations
Objectives
The main objective is to realize the half subtractor and full subtractor by using basic gates and
universal NAND gate
Equipment Required
 IC 7400
 IC 7408
 IC 7486
 IC 7432
 Patch Cords
 IC Trainer Kit
Lab Instructions

items:
 Lab objectives
 Results
 Conclusion
Familiarize yourself with Half Subtractor & Full Subtractor

Half Subtractor:
The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has
two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).
Fig 5.1: Block diagram of half subtractor

Full Subtractor:
A full Subtractor is combinational circuit that performs a subtraction between three bits. Subtracting
two single-bit binary values, B, Cin from a single-bit value A produces a difference bit D and a borrow
out Br bit. This is called full subtraction.
Fig 5.2: Block diagram of Full subtractor
Lab Task
Lab Task 1:
Implement half subtractor by using basic gates and verify the results
Fig 5.3: Circuit diagram of half subtractor
Procedure:
 Collect the components necessary to accomplish this experiment.
 Plug the IC chip into the breadboard.
 Connect the supply voltage and ground lines to the chips. PIN7 = Ground and PIN14 = +5V.
 Make the connections according to circuit diagram.
 Connect the inputs of the gate to the input switches of the LED.
 Connect the output of the gate to the output LEDs.
 Once all connections have been done, turn on the power switch of the breadboard.
 Operate the switches and fill in the truth table (Write "1" if LED is ON and "0" if LED is OFF
Apply the various combination of inputs according to the truth table and observe the condition of
Output LEDs
Truth Table:
Inputs Outputs
Desired Observed
Value Value
A B D Br D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Table: 5.1
Lab Task 2:
Implement half subtractor by using NAND gates and verify the results
Fig 5.4: Circuit diagram of half subtractor using NAND gate
Lab Task 3:
Implement full subtractor by using basic gates and verify the results
Fig 5.5: Circuit diagram of Full subtractor

Truth Table:
Inputs Outputs
A B Cin D Br D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Table: 5.2
Lab Task 4:
Implement full subtractor by using NAND gates and verify the results
Fig 5.6: Circuit diagram of Full subtractor using NAND gate

Truth Table
Inputs Outputs
A B Cin D Br D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Table: 5.3
Post Lab Exercise:
1. Perform all the Lab Tasks by using Proteus ISIS Professional and verify the results
2. Implementation of 2-bit binary parallel subtractor and verify results.
Sample Viva Question
1. What is half and full subtractor?
2. What does Minuend and Subtrahend denote in a subtractor?

LAB # 6: Design of combinational circuits
Objectives
The objective of this experiment is to realize how to implement the simplified Boolean Expression
using logic gates
Equipment Required
 IC 7400
 IC 7408
 IC 7486
 IC 7432
 IC Trainer Kit
Lab Instructions

items:
 Lab objectives
 Results
 Conclusion
Part 1 –Introduction to combinational circuits

The combinational logic circuits or time-independent logic circuits in digital circuit theory can be
defined as a type of digital logic circuit implemented using Boolean circuits, where the output of logic
circuit is a pure function of the present inputs only. The combinational logic circuit operation is
instantaneous and these circuits do not have the memory or feedback loops.
This combinational logic is in contrast compared to the sequential logic circuit in which the output
depends on both present inputs and also on the previous inputs. Thus, we can say that combinational
logic does not have memory, whereas sequential logic stores previous input in its memory. Hence, if
the input of combinational logic circuit changes, then the output also changes.
Characteristics of combinational circuits
1. An outputs remain constant; as long input conditions do not require change inputs.
2. An output depends solely on the current input and not on any past input condition or past output
condition.
Part 2 -Introduction to simplify the Boolean Expression
Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive normal form
(sum of min-terms) or conjunctive normal form (product of max-terms).
A Boolean function can be represented by a Karnaugh map in which each cell corresponds to a minterm.
The cells are arranged in such a way that any two immediately adjacent cells correspond to two
minterms of distance 1. There is more than one way to construct a map with this property.
Karnaugh Maps
For a function of two variables, say, f(x, y),
For a function of three variables, say, f(A, B, C)
For a function of four variable f(A,B,C,D)

Task 1 –Design a combinational circuit
Statement:
Following figure shows the intersection of the main highway (Comsats road) with a secondary
access road. vehicle detection sensor is placed along lanes C and D (main road) and lanes A
and B (access road). These sensor outputs are low (0) when no vehicle is present and high (1)
when a vehicle is present. Define the truth-tables for the problem. This intersection traffic light
is to be controlled according to the following logic:
Figure 6.1: vehicle detection sensor
1. The East West light will be green whenever both lanes C and D are occupied.
2. The East West light will be green whenever either C or D is occupied but lanes A and B
are not both occupied.
3. The North South light will be green whenever both lanes A and B are occupied but C and
D and not both occupied.
4. The North South light will be green when either A or B is occupied while C and D are
both vacant.
5. The East West light will be green when no vehicles are present.
Using the sensor outputs, A, B, C, D as inputs, make a truth table to control the traffic light.
There should be two Outputs-S and E-W, that go high when the corresponding light is to be
green. Simplify the circuit as much as possible and show all steps
1. Truth table
Inputs Outputs
A B C D E-W N-S
Table 6.1: input & output states

2. Simplification using K-map
3. Boolean function
4. Logic diagram of E-W
5. Logic diagram of N-S

Task 2 –Design a combinational circuit
Statement
A four-bit binary number is represented as A3, A2, A1, A0, where A3, A2, A1 and A0 represent
the individual bits and A0 is equal to LSB. Design a logic circuit that will produce HIGH output
whenever the binary number is greater than 0010 and less than 1000.
1. Make a truth table 2. Minimize the function 3. Implement the circuit
Truth table
Minimizing the function
Implement the circuit
Use modern tools/resources for implementing digital circuit
Post Lab Exercise:
Perform all the Lab Tasks by using Proteus ISIS Professional and verify the results.
1. Simplify the Boolean function to a minimum number of literals F = xy + x'z + yz.
2. Write the procedural steps for the design of combinational circuits.
LAB # 7: Design and realization of BCD to EXCES- 3 code converters
Objectives
 Creation and observation of the excess 3 code representation sequence
 Exercising the design of code conversion logic circuits,
 Creating the truth table of conversion functions from BCD to EXCESS 3 code
 Developing skills in simplification of specified logical functions
Equipment Required
 IC 7483
 IC 7486
 Patch Cords
 IC Trainer Kit
Lab Instructions

items:
 Lab objectives
 Results
 Conclusion

items:
 Lab objectives
 Results (graphs/tables) duly commented and discussed
 Conclusion
Part 1 -Familiarize yourself with BCD to Excess-3
Code converter is a combinational circuit that translates the input code word into a new corresponding
word. The excess-3 code digit is obtained by adding three to the corresponding BCD digit. To Construct
a BCD-to-excess-3-code converter with a 4-bit adder feed BCD-code to the 4-bit adder as the first
operand and then feed constant 3 as the second operand. The output is the corresponding excess-3 code.
BCD to Excess-3 Circuit specification:
 BCD Excess-3 circuit will convert numbers from their binary representation to their excess-3
representation.
 4 variables, A, B, C, D as inputs and 4 variables, W, X, Y, Z as outputs.
 We can represent 10 binary values from 0000 to 1001. The values 1010, 1011,
 1100,1101,1110,1111 are not used. So those input bit combinations are considered as don’t
 care conditions. It means d (A, B, C, D) = ∑m (10,11,12,13,14,15).
 The Truth table for this circuit as shown in below:
Truth Table
Boolean functions
The Boolean functions for the outputs lines of the circuit are derived from k-maps which are:
BCD to Excess-3 Circuit Design:
We will use the truth table of the circuit to find the Boolean functions for the output lines W, X, Y, Z.
Karnaugh-map is used with don’t care conditions labeled by ‘X’ to obtain the circuit outputs in
simplified form.
For Output Line W
For Output Line X

For Output Line Y
For Output Line Z

Implementation:
A logic diagram is obtained from the Boolean expressions derived by the maps as shown below:
Figure 7.1: Circuit diagram of BCD to EXCESS- 3 converter
Procedure:
1. Use data sheets to get pins description for the IC are used in the circuit as shown in the logic
diagram.
2. Connect the inputs of the circuit to the corresponding logical switches A, B, C and D.
3. Connect the outputs of the circuit W, X, Y and Z to the logical LEDs.
4. Connect the ground and Vcc of for all IC's used in the circuit through the logical trainer kit.
5. Test all input combinations and verify the outputs in the truth table.
Figure 7.2: Circuit diagram of BCD to EXCESS- 3 converter using IC

Truth Table
INPUTS OUTPUT(Ex-3)
BCD Desired Values Observed Values
A B C D W X Y Z W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
Part 2 - Excess-3 to BCD converter
Excess-3 code can be converted back to BCD in the same manner.

Boolean functions
Implementation:
A logic diagram is obtained from the Boolean expressions derived by the maps as shown below
Figure 7.3: Circuit diagram of EXCESS- 3 to BCD converter
Post Lab Exercise:
1. What do you mean by code conversion?
2. What are the applications of code conversion?
3. Convert 0101 into Excess-3 code and 0010 into BCD?

LAB # 8 Design and realization of binary to gray code converter
Objectives
 To design various Code converters using logic gates

 To simulate various code converters
 To understand the importance of code converters in real life applications
Equipment Required
 IC7400
 IC7486
 IC7408
 Patch Cords
 IC Trainer kit
Lab Instructions

items:
 Lab objectives
 Results
 Conclusion
Theory
Binary Codes
A symbolic representation of data/ information is called code. The base or radix of the binary number
is 2. Hence, it has two independent symbols. The symbols used are 0 and 1. A binary digit is called as
a bit. A binary number consists of sequence of bits, each of which is either a 0 or 1. Each bit carries a
weight based on its position relative to the binary point. The weight of each bit position is one power
of 2 greater than the weight of the position to its immediate right. e. g. of binary number is 100011
which is equivalent to decimal number 35.
BCD Codes
Numeric codes represent numeric information i.e. only numbers as a series of 0’s and 1’s. Numeric
codes used to represent decimal digits are called Binary Coded Decimal (BCD) codes. A BCD code is
one, in which the digits of a decimal number are encoded-one at a time into group of four binary digits.
There are a large number of BCD codes in order to represent decimal digits0, 1, 2 …9, it is necessary
to use a sequence of at least four binary digits. Such a sequence of binary digits which represents a
decimal digit is called code word.
Gray Codes
It is a non-weighted code; therefore, it is not a suitable for arithmetic operations. It is a cyclic code
because successive code words in this code differ in one-bit position only i.e. it is a unit distance code.
Applications of Gray Code:
In instrumentation and data acquisition systems, where linear or angular displacement is measured. In
shaft encoders, input-output devices, A/D converters and the other peripheral equipment.
Binary to Gray Code Conversion Steps:
The example shows the steps involved in conversion of a binary code to its gray code. Binary code
taken for the example is 1011.
In the conversion process the most significant bit (MSB) of the binary code is taken as the MSB of the
Gray code. The bit positions G2, G1 and G0 is obtained by adding (B3, B2), (B2, B1) and (B1, B0)
respectively, ignoring the carry generated. From the K-Map simplification for binary to Gray code
conversion the following Boolean expressions are obtained,
Lab Tasks-Part-1
Lab Task 1: Binary Code to Gray Code Conversion
Binary code Gray code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
K-Map for G3
K-Map for G2
K-Map for G1
K-Map for G0
Implementation:
Figure 8.1: circuit diagram Binary to gray code
Truth table:
Binary code Gray code (Observed Value)

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Lab Tasks-Part-2
Lab Task 2: Gray Code to Binary Code Conversion
Binary to Gray conversion is the Most Significant Bit (MSB) of the gray code is always equal to the
MSB of the given binary code. Other bits of the output gray code can be obtained by XOR binary
code bit at that index and previous index.
Truth table:
Gray code Binary output
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
K-Map for B3
K-Map for B2
K-Map for B1
K-Map for B0
Implementation:
Figure 8.2: circuit diagram gray code to Binary converter
Truth table:
Gray code Binary output (observed value )
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 1
0 0 1 0
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 0
1 1 0 0
1 1 0 1
1 1 1 1
1 1 1 0
1 0 1 0
1 0 1 1
1 0 0 1
1 0 0 0
Post Lab Exercise:
1. How do you convert binary to gray code?
2. What is the necessity of code conversions?

LAB # 9: Design and realization of multiplexer and demultiplexer operations
Objectives
 To learn about various application of multiplexer and de-multiplexer.

 To learn and understand the working of IC 74153 and multiplexer.
 To learn and understand the working of IC 74139 and de- multiplexer.
Equipment Required
 IC7400
 IC7486
 IC7408
 IC 74153
 IC 74139
 Patch Cords
 IC Trainer kit
Lab Instructions

items:
 Lab objectives
 Results
 Conclusion
Part 1 -Familiarize yourself with Multiplexers
Multiplexers are very useful components in digital systems. They transfer a large number of information
units over a smaller number of channels, (usually one channel) under the control of selection signals.
Multiplexer means many to one. A multiplexer is a circuit with many inputs but only one output. By
using control signals (select lines) we can select any input to the output. Multiplexer is also called as
data selector because the output bit depends on the input data bit that is selected. The general multiplexer
circuit has 2n input signals, n control/select signals and 1 output signal.
Types of multiplexer:
 2:1 MUX
 4:1 MUX
 8:1 MUX
 16:1 MUX
LAB Tasks-Part-1
Lab Task 1:
4x1 Multiplexer
Figure 9.1: Block diagram of 4x1 Mux
Circuit diagram of 4x1 Mux using AND & OR gate:
Figure 9.2: Circuit diagram of 4x1 Mux

Circuit diagram of 4x1 Mux using NAND gate:
Figure 9.3: Circuit diagram of 4x1 Mux using NAND gate
Truth Table
Select Enable Inputs Outputs

Inputs Input
Desired Observed
S1 S0 E I0 I1 I2 I3 Y Y
X X 1 X X X X 0
0 0 0 0 X X X 0
0 0 0 1 X X X 1
0 1 0 X 0 X X 0
0 1 0 X 1 X X 1
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1
1 1 0 X X X 0 0
1 1 0 X X X 1 1

Implementation of MUX using IC 74153:
Figure 9.4: Pin configuration of IC 74153
Truth Table
Select Enable Inputs Outputs

Inputs Input
Desired Observed
S1 S0 E I0 I1 I2 I3 Y Y
X X 1 X X X X 0
0 0 0 0 X X X 0
0 0 0 1 X X X 1
0 1 0 X 0 X X 0
0 1 0 X 1 X X 1
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1
1 1 0 X X X 0 0
1 1 0 X X X 1 1

Part 2 -Familiarize yourself with De-multiplexers:
De-multiplexers perform the opposite function of multiplexers. They transfer a small number of
information units usually one unit) over a larger number of channels under the control of selection
signals. The general de-multiplexer circuit has 1 input signal, n control/select signals and 2n output
signals. De-multiplexer circuit can also be realized using a decoder circuit with enable.
Circuit diagram of De-multiplexer:
Figure 9.5: Circuit diagram of de-multiplexer
Truth Table:
Enable DATA Select Outputs

Input Input Inputs
Desired Observed
E D S1 S0 Y3 Y2 Y1 Y0 Y3 Y2 Y1 Y0

Implementation of DEMUX using IC 74139 :
Figure 9.6: Pin configuration of IC 74139
Block diagram of (1x4) DEMUX:
Figure 9.7: Block diagram of 1x4 De- Mux
Truth Table:
Enable Select Outputs

Input Inputs
Desired Observed
E S1 S0 Y3 Y2 Y1 Y0 Y3 Y2 Y1 Y0
Post Lab Exercise:
1. What is a multiplexer and de-multiplexer?
2. What are the applications of multiplexer and de-multiplexer?

LAB # 10: Design and realization of comparator circuits
Objectives
 To learn about various applications of comparator

 To learn and understand the working of IC 7485 magnitude comparator
Equipment Required
 IC7400
 IC7410
 IC7420
 IC 7432
 IC 7486
 IC 7402
 IC 7408
 IC 7404
 IC 7432
 IC 7485
Lab Instructions

items:
 Lab objectives
 Results
 Conclusion
Part 1 -Familiarize yourself with Comparators
Magnitude Comparator is a logical circuit, which compares two signals A and B and generates three
logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high speed 4 bit magnitude comparator,
which compares two 4-bit words. The A = B Input must be held high for proper compare operation.
Lab Tasks-Part-1
Lab Task 1: 1-Bit Comparator
Design:
Truth Table:
Design:
Truth table:
Circuit Diagram:
Procedure:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.
Truth Table:
Post Lab Exercise:
1. What is a comparator?
2. What are the applications of comparator?
3. Design a 2-bit comparator using a single Logic gates?

LAB#11: Design and realization of decoders
Objectives
 To learn about working principle of decoder

 To learn and understand the working of IC 74LS139
 To learn about various applications of decoder
 To learn and understand the working of IC 7447
 To learn about types of seven-segment display
Equipment Required
 IC74LS139, IC 7400, IC 7408, IC 7432, IC 7404, IC 7410, IC 74147, IC 74148, IC

74157, IC7447,
 7-Segment display (common anode)
Lab Instructions
 The students should perform and demonstrate each lab task separately for step- wise
evaluation (please ensure that course instructor/lab engineer has signed each step after
ascertaining its functional verification).
enhancing their skills

following items:
 Lab objectives
 Results
 Conclusion
Part 1 - To realize a decoder circuit using basic gates and to verify IC 74LS139.
Decoder
A decoder is a combinational circuit that connects the binary information from 'n' input lines
to a maximum of 2n unique output lines. Decoder is also called a min-term generator/max-term
generator. A min-term generator is constructed using AND & NOT gates. The appropriate
output is indicated by logic 1 (positive logic). Max-term generator is constructed using NAND
gates. The appropriate output is indicated by logic 0 (Negative logic).
The IC 74139 accepts two binary inputs and when enable provides 4 individual active low
outputs. The device has 2 enable inputs (Two active low).
Lab Task 1: 2 to 4 Decoder:
Block diagram:
Figure 11.1: Block diagram of 2 to 4 decoder
Truth Table:
Table 11.1: Truth table of 2 to 4 decoder
Boolean expressions:
Circuit diagram
Figure 11.2: Circuit diagram of 2 to 4 decoder
Verify the Operation for 2 to 4-bit Decoder:
A B C Y0 Y1 Y2 Y3
0 0 0
0 0 1
0 1 0
0 1 1

Lab Task 2:
Verify the Operation for 3 to 8-bit Decoder:
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Part 2 - 7-segment static display
The Light Emitting Diode (LED) finds its place in many applications in these modern
electronic fields. One of them is the Seven Segment Display. Seven-segment displays contain
the arrangement of the LEDs in "Eight" (8) passion, and a Dot (.) with a common electrode,
lead (Anode or Cathode). The purpose of arranging it in that passion is that we can make any
number out of that by switching ON and OFF the particular LED's. Here is the block diagram
of the Seven Segment LED arrangement.
The Light Emitting Diode (LED), finds its place in many applications in this modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contain the
arrangement of the LEDs in "Eight" (8) passion, and a Dot (.) with a common electrode, lead
(Anode or Cathode). The purpose of arranging it in that passion is that we can make any number
out of that by switching ON and OFF the particular LED’s. Here is the block diagram of the
Seven Segment LED arrangement. LED's are basically of two types- Common Cathode (CC) -All
the 8 anode legs use only one cathode, which is common. Common Anode (CA)-The common leg for
the entire cathode is of Anode type. A decoder is a combinational circuit that connects the binary
information from 'n' input lines to a maximum of 2n unique output lines. The IC7447 is a BCD to 7-
segment pattern converter. The IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs
the relevant 7 segment code.
Diagram of seven-segment display
Fig 11.3: Seven segment display
Circuit diagram:
Verify the BCD to seven segment display:
Procedure

 Insert the appropriate IC into the Breadboard.
 Make connections as shown in the circuit diagram
 Verify the Truth Table and observe the outputs
Results:
BCD input Output logic levels Number

display
Table 11.4: Truth table of BCD-Seven segment
Post Lab Exercise:
1. What are the applications of decoder?
2. What is the difference between decoder & encoder?
3. What is the difference between decoder and de-mux?
LAB#12: Realization of flip flop operations
Objectives
 To understand the principle of operation of sequential circuit

 To differentiate between combinational circuit and sequential circuit.
 To get familiar with basic Flip flops
Equipment Required
 IC 7408
 IC 7404
 IC 7402
 IC 7400
Lab Instructions
enhancing their skills

following items:
 Lab objectives
 Results
 Conclusion
Truth Table verification of FF and conversion of one FF to another
Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation. The latch
(flip-flop) is a basic bi-stable memory element widely used in sequential logic circuits. Usually
there are two outputs, Q and its complementary value. Some of the most widely used latches
are listed below
SR LATCH:
S-R latch consists of two cross-coupled NOR gates. An S-R flip-flop can also be design using
cross-coupled NAND gates as shown. The truth tables of the circuits are shown below.A
clocked S-R flip-flop has an additional clock input so that the S and R inputs are active only
when the clock is high. When the clock goes low, the state of flip-flop is latched and cannot
change until the clock goes high again. Therefore, the clocked S-R flip-flop is also called
"enabled" S-R flip-flop.
A D latch combines the S and R inputs of an S-R latch into one input by adding an inverter.
When the clock is high, the output follows the D input, and when the clock goes low, the state
is latched.
Lab Task 1
S-R Latch
Figure 12.1: SR Latch Figure 12.2: Block diagram SR Latch
Truth table
Table 12.1: Truth table of SR Latch
Lab Task 2
S-R Flip Flop
Figure 12.3: SR Flip flop Figure 12.4: Block diagram SR Flip flop
Truth table:
Table 12.2: Truth table of SR Flip Flop
Lab Task 3
D- Flip Flop
The D-type flip-flop is a modified Set-Reset flip-flop with the addition of an inverter to
prevent the S and R inputs from being at the same logic level
Figure 12.5: Circuit diagram of D Flip flop

Truth Table:
Table 12.3: Truth table of D Flip Flop

Truth Table
CLK Input Output
D Qn+1 Q*n+1
Table 12.4: Truth table of D Flip Flop
Lab Task 4
JK- Flip Flop
The JK Flip-flop is similar to the SR Flip-flop but there is no change in state when the J and K
inputs are both LOW. The JK flip flop is basically a gated SR flip-flop with the addition of a
clock input circuitry that prevents the illegal or invalid output condition that can occur when
both inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK flip-
flop has four possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The
symbol for a JK flip flop is similar to that of an SR Bistable Latch as seen in the previous
tutorial except for the addition of a clock input.
Table 12.5: Truth table of JK Flip Flop

Truth Table:
Input Output States
CLK J K Qn+1 Q*n+1
Table 12.6: Truth table of JK Flip Flop
Post Lab Exercise:
1. What does the triangle in a flip flop mean?
2. What is difference between latch and flip-flop?

Lab# 13: Open Ended Lab (Design and implementation of Binary Counters)
Objectives:
 To implement a mod-8, mod-16 counters
 To develop digital circuit building and troubleshooting skills
 Learn to use Modern tool (Proteus Software) for Simulation of Digital Logic Circuits.
Description:
Using the background knowledge of Digital logic design, you are going to design a 3-bit (Mod 8) and
4-bit (Mod 16) counter
LAB PROCEDURE
Design and simulate your circuit

Construct the digital circuit you’ve designed to satisfy the requirements of your design
problem. You can choose any memory components. Use the pulsar switches to act as the clock
input and designing the counter circuit sketch it out on paper and then design the counter in
proteus. The output of a counters must be display on seven segment display. As always, include
a sketch of the schematic with digital component states for each logic you investigate. Explain
your analysis behind your design and conclusion of your findings
LAB # 14: Shift Registers
Objectives
To realize and study the types of Shift Register

 SISO (Serial in Serial out)
 SIPO (Serial in Parallel out)
 PIPO (Parallel in Parallel out)
 PISO (Parallel in Serial out)
Lab Instructions

following items:
 Lab objectives
 Results
 Conclusion
Theory
The Shift Register is another type of sequential logic circuit that can be used for the storage or
the transfer of binary data. This sequential device loads the data present on its inputs and then
moves or “shifts” it to its output once every clock cycle, hence the name Shift Register.
A shift register basically consists of several single bit “D-Type Data Latches”, one for each
data bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement
so that the output from one data latch becomes the input of the next latch and so on. Data bits
may be fed in or out of a shift register serially, that is one after the other from either the left or
the right direction, or all together at the same time in a parallel configuration.
The number of individual data latches required to make up a single Shift Register device is
usually determined by the number of bits to be stored with the most common being 8-bits (one
byte) wide constructed from eight individual data latches. Shift Registers are used for data
storage or for the movement of data and are therefore commonly used inside calculators or
computers to store data such as two binary numbers before they are added together, or to
convert the data from either a serial to parallel or parallel to serial format.
Lab Task 1:
Serial in Serial out (SISO) (Right Shift)
The data is shifted serially “IN” and “OUT” of the register, one bit at a time in either a left or
right direction under clock control.
Implementation of SISO Register:

Lab Task 2:
Serial in Parallel out (SIPO)
The register is loaded with serial data, one bit at a time, with the stored data being available at
the output in parallel form.
Implementation of SIPO Register:

Lab Task 3:
Parallel-in to Parallel-out (PIPO)
The parallel data is loaded simultaneously into the register, and transferred together to
their respective outputs by the same clock pulse.
Implementation of SIPO Register:

1. What is register?
2. What is the application of register?
3. What is the difference between shift right register and shift left register?

Lab # 01: Introduction To Basic Logic Gates & DLD Trainer: Objectives

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Lab # 01: Introduction To Basic Logic Gates & DLD Trainer: Objectives

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Lab # 01: Introduction to Basic Logic Gates & DLD Trainer

Lab Report Instructions

Part 1. Familiarize yourself with AM 2001 logic trainer:

Figure 1.1 AM 2001 logic trainer

State Monitors / LEDs:

Lab Task 1: Inputs Outputs

IC 7408 AND gate A B Desired Observed

Lab Task 3: Inputs Outputs

AND Gate IC (7408) XOR Gate IC (7486)

NAND Gate IC (7400)

NOT Gate IC (7404)

1. Explain what are the universal logic gates?

2. Define 0 and 1 in items of voltage values.

3. Explain what is a truth table?

Critical Analysis / Conclusion

Lab Report Instructions

Part 1 - Proteus (Simulation Software)

Figure 2.1 ISIS icon

Figure 2.2 Interface of Proteus software window

Figure 2.3 Pick Devices window in Proteus

Power supply and input signal Generator

Figure 2.7 Logic State in Proteus

Figure 2.8 Placing the devices in Proteus

Figure 2.9 Wiring devices to make a circuit

Take the components from Library by pressing the tab “Library”

Figure 2.11 Pick parts from library

Figure 2.12 Pick parts from library

Figure 2.13 Connection the components

Figure 2.14 Design of logic AND gate

Figure 2.18 Design of logic NOT gate

Figure 2.22 Design of logic XOR gate

2. Write Boolean Logic equation for function F2 in terms of the inputs A, B, C, D.

3. Verify the functionality of F1 and F2 on Proteus by comparing F1 and F2 in truth

( By Student about Learning from the Lab)

 Logic gates (IC) trainer kit.

Lab Report Instructions

Lab Task 1: Verification of NOT function

 Connect the circuit as per Figure 3.1.

Figure 3.1 NOT gate

Lab Task 2: Verification of AND function

 Connect the circuit as per Figure 3.2.

Figure 3.2 AND gate

Lab Task 3: Verification of OR function

 Connect the circuit as per Figure 3.3.

Figure 3.3 OR gate

 Connect the circuit as per Figure 3.4.

Figure 3.4 XOR gate

Lab Task 5: Verification of XNOR function

 Connect the circuit as per Figure 3.5.

Figure 3.5 XNOR gate

Part 2 - Implementing any logic expression by using only NOR gates

Lab Task 6: Verification of NOT function

 Connect the circuit as per Figure 3.6.

Figure 3.6 NOT gate

 Connect the circuit as per Figure 3.7

Figure 3.7 AND gate

Lab Task 8: Verification of OR function

 Connect the circuit as per Figure 3.8.

Figure 3.8 OR gate

Verify absorption theorem 𝑨 + (𝑨. 𝑩) = 𝑨

Draw circuit diagram

Verify absorption theorem 𝑨. (𝑨 + 𝑩) = 𝑨

Draw circuit diagram