Lab Manual Digital Logic Design | CEL-120

Faculty’s Name: Dr. Jhenazaib Lab Engineer: Mr. Abdul Mannan

Name: Khubab Hussain Enroll No: 03-134201-035

Objective(s):
 To construct half and full subtractor circuit.

Task 1: Half Subtractor Circuit Constructed with Basic Logic Gates. Draw half
subtractor circuit using basic logic gates.
Task 2: Full Subtractor Circuit Constructed with Basic Logic Gates.
Task 3: Draw the equivalent circuit of full subtractor using basic logic gates.
Task 4: Write the output of each gate.

Lab Grading Sheet :

Max Obtained
Task Comments(if any)
Marks Marks
1. 10

2. 10

3. 10

4. 10

Total 40 Signature

Note : Attempt all tasks and get them checked by your Lab Instructor

Department of Computer Sciences, BULC

Lab 07: Half and Full Subtractor Circuit

Objective(s):

“To construct half and full subtractor circuit”.

Tool(s) used:

 Multisim

Overview:

A binary subtractor is a decision-making circuit that subtracts two binary numbers

from each other to find the resulting difference between the two numbers.

Task 01: Time: 30 Minutes

Half Subtractor Circuit Constructed with Basic Logic

 A B � D BO
�
̅
1 0 0
0 0

1 1 1
0 1

0 1 0
1 0

0 0 0
1 1

Draw half subtractor circuit using basic logic gates.

Task 02: Time: 30 Minutes

Draw Full Adder Circuit Constructed with Basic Logic Gates

Truth Table

Input Output

Sum Carry out

A B C

0 0
0 0 0

1 0
0 0 1

1 0
0 1 0

0 1
0 1 1

1 0
1 0 0

0 1
1 0 1

0 1
1 1 0

1 1
1 1 1
Task 03: Time: 30 Minutes

Draw the equivalent circuit of full subtractor using basic logic gates. Construct the
circuit on breadboard as well.
 Task 04: Time: 30 Minutes

Write the output of each gate.

X Y Z X ⊕ Y Z ⊕ (X (X⊕Y) ((X⊕ RESUL

⊕ B)
¬X (X¬ )
NOT T
AND B Y)¬ )
AND Z
0 0 0 0 0 1 0 1 0 0

0 0 1 0 1 1 0 1 1 1

0 1 0 1 1 1 1 0 0 1

0 1 1 1 0 1 1 0 0 1

1 0 0 1 1 0 0 0 0 0

1 0 1 1 0 0 0 0 0 0

1 1 0 0 0 0 0 1 0 0

1 1 1 0 1 0 0 1 1 1