SUBSCRIBE @ VU with Dilshad Ahmad

Total marks = 20
Digital Logic Design Practical
(CS302P) Deadline
th
Assignment # 02 24 of January,
Fall 2022 2023

Please carefully read the following instructions before attempting the assignment.

RULES FOR MARKING

It should be clear that your assignment would not get any credit if:
▪ The assignment is submitted after the due date.
▪ The submitted assignment does not open or the file is corrupt.
▪ Strict action will be taken if the submitted solution is copied from any other student
or the internet.

You should consult the recommended books to clarify your concepts as handouts are not
sufficient.

You are supposed to submit your assignment in Doc or Docx format & EWB File (If required).
Any other formats like scan images, PDF, ZIP, RAR, PPT, BMP, etc. will not be accepted.

Topic Covered:

• Lab Work - Week # 09 - Building Logic Circuits using Multiplexers

• Lab Work - Week # 10 - Building Digital Logic Circuits using Decoders
• Lab Work - Week # 11 - Sequential Circuits

NOTE

No assignment will be accepted after the due date via email in any case (whether it is the case
of load shedding or internet malfunctioning etc.). Hence refrain from uploading assignments
in the last hour of the deadline. It is recommended to upload the solution file at least two days
before its closing date.

If you people find any mistake or confusion in the assignment (Question statement), please
consult with your instructor before the deadline. After the deadline, no queries will be
entertained in this regard.

For any query, feel free to email me at:

cs302p@vu.edu.pk

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 SUBSCRIBE @ VU with Dilshad Ahmad
Question Statement Marks (20)
You have been provided with a function table for a 4-Variable boolean function as given below:

Number A B C D F
0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 1

You are required to:

1. Generate the Boolean Expression for the Output (F) for the given table.
2. Draw the NAND Level Diagram using Electronic Workbench with the OUTPUT labelled with your
VU Student ID.

Note: Copied assignments will not be accepted. Student Must have to mention their VU Student ID in the shared circuit
diagram, otherwise, your assignment will be marked as a Copy Case as well.

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 SUBSCRIBE @ VU with Dilshad Ahmad
The simplified boolen expression is:

AB’CD’+AB’C’D+A’CD+BCD

The Nand Level diagram is following:

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