Advanced VLSI Design

Dr. Premananda B.S.

BITS Pilani
Pilani Campus
 BITS Pilani
Pilani Campus

MEL ZG623, Advanced VLSI Design

Lecture No. 11
Agenda

• Introduction/Review, Design issues

• Sequential logic circuit
• Dynamic latches and Registers
• Timing issues in clock systems
• Clock generation and distribution
• Asynchronous system design
• Interfacing circuits

BITS Pilani, Pilani Campus

Agenda Contd …

• Datapath subsystem design

• High speed computer arithmetic design
• Adders, Multipliers, Barrel shifter
• Logical efforts
• Optimizing logic circuits
• Wire design principles
• Deep submicron device engineering
• Scaling theory, geometrical/physical effects

BITS Pilani, Pilani Campus

Reference Books
• Jan M. Rabaey and A. Chandrakasan, “Digital Integrated
Circuits”, 2nd Edition, Prentice Hall Electronics and VLSI
Series.
• Ming-Bo Lin, “Introduction to VLSI systems A logic circuit
and system perspective”, CRC press. Taylor & Francis
Group.
• Neil H. E. Weste, David Harris, and Ayan Banerjee, “CMOS
VLSI Design” 3rd/4th edition, Pearson education.
• John P. Uyemura, “Introduction to VLSI Circuits and
systems” Wiley.
• John P. Uyemura, CMOS Logic Circuit Design Kluwer
Academic Publishers.
• …
BITS Pilani, Pilani Campus
 Adders
• Carry-Ripple Adder
• Adder/subtractor
• Mirror adder
• Carry-Skip/Bypass Adder
• Carry-Select Adder

• Conditional-Sum adder
• Carry-Save Adder
• Manchester carry-chain Adder
• Parallel-Prefix Adders
Conditional-Sum Adder

• The carry-select addition starts from single bit and

recursively doubling to n/2 bits,
• The first two rows consist of full adders and compute the
sum and carry-out assuming that the carry-in bits are 0
and 1, respectively.
• The rest of the adder is the sum-selection tree that
selects the proper sum bit.
8-bit Conditional-Sum Adder
Carry Save Addition
• A full adder sums 3 inputs and produces 2 outputs
– Carry output has twice weight of sum output
• N full adders in parallel are called carry save adder
– Produce N sums and N carry outs
X4 Y4 Z4 X3 Y3 Z3 X2 Y2 Z2 X1 Y 1 Z1

C4 S4 C3 S3 C2 S2 C1 S1
XN...1 YN...1 ZN...1

n-bit CSA

CN...1 SN...1
n-bit Carry-save Adder
• Used in the situations whenever multiple operands need
to be added.
• An n-bit CSA can accept three n-bit inputs and yield two
n-bit outputs, representing the sum and carry portions of
the three input operands, respectively.
• To obtain the true result, a carry-propagate adder (CPA)
is used to combine both output sum and carry together.
• CSA is also referred to as a 3:2 compressor (because it
counts the number of 1s in the three single-bit inputs and
indicates the result on the two single-bit outputs).
• In the multiplication section, many examples using CSAs
to construct efficient multipliers are concerned.
n-bit Carry-save Adder
CSA Application: Multi-input Adders
• Use k-2 stages of CSAs
– Keep result in carry-save redundant form
• Final CPA computes actual result
0001 X
0001 0111 1101 0010 0111 Y
+1101 Z
4-bit CSA 1011 S
0101_ C
0101_ 1011
0101_ X
5-bit CSA 1011 Y
+0010 Z
S
C
+
A
B
S
CSA Application: Multi-input Adders

0001 X
0001 0111 1101 0010 0111 Y
+1101 Z
4-bit CSA 1011 S
0101_ C
0101_ 1011
0101_ X
5-bit CSA 1011 Y
+0010 Z
01010_ 00011 00011 S
01010_ C
+
01010_ A
+ 00011 B
S
CSA Application: Multi-input Adders

0001 X
0001 0111 1101 0010 0111 Y
+1101 Z
4-bit CSA 1011 S
0101_ C
0101_ 1011
0101_ X
5-bit CSA 1011 Y
+0010 Z
01010_ 00011 00011 S
01010_ C
+
01010_ A
10111 + 00011 B
10111 S
Manchester Carry-chain Adder
• It uses a cascade of pass transistors to implement carry chain.
ci+1 = gi + pici

• Manchester carry style: (a) static circuit; (b) dynamic circuit

4-bit Manchester carry chain
Dynamic/Domino logic circuit
Parallel-Prefix Adder
• If lookahead is good, lookahead across lookahead!
– Recursive lookahead gives O(log N) delay
• Many variations on tree adders
PG Diagram Notation
Black cell Gray cell Buffer
i:k k-1:j i:k k-1:j i:j

i:j i:j i:j

Gi:k Gi:k
Gi:j Gi:j
Pi:k Pi:k Gi:j Gi:j
Gk-1:j Gk-1:j
Pi:j Pi:j
Pi:j
Pk-1:j
Brent-Kung
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0

15:12 11:8 7:4 3:0

15:8 7:0

11:0

13:0 9:0 5:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Sklansky
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0

15:12 14:12 11:8 10:8 7:4 6:4 3:0 2:0

15:8 14:8 13:8 12:8

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Kogge-Stone
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15:14 14:13 13:12 12:11 11:10 10:9 9:8 8:7 7:6 6:5 5:4 4:3 3:2 2:1 1:0

15:12 14:11 13:10 12:9 11:8 10:7 9:6 8:5 7:4 6:3 5:2 4:1 3:0 2:0

15:8 14:7 13:6 12:5 11:4 10:3 9:2 8:1 7:0 6:0 5:0 4:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Han-Carlson
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0

15:12 13:10 11:8 9:6 7:4 5:2 3:0

15:8 13:6 11:4 9:2 7:0 5:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Knowles
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15:14 14:13 13:12 12:11 11:10 10:9 9:8 8:7 7:6 6:5 5:4 4:3 3:2 2:1 1:0

15:12 14:11 13:10 12:9 11:8 10:7 9:6 8:5 7:4 6:3 5:2 4:1 3:0 2:0

15:8 14:7 13:6 12:5 11:4 10:3 9:2 8:1 7:0 6:0 5:0 4:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Ladner-Fischer

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0

15:12 11:8 7:4 3:0

15:8 13:8 7:0 5:0

15:8 13:0 11:0 9:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Comparison of Adder Architectures
Area vs. Delay of Adders
Summary
• Addition plays very important roles in arithmetic
operations, including subtraction, multiplication, and
division.
• The performance bottleneck of an n-bit adder lies on the
generation of carriers needed in all stages.
• To remove the bottleneck, a variety of addition
algorithms are proposed,
• carry-skip adder, carry-select adder, conditional-sum
adder, carry-save adder, parallel-prefix adders…
Agenda Contd …

• Datapath subsystem design

• High speed computer arithmetic design
• Adders, Multipliers, Barrel shifter
• Logical efforts
• Optimizing logic circuits
• Wire design principles
• Deep submicron device engineering
• Scaling theory, geometrical/physical effects

BITS Pilani, Pilani Campus

Multipliers
• Array Multiplier
• Carry-save multiplier
• Baugh-Wooley Multiplier
• Tree Multiplier
• Booth Multiplier
General Form
• Multiplicand: Y = (yM-1, yM-2, …, y1, y0)
• Multiplier: X = (xN-1, xN-2, …, x1, x0)

 M 1   N 1
 N 1 M 1
• Product: P    y j 2 j    xi 2i     xi y j 2i  j
 j 0   i 0  i 0 j 0
y5 y4 y3 y2 y1 y0 multiplicand
x5 x4 x3 x2 x1 x0 multiplier
x0y5 x0y4 x0y3 x0y2 x0y1 x0y0
x1y5 x1y4 x1y3 x1y2 x1y1 x1y0
x2y5 x2y4 x2y3 x2y2 x2y1 x2y0 partial
x3y5 x3y4 x3y3 x3y2 x3y1 x3y0 products
x4y5 x4y4 x4y3 x4y2 x4y1 x4y0
x5y5 x5y4 x5y3 x5y2 x5y1 x5y0
p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 product
4*4 Array Multiplier
Unsigned 4×4 (n x m) Array Multiplier
Carry-save Multiplier
Comparisons
• Propagation delay of critical path (first two rows
combined) of array multiplier is 9TFA
• Propagation delay of critical path of carry save multiplier
is 7TFA
• Generalize for n x m bit.
Parallel Multiplier
 Multiplicand: Y = (yM-1, yM-2, …, y1, y0)
 Multiplier: X = (xN-1, xN-2, …, x1, x0)

 M 1   N 1
 N 1 M 1
 Product:
P    y j 2 j    xi 2i     xi y j 2i  j
 j 0   i 0  i 0 j 0

Braun Multiplier
Only for unsigned multiplication
Structure of 4x4 Braun Multiplier

For n x n multiplier, n(n-1) adders are required

 Multiplier for Signed Numbers
• Baugh-Wooley Multiplier
• .
Simplified partial products
• .
Summary
• Array Multiplier
• Carry-save multiplier
• Baugh-Wooley Multiplier
THANK YOU

BITS Pilani, Pilani Campus