Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference (Jeju, Korea, 28-31 October 2018)
Design and Implementation of Reversible Logic
based RGB to Gray scale Color Space Converter
Sithara Raveendran, Pranose J Edavoor, Nithin Kumar Y. B., Vasantha M. H.
National Institute of Technology Goa, India
Email: (sithararaveendrann,pranose)@gmail.com, (nithin.shastri, vasanthmh)@nitgoa.ac.in
Abstract—Color space conversion is an age old technique used
to achieve ease in processing, feature extraction, compression and
storage of image and video data. One such color space conversion
is RGB to gray scale conversion. Gray scale representation of
images aids in reducing storage space and increasing speed of
operation. This paper presents a color space conversion scheme
using reversible logic gates. An RGB color space to gray scale
color space conversion using color channel averaging method
and color space desaturation method is implemented in this
paper. Reversible logic/computations have emerged as a major
alternative to decrease the power dissipation in digital circuits.
Reversible sub modules like 8-bit adder, comparator, shifter
etc are used to implement the color space conversion. The
implementation of reversible logic circuits was done and the
functionality verification was done on Kintex 7 FPGA platform.
The results are projected in terms of gate count, ancilla input,
garbage output and quantum cost for reversible implementation
and in terms of hardware utilization and power for FPGA. The
proposed reversible circuit complies with the color conversion
standards and can find application in any low power image and
video processing applications.
Keywords—Reversible logic, Color space conversion, RGB to
Gray scale, Reversible logic gates, FPGA.
I. I NTRODUCTION
In the present era of power hungry devices, quantum
technology has emerged as a promising technology. The main
theory behind which the quantum logic is based on, is the
law of conservation of energy. Law of conservation of energy
states that energy can never be created nor destroyed; rather
it can only be transformed from one form to another. The
fundamental law of conservation of energy is incorporated in
the design of systems, to be precise, the circuits in quantum
logic/ quantum technology[1]. Quantum technology has shown
promising results in power consumption of a circuit. Theoret-
ically it is proved that the quantum logic circuits does not
consume any power for internal computations.
R. Landauer[2] had stated in 1960s that irrespective of the
design technique, energy dissipation is incurred in irreversible
hardware circuits and this was due to the information loss. His
study showed that for each bit of information that is lost in
a computation in non reversible circuits, a minimum of kTln2
joules of energy(heat), is dissipated; where k= 1.38065051023
J per K is the Boltzmann constant and T is the absolute oper-
ating temperature of the computation. With further studies in
this area, Bennett established that circuits using reversible logic
gates can avoid the kT ln2 joules of energy dissipation[3]. With
this ground breaking theory, quantum circuits was considered
to be information-lossless circuits with the ability to reduce
the power dissipation in the form of heat.
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Efficient conversion in color space especially RGB to gray
scale color space conversion plays a key role in reducing the
computational complexity and cost for algorithms that find ap-
plication in computer vision. The reduction in computations is
achieved by reducing the color channels. The main challenges
involve preservation of details of color, luminance and edge.
Implementation of color space converter using reversible
logic nullifies the internal energy dissipation as it provides
computations that does not result in information loss. An RGB
to gray scale color space converter is presented in this paper
with two architectures - 1) color channel averaging and 2)
color space desaturation. Reversible circuit implementation has
been carried out and the efficiency of the circuit is measured
in terms of quantum cost(QC), gate count(GC), number of
ancilla inputs(AI) and the number of garbage outputs(GO). The
functional verification[4] is done on an FPGA using Verilog
HDL. The PSNR for each method is analyzed to measure the
efficiency of the reversible color space conversion circuits.
The paper is organized as follows. Section II introduces
the basic concepts of reversible circuit design. The proposed
architectures namely Color channel averaging method and
Color space desaturation method along with reversible logic
implementation is discussed in Section III. The results obtained
are presented in Section IV followed by conclusion in Section
V.
II. BASICS OF REVERSIBLE CIRCUIT DESIGN
Design and implementation of reversible circuits has to
comply with a set of rules[5][6] that differentiates it from the
conventional combinational circuits.
∗ Number of Inputs = Number of Outputs
∗ Circuit has to be logically reversible - unique mapping
between input and output.
∗ Circuit has to be physically reversible - circuits are
backward deterministic.
∗ Fan-out is not permissible in reversible circuits.
∗ Feedback paths should not exist in reversible circuits.
The design parameters and constraints to be considered while
designing reversible circuits are :
1) Quantum cost - The number of elementary quantum
gates required to implement a function.
2) Garbage Output - The output bits added to a re-
versible functional block to achieve reversibility.
3) Ancilla Input - The input bits added to a reversible
functional block to achieve reversibility.
4) Gate Count - The number of reversible gates used in
the reversible functional block.
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 Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference (Jeju, Korea, 28-31 October 2018)

QUANTUM QUANTUM R G B
GATE DELAY
REPRESENTATION COST

Not A x A’ 1 1 REVERSIBLE
8-BIT ADDER
Feynman A A 1 1
Cy1 Sum
B A B

A A REVERSIBLE
Toffoli B B 5 5 8-BIT ADDER
C AB C Cy2 Sum
A A
Fredkin 5 REVERSIBLE
B B 5
FULL ADDER
C AB C

A A 3
REVERSIBLE 10-BIT DIVIDER
B A C 6 6
HNFG
C B
D B D
GRAY COMPONENT
A A
Peres 4 4 Fig. 2: Architecture of Reversible Color Channel Averaging
B A B
C AB C

Fig. 1: Architecture of Reversible Color Channel Averaging A Half Sum

Feynman
B Full Sum

Cin Toffoli Fredkin Cout

I1 g1
The constraints on the designer while designing a reversible I2
Feynman
g2
circuit[7][13] is to keep the QC, GC, AI and GO to the
minimum as it reduces the hardware cost and complexity. The
Fig. 3: Reversible Full Adder
basic gates[8][11] that are used in the paper are briefed in Fig.
1.

III. P ROPOSED RGB TO G RAY-S CALE CONVERSION
CIRCUITS USING REVERSIBLE LOGIC
Complex image processing algorithms like computer vision
tasks, demands a high performance and low-power RGB to
gray-scale conversion circuits to reduce the computational
load on the channel. Several methods have been proposed
in the past for efficient color space conversion from RGB to
gray-scale. Widely used methods include averaging the values
at each color channel, desaturation of color space, weighted
sum method and other color-to-gray approaches[9][10]. Two
main color-space conversion schemes for RGB to gray-scale
conversion are used to realize the reversible hardware in this
paper, namely:
1) Color channel averaging method
2) Color space desaturation method
A. Color Channel Averaging Method
Averaging is the most common gray-scale conversion tech-
nique.
R+G+B
Gray Component = (1)
3 inputs to the divider are the 10-bit dividend(Dd ) and 10-bit
This method is considered to be the simplest method as it
is easy to implement and optimize the hardware. One of the
major drawbacks of this method is that the representation of
gray shades is not at par with the luminosity perception of
humans. Proposed reversible color channel averaging circuit
is as shown in Fig. 2.
Hardware required:
. 8-bit reversible adder for calculating sum of R and G
components(result will be 9 bits)
. 8-bit reversible adder to add B component to the sum
of R and G(result will be 9 bits)
. Reversible full adder to add the carry generated from
two 8-bit adders
. Reversible Divider circuit with 10 bit dividend and
divisor.
1) Reversible Adder: The full adder circuit used, is the
reversible adder proposed by Aditya et. al.[14] which has
minimum gates and depth. The full adder circuit is as shown
in Fig. 3.
8-bit reversible adder is implemented using 8 reversible full
adders. A Full adder has a GC of 4, AI of 2, GO of 3 and QC
of 12
Design Summary: An n-bit adder has a GC of 4n, AI of 2n,
GO of 3n and QC of 12n
2) Reversible Divider: A fixed point divider[15] is em-
ployed in the proposed architecture as shown in Fig. 4. The
divisor(Dv ). Quotient(Qu ) and remainder(Rm ) are the outputs.
Dd can be expressed in terms of Dv , Qu and Rm as shown
in Eq. 2.
Dd = Dv × Qu + Rm (2)
Division operation is performed by right shifting Dv by k bits
at k th iteration. If the remainder in k th iteration Rmk <Dv 2−k ,
the Quk is set to 1. If this condition is not met, Quk is set to

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 Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference (Jeju, Korea, 28-31 October 2018)

S=0 a10 a1 a0 d9 d2 d1 d0
R G B

2-input 11-bit Multiplexer 2-input 10-bit Multiplexer FAN-OUT

SELECT SELECT
GENERATOR
1
CLK
CLK R G B B G R
10-bits Reversible S1 S0 10-bits Reversible E
E REVERSIBLE REVERSIBLE
Left-Shift Register Left-Shift Register
HOLD2
S1 S a10 a1 a0 q9 q2 q1 q0 HOLD1 MAX MIN
1 0 0 0 0 0 0 ESTIMATOR ESTIMATOR
Peres
FG FG FG FG FG FG FG

0
r10 r1 r0
q9 q2 q1 q0 REVERSIBLE
8-BIT ADDER
0 SIG Control CLK

FG SIG GRAY COMPONENT

V9 V1 V0
EXTRACTOR

Divisor GRAY COMPONENT

0

FG FG FG FG
Fig. 5: Architecture of Reversible Color Space Desaturation

0 0 R7 0 0 R6 0 0 R5 0 0 R4 0 0 R3 0 0 R2 0 0 R1 0 0 R0
Augend Augend Cin
11 - bit Adder
MSB Sum 11-bit LSB DFG DFG DFG DFG DFG DFG DFG DFG
1

FG R7 R7 R6 R6 R5 R5 R4 R4 R3 R3 R2 R2 R1R1 R0 R0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DFG DFG DFG DFG DFG DFG DFG DFG

Fig. 4: Reversible Divider R7 R7 R6 R6 R5R5 R4 R4 R3R3 R2R2 R1R1 R0 R0

0 0 0 0 0 0 0 0

FG FG FG FG FG FG FG FG

th
0. The remainder for k + 1 iteration is estimated as in Eq. R7 R7 R6 R6 R5 R5 R4 R4 R3 R3 R2 R2 R1 R1 R0 R0
3.
Rk+1 = Rk − Dv × 2−k Quk (3) Fig. 6: 8-bit Fan-out Generator

Non restoring division is performed in this design. If Quk =

1, Rk+1 is estimated by subtraction and if Quk = 0, Rk+1 is
calculated by adding Dv to Rmk .
Design Summary: An n-bit divider has a GC of 18n+17, GO
of 11n+18 and QC of 61n+50.
B. Color Space Desaturation Method
Saturation of a color refers to how vivid a color is. It is
also a representation of the percentage of existence of that
particular color in that shade. If the saturation is zero, then it
will produce gray color. The brightness of a color refers to the
lightness of a color. White has 100% lightness and black has
0% lightness.
M ax(R, G, B) + M in(R, G, B)
Gray Component =
2 An n-bit adder has a GC of 3n, AI of 5n, GO of 0 and QC of
Desaturation refers to taking a color and converting it to
its least-saturated variant. Desaturation of a pixel involves
calculating the midpoint of maximum of (R, G, B) and
minimum of (R, G, B) as shown in Eq. 2. The end result
is a softer, flatter gray-scale image. Proposed Reversible Color
Space Desaturation circuit is as shown in Fig. 5.
Hardware required:
. Fan-out generator to create copies of R, G and B.
. Reversible Max estimator to find maximum of R, G
and B.
. Reversible Min estimator to find minimum of R, G
and B.
. 8-bit reversible adder.
. Gray component extractor to extract the significant
gray component(8 bits) from 9 bit adder output from
8-bit reversible adder.
1) Reversible Fan-out Generator: The reversible fan-out
generator as shown in Fig. 6 consists of 8 individual fan-out
generation unit. Each unit consists of two Double Feynman
Gate(DFG) and a single Feynman Gate(FG). Each fan-out
generator generates 6 copies of each color component.
(4)
5n
2) Reversible Max/Min Estimator: The reversible Min/
Max estimator is as shown in Fig. 7. In this stage, first R and
G are compared and the maximum/ minimum is calculated.
The output of Comparator acts as the select line for the 8 line
Min/Max Selector. The Max / Min value thus generated is
passed through a fan-out generator to obtain copy. This again
is passed through the second comparator to get the final Max/

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 Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference (Jeju, Korea, 28-31 October 2018)

TABLE I: Reversible logic parameters for individual blocks in color channel averaging and color space desaturation
Color Channel Averaging Color Space Desaturation
Design Block GC AI GO QC Design Block GC AI GO QC
Full Adder 4 2 2 12 Min/Max Selector 8 0 1 40
8-bit Adder 32 16 24 96 Fan-out Generator 24 40 0 40
Divider 197 115 128 660 Comparator 25 18 32 88
Complete color channel averaging module 265 149 178 768 Complete Color Space Desaturation module 138 146 66 376

TABLE II: FPGA implementation for individual blocks in color channel averaging and color space desaturation
Color Channel Averaging Color Space Desaturation
Total Power Total Power
Design Block Slice LUTs Design Block Slice LUTs
Dissipation Dissipation
Full Adder 2 2.131 Min/Max Selector 8 5.924
8-bit Adder 25 14.897 Fanout Generator 24 16.997
Divider 176 93.938 Comparator 24 12.708
Complete Color Channel Averaging Module 228 125.863 Complete Color Space Desaturation Module 149 82.955

Min value. The resultant Max/ Min value is selected using

another 8 bit Min/Max Selector.

R G

B R G R G B
Comparator
R >G
Min Max
Selector Selector (a) Pepper Original (b) Lena Original (c) Butterfly Original
SELECT
Min1 Max1
Fan out Generator B B Fan out Generator
Min1 Min1 Max1 Max1
Comparator Min Max Comparator
Min1 < B SELECT
Selector Selector SELECT Max1 > B

Min_Value Max_Value

Fig. 7: 8-bit Reversible Max/Min Estimator

(d) Pepper (e) Lena (f) Butterfly
Color Channel Color Channel Color Channel
Averaging Averaging Averaging
3) Reversible Min/Max Selector: The Max/Min selector
is as shown in Fig. 8.Maximum of the other two inputs will
directed to output named max. The SELECT input from the
comparator, decides the input to be directed.
An n-bit Max / Min Selector has a GC of 8n, AI of 0, GO of
n and QC of 5n

4) Reversible Adder and Gray component extractor: The

fuller adder circuit is as shown in Fig. 3. 8-bit reversible adder (g) Pepper (h) Lena (i) Butterfly
is used. Gray component extractor assigns the invalid bits as Color Space Color Space Color Space
garbage outputs and passes only the valid 8-bits as the gray Desaturation Desaturation Desaturation
equivalent for the pixel.
Fig. 9: Original and color space converted Images
SELECT SELECT SELECT SELECT_OUT
Fredkin

Fredkin

Fredkin

R0 max1 R1 max2 R7 max7

IV. R ESULTS
G0 min1 G1 min2 G7 min7
A. Reversible logic implementation Results

Fig. 8: Max / Min Selector Reversible logic implementation was done to extract the
delay and quantum cost of the proposed architectures.

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 Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference (Jeju, Korea, 28-31 October 2018)

The QC, AI count and GB count for individual blocks
and for complete color channel averaging and color space
desaturation modules are given in Table I.
B. FPGA Implementation Results
Functional verification of the proposed architectures for
RGB to Gray scale color space conversion using reversible
logic was done using Kintex 7 FPGA. The simulations
were carried out on Vivado 2016.4 and the design was done
using Verilog Hardware Description Language. The hardware
utilization for individual blocks are as show in Table II.
The hardware utilization and power consumption for pro-
posed architectures namely color channel averaging method
and color space desaturation method is also tabulated in Table
II. It can be see that the hardware utilization and power
consumption is more for color channel averaging module. The
color space converted images on FPGA platform for both is
as shown Fig. 9.
[9] Amy A. Gooch, Sven C. Olsen, Jack Tumblin, and Bruce Gooch,
“Color2gray: salience-preserving color removal”,ACM Transactions on
Graphics (TOG). ACM, 2005, vol. 24, pp. 634639.
[10] Yongjin Kim, Cheolhun Jang, Julien Demouth, and Seungyong Lee, ,
“Robust color-to-gray via nonlinear global mapping,” ACM Transactions
on Graphics (TOG). ACM, 2009, vol. 28, p. 161.
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logic gates, Theor. Comput. Sci., 2005, 334, (13), pp. 259274
[13] Lenin, G., Nor, S., Mohd, M., et al.: Design and synthesis of reversible
arithmetic and logic unit (ALU). IEEE Conf. Computer, Communications,
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1138.

V. C ONCLUSION
This paper proposes the architecture for a reversible logic
based color space conversion unit for RGB to Gray scale
conversion. Two architectures are proposed mainly color chan-
nel averaging method and desaturation method. The accuracy
of functional block for conversion unit was tested by using
FPGA using Verilog Hardware description language. It is
seen the Quantum cost for color channel averaging method
is 104% more than color space desaturation method.GC of
color channel averaging is 92% more when compared to color
desaturation method.Color space desaturation shows a 34%
reduction in Slice LUT and dissipates 34.4% less power when
compared to color channel averaging method. For randomly
distributed R, G, B values, color channel averaging method
will give better results while conversion when compared to
color space desaturation method. Both the methods are verified
thoroughly and can be the starting blocks for image processing
blocks using reversible logic.

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