2023 International Conference on Recent Advances in Science & Engineering Technology (ICRASET)
Digital System Design of ALU using Reversible
Logic Gates
2023 International Conference on Recent Advances in Science and Engineering Technology (ICRASET) | 979-8-3503-0692-7/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICRASET59632.2023.10420008
Ravi L S
Research Scholar, Adichunchanagiri University, BG Nagara
Assistant Professor, Rajeev Institute of Technology,
Hassan, Karnataka, INDIA
ravigowda1234@gmail.com
Abstract— In the integrated circuit designs, the Area,
Power dissipation and Time delay will play an important role.
The Speed will rises with decreasing the size of a computing
element and mean while heat dissipation will lowers with
decreasing power dissipation. Future technologies for quantum
computing will involve reversible logic, and reversible logic
gates reduce leakage power usage. Reversible logic gates were
used to design the arithmetic and logical unit (ALU) in this
research work. Electronic unit such as ALU’s are built upon
conventional or irreversible logic gates. Due to the saturation
of Moore’s law, alternating ways are formed where new
semiconductor materials and new methodologies have been
implemented. One such way is to use reversible logic gates
instead of irreversible logic gates. In this application of VLSI
design, reversible logic has significantly emerged in power
optimization technology. To validate functionality, each
suggested design was analyzed and simulated using cadence
virtuoso.
Keywords— Reversible Logic, Garbage Outputs, ALU,
Quantum Cost.
I. INTRODUCTION
The advancement of computer equipment has been
extremely successful during the last decade. Conventional
technologies, like MOS transistors, would reach new
heights as transistor density increased exponentially,
especially as power dissipation increased. To improve the
processing capability of the present generation, many
choices are necessary. Reversible logic is a technology,
which results in low leakage power dissipation in CMOS
circuits, low quantum technology and optical computing.
Garbage outputs and quantum costs will be decrease in the
reversible logic. Power dissipation is the major issue in
the conventional logic. Landauer, created a computer
device to handle the degrees of freedom that would
operate as a heat sink for the energy needed for
calculations, leading to mistakes in the calculations. Here,
1-Bit of information is lost will result in the dissipation of
KT*ln2 amount joules of energy, where T is the
temperature and K is defined as Boltzmann's constant. In
the combinational circuits, information will lost due to
more heat energy and hence once information is lost, it
cannot recover back in the conventional logic. The power
dissipation is directly related to number of bits lost in the
digital circuit throughout the operation and thus it yields
in circuit complexity [1].
Reversible logic circuits can be used to overcome the
complexity in the digital circuits. It accelerates the precise
computations and reduces the energy dissipation, if the
circuits are logically reversible. The reversible logic is
used in designing the logical circuits to reduce the power
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Naveen K B
Depatment of ECE
Adichunchanagiri University
BG Nagara, Mandya District, Karnataka, INDIA
naveenkb@bgsit.ac.in
dissipation. The Arithmetic and logic unit outputs are
designed from reversible logic.
II. DEFINETIONS ESSENTIAL RELATED TO REVERSIBLE
LOGIC
A. Garbage Outputs
The number of inputs and outputs can be balanced by
adding additional inputs or outputs as necessary to achieve
reversibility in certain situations. The quantity of outputs
needed to build a reversible n-input and k-output function is
known as garbage [2]. The relationship between the
quantity of garbage outputs and constant inputs is
demonstrated by the straight forward formula below.
+ / = + / (1)
B. Quantum Costs
The quantum cost of the circuit is its cost expressed in terms
of a basic gate.
C. Gate Level
This is a reference to how many circuit levels are necessary
to carry out the specified logic functions.
D. Logic Complexity
This is the total amount of logic operations that make up
a circuit is used to describe how many AND, OR, and
EXOR operations there are overall in a circuit.
The following are the main limitations on reversible logic
circuit design.
• Fan-outs are not permitted with reversible logic
gates.
• Reversible logic circuits ought to be as inexpensive
as possible.
• The design may be optimized to yield the fewest
number of trash outputs.
• For reversible logic circuits, a single constant input
is the minimum quantity needed.
III. REVERSIBLE LOGIC
Equal numbers of input and output lines with one-to-
one correspondence between the input and output lines are
defined as reversible logic gates. Here the output is
defined by inputs and in the same way inputs can also
retrieve from the outputs, hence this logic is said to be
reversible and all reversible logic gates have equal number
of input lines in the circuit and output lines [3] in the
 circuit. ALU has a wide range of outputs. If the n number Fig. 4. FeynmanGate Quantum Cost
of inputs and outputs in the logic gate have one-to-one
mapping, then the logic gate will be reversible. The inputs
and outputs of reversible logic gates is defined by defining C. Fredkin Gate
the input vector of the digital circuit (IV) and output vector This is the reversible logic gate, defined by 3-input lines
of the digital circuit (OV) is as shown below and 3-output lines. The logic block of Fredkin gate is shown
= 1, 2, 3, 4, 5 … . (2) in fig.5 and the quantum cost of Fredkin gate in 7, which is
shown in fig.6
! ! = !1, !2, !3, !4, !5 … . ! (3)
The above equations 1 and 2 defines the input and output
lines and clearly defines that both vectors are equal in the
reversible logic based digital circuit and hence the reversible
logic gates are used to designed the ALU block.
A. Toffoli Gate
Fig. 5. Fredkin Gate
It is a 3x3reversible logic gate with three outputs (P=A,
Q=B, and R=AB XOR C) and three inputs (A, B, and C).
The fig.1 represents toffoli gate [2], in that (a) represents the
logic block of toffoli gate and (b) represents logic circuit of
toffoli gate. The Quantum cost is 5 as shown in fig.1.

Fig. 6. Fredkin Gate Quantum Cost

D. HNG Gate
This HNG reversible gate has 4-inputs and 4-outputsas
shown in fig.7, it displays the input mapping (A, B, C, D)
and to the output mapping (P=A, Q=B, R=A ⊕ (B ⊕ C),
S=A ⊕ B.C ⊕A.B) and the quantum cost is 6 as shown in
fig. 8.
Fig. 1. Toffoli Gate &its Logic Circuit

Fig. 7. HNGGate

Fig. 2. Toffoli Gate Quantum Cost

B. Feynman Gate
The logic block of Feynman reversible logic gate is shown in
below fig.3, which has 2-input and 2-output lines. The
quantum cost of Feynman gate is 2 and it is shown in fig.4.

Fig. 8. HNGGate Quantum Cost

IV. PROPOSED METHODOLOGY

A. Existing System
The digital system design of ALU [4] is implemented
using conventional logic gates, which can be expend a
significant energy in the form of bits that can be erased
Fig. 3. FeynmanGate during logic operations and are constructed on un-optimized
parameters in terms of quantum cost, and garbage outputs.
The main drawbacks of existing system are logic complexity
which yields in more delay and power dissipation.
B. Proposed System
The implementations at the gate level, as well as the
logics employed to develop the design. The ALU systems are
designed using the fewest number of gates based on

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 reversible logic as possible. The problem of energy loss in
digital circuit design may be handled by utilizing reversible
logic circuits instead of traditional or conventional logic
circuits. In this design, two Fredkin gates, a 4*4 Toffoli gate,
and a Feynman gate are used to build the control unit. As the
whole adder unit, HNG gates are utilized. As seen in figure
7, the HNG gate's outputs R and S will result in the output F
and carry Cout. The quantum cost of this design is 22. There
are seven trash outputs and three constant inputs [5]. As seen
in table 1, it is capable of eight arithmetic operations and
seven logical operations. Setting S2 to logic 0 selects
arithmetic operations, whereas setting S2 to logic 1 allows
logical operations to be carried out [6].
The central processing unit (CPU) is also known as the
ALU. It is a key part of the computer system and conducts
both arithmetic and logic operations. An integrated circuit
found inside a CPU or GPU [7], commonly referred to as an
integer unit (IU), is the final part of the processor to conduct
computations. It is capable of carrying out the arithmetic
operations and logical operations, including addition,
Fig. 9. Proposed Block Diagram Reversible Logic based Arithmetic and Logic Unit
V. RESULT AND ANALYSIS
After the optimization and technology targeting phases of
the synthesis process, TL schematic is created.
Fig. 10. RTL Schematic of 8-Bit ALU Proposed
Reversible Logic Architecture
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subtraction, shifting, and Boolean comparisons (XOR, OR,
AND, and NOT operations) [8]. Additionally, bit wise and
mathematical operations may be performed on binary
integers. The data is sent to the computer's memory after the
ALU operations has completed processing the input. ALU
can do multiply operation [9] of two numbers and hence it
can handle integer calculations and the result is likewise an
integer. This is in addition to conducting addition and
subtraction calculations but ALU will not perform division
operation because as the consequences, these operation
produces floating point numbers which cannot operated in
ALU and floating point number will be utilized for non-
integer computations [10].
The ALU operations get more intricate, the cost of the
ALU increases since it consumes more CPU space and yields
in more heat generation in conventional logic. Hence the
information will be lost cannot recover back. To overcome
this problem ALU unit [11] is designed by using reversible
logic gates. The proposed ALU block was designed using
reversible logic gates as shown in figure.
Fig. 11. RTL Schematic of ALU Block
 Fig. 12. RTL Schematic of 8-Bit ALU Proposed Reversible Logic Architecture

TABLE I. PROPOSED ALU BLOCK RESULTS USING REVERSIBLE LOGIC

Existing Design Proposed Improvement in %

Parameters Design
[4] [11] [6] [4] [11] [6]

QuantumCost 32 40 52 30 6.25 25 42

GarbageO/Ps 7 9 12 6 6.14 33.3 50

ConstantI/Ps 3 4 2 1 66.6 75 50

NumberofCells 598 211 64.7

Total Power ( Watt) 0.108 0.112 0.118 0.107 0.1 0.5 1.1

Static Power (Watt) 0.104 0.106 0.110 0.104 0 0.2 0.6

Dynamic Power (Watt) 0.004 0.006 0.008 0.002 0.2 0.4 0.6

Delay (ns) 6.2 7.658 9.56 5.5 11 27 42.4

LUTs 25 27 31 23 8 14.8 25.8

The suggested arithmetic unit is compared in Table I with

previous designs results, showing improvements in all of
them, including the quantum cost and garbage outputs.
Thus the improvement percentage may approach a decrease
in garbage output of 50% and a reduction in quantum cost
of 42%. The dynamic power is reduced in the proposed
design.

TABLE II. ALU BLOCK DESIGN COMPARISION

Design Existing Design Proposed

Parameters
Parameters Design
[4]
Arithmetic Unit 32 30
Quantum Fig. 13. A comparison chart between the existing and
Cost Logical Unit 72 60 proposed designs' gate counts, trash output counts, and
quantum costs
Arithmetic Unit 7 6
Garbage
Outputs VI. CONCLUSION
Logical Unit 12 5
ALU design and its implementation are carried out
Arithmetic Unit 3 1
Constant based on reversible logic. The performance analysis of
Inputs Logical Unit 3 2 ALU design reduces garbage outputs in the system and
reduces quantum costs, reduces constant inputs and also the
Arithmetic Unit 598 211
Number of total number of cells in the design. Hence this yields in low
Cells Logical Unit 464 236 power dissipation and reduces the energy loss when
compare to conventional logic design. It has been
Table II, displays the ALU design comparison table. determined that the most promising method for building
The arithmetic, logical, and integration units' gate counts digital circuits is reversibility. ALU is an essential part of
and number of cells utilized are all much increased by the every system in the modern world, having a wide range of
recommended architecture. According to the comparisons uses in devices like calculators, smart phones, computers,
above, the ALU based reversible logic design exhibits the and more. The circuits should be garbage free. However,
significant enhancement from all design view points. their main purpose is to minimize the logic size or the
number of trash bits for a certain digital circuits. The

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 proposed designs can be elaborated and integrated for n-bit
ALU.
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