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Book Title Energy Systems, Drives and Automations
Series Title
Chapter Title Associative Array Architecture to Use Each Change of Series of Changes in Reversible Computing
Copyright Year 2020
Copyright HolderName The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte
Ltd.
Corresponding Author Family Name Chakrabortyor
Particle
Given Name Supriya
Prefix
Suffix
Role
Division
Organization AMITY University
Address Kolkata, India
Email schakraborty5@kol.amity.edu
Author Family Name Deb
Particle
Given Name Ankit
Prefix
Suffix
Role
Division
Organization AMITY University
Address Kolkata, India
Email

Abstract The energy-saving and quick computations are getting momentum among the researchers across the globe.
Reversible computing pays significant contributions from architectural, instructional and logical
perspectives in the literature. The present nature of data and complex applications involve many series of
changes, however, past data are compared for decision making or backtracking to draw the inference. In
this regard, dynamic dispatch with the lexical scoping was combined to access the series of changes that
were most recent advancement. However, the loosely coupled data structure is the fundamental drawback
to achieve the advantages of reversible computing in all directions. In this work, architecture is proposed
that uses the novel associative array in the underlying combination of dynamic dispatch with lexicographic
scope. The solution is abstracted as a memory management scheme. The procedural and object orientation
paradigm could use such proposed architecture in the programming level. The advancement of the
proposed work is supported with results.
Keywords Associative array - Register - Logical - Build time - Series of changes - Complex application
(separated by '-')
 Associative Array Architecture to Use
Author Proof

Each Change of Series of Changes

in Reversible Computing

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Supriya Chakrabortyor and Ankit Deb

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1 Abstract The energy-saving and quick computations are getting momentum among
2 the researchers across the globe. Reversible computing pays significant contributions
3 from architectural, instructional and logical perspectives in the literature. The present
4 nature of data and complex applications involve many series of changes, however,
5

7
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past data are compared for decision making or backtracking to draw the inference.
In this regard, dynamic dispatch with the lexical scoping was combined to access
the series of changes that were most recent advancement. However, the loosely
8 coupled data structure is the fundamental drawback to achieve the advantages of
9 reversible computing in all directions. In this work, architecture is proposed that uses
10 the novel associative array in the underlying combination of dynamic dispatch with
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11 lexicographic scope. The solution is abstracted as a memory management scheme.
12 The procedural and object orientation paradigm could use such proposed architecture
13 in the programming level. The advancement of the proposed work is supported with
14 results.
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15 Keywords Associative array · Register · Logical · Build time · Series of changes ·

16 Complex application

1 Introduction
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17

18 In recent days, reversible computation is getting the attention of the researchers. AQ1

19 In the entire history of computing, the loss of information and generation of heat
20 (energy) in the series computations observed. The real concern of the future market
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21 is the energy-efficient computations on behalf of global concern against the mammoth

22 energy exhaust for computing across the globe. This writ in the subsequent paragraphs
23 illustrates the specific technical gaps of reversing the series of computations and
24 provides an efficient solution in the successive section.
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S. Chakrabortyor (B) · A. Deb

AMITY University, Kolkata, India
e-mail: schakraborty5@kol.amity.edu

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer 1
Nature Singapore Pte Ltd. 2020
A. Sikander et al. (eds.), Energy Systems, Drives and Automations, Lecture Notes
in Electrical Engineering 664, https://doi.org/10.1007/978-981-15-5089-8_59
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 2 S. Chakrabortyor and A. Deb

Janus, procedural language thoroughly discusses the notion of reversible compu-

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25

26 tation in [1, 2]. Joule made the advancement [3] by incorporating object-oriented
27 language features for reversible computing. However, the Joule traditionally depends
28 on compiler-generated dispatch method to achieve reversibility.
29 Many related but different works have observed with their specific purpose and

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30 scopes in the field of reversible computing. [4] has attempted to extend the object-
31 oriented language features in reversible machines. The advantages of object-oriented
32 features have already realized as best practices in Industry for the past few years.
33 However, a related work, Taffoli network is space-inefficient for irreversible function
34 [5]. In this work, a simple space-efficient method has proposed with the extension of

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35 object-oriented features for reversing the computation. There is always a challenge
36 for the system that demands irreversibility; however, the reversible function does not
37 exist for the purpose.
38 In this regard, two closest work [6] that describes the complete description of the
39 semantics of reversible object-oriented programming language and [4] that attempted
40

41

42
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dynamic dispatch method using virtual method to achieve reversibility. Broadly, the
virtual method call consists of three steps—Lookup, Jump and Cleanup. However,
reversibility is not persistent and the use of program stack limits the flexibility of the
43 language, the series of changes are out of the scope of [4].
44 In this work, the extension of PISA [4] has proposed by introducing a hypothetical
45 heap memory on top of the object instance. The physical size of the heap memory is
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46 subject to number of fields in the object. A default value for each field is considered
47 in this work.
48 This writ organized as follows. The paper starts with a brief description of the
49 problems and challenges regarding reversible computing. The problem space has
been elaborated with a summary of the previous works in the Introduction section In
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50

51 this section, the specific shortcomings have been identified and technical extension
52 over the related work has been specifically mentioned. The proposed methodology
53 has discussed in detail with diagrams in Sect. 2 and its sub-sections. The proposed
54 claim has justified with the experimental details and results set in Sect. 3. A conclusion
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55 has drawn in Sect. 4. This paper has ended with the reference section.

56 2 Related Work
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57 Pendulum Instruction Set (PISA) is an instruction set for reversible computing. The
58 architecture is the modification of a cross between RISC and PDP-8 machines to
59 support reversibility. The notion is also to support energy efficiency computations.
60 The list operations are Add, Add Immediate, And Immediate, And-XOR, Branch
or Equal to Zero, Branch or Less Than Zero, Exchange, Or Immediate-XOR, Or
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61

62 XOR, Reverse Direction- Branch On Equal to Zero, Reverse Direction- Branch

63 On Less Than Zero, Rotate left, Rotate Right, Shift Left Logical-XOR, Shift Right
64 Arithmetic XOR, Exclusive OR, XOR Immediate. The authenticate syntax and usage
65 are available in [7].

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 Associative Array Architecture to Use Each Change … 3

The objective of the reversible computing is to support logical reversibility of

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66

67 operations and be implemented in a physically reversible technology. Freedkin [8]

68 demonstrated that billiard ball collisions are capable of simulating any logic function.
69 Energy recovering integrated circuit technique, e.g. Split-level charge recovery
70 logic reduces power consumption in logic circuits.

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71 The Pendulum processor is based on the MIPS R2000. MIPS R2000 lets the
72 mapping between instruction set architecture and register transfer level functional
73 architecture. The primitive model executes the instruction in five cycles where each
74 cycle resembles an appropriate pipeline stage. Two are dedicated to instruction fetch
75 and decode, while the three remaining stages perform register access, operation

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76 execution or memory access and register write back. Processor direction is controlled
77 by an external signal. The signal is synchronized with instruction execution so that the
78 currently executing instruction completes execution before the processor direction
79 is changed.
80 Read/Read−1 and Write/Write−1 imply the Pendulum register file and its connec-
81

82

83
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tion. Copying information from one location to another involves losing the informa-
tion, which was stored at the destination. Reading and writing information is therefore
done as a swap. Reading from a memory location clears it, and only memory loca-
84 tions, which are clear, maybe written to. This suggests that the inverse of the reading
85 a value, and the inverse of writing value is reading a value.
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86 3 Associative Array Architecture

In a broader sense, two types of approaches have been summarized for reversibility.
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87

88 In the first approach, the right-hand side is never reversible for expression if the
89 left-hand side is dependent on the right-hand side [9]. The further restrictions in the
90 variant of Janus also do exist, one variable is passed to only one parameter during
91 function call, and class field is not possible to pass in the method call of the same
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92 class. The major reason, the compiler does the simple compile-time analysis and
93 detection for reversibility.
94 In contrast to the above approach is the continuous checking for updating variables
95 on run time. The continuous checking is very time consuming, the slightly better
96 approach is the period checking. Still, the threshold value for the period is subject
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97 to determination and accuracy is in question for all the changes. In this regard, a
98 complete different thing is that compiler does not check the variable at run time if it
99 detects early that the update is irreversible.
100 To achieve the reversibility, object uses lexical scoping for class fields; such lexical
101 scoping implies that the object fields would create in program stack, but not in the
reversible heap memory.
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102

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 4 S. Chakrabortyor and A. Deb

3.1 Memory Management

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104 The proposed method extends the memory usage in PISA to use the reversible heap
105 memory. The constraint is that the proposed method is not applicable for objects
106 when created in system stack. When an object instance is called, instance is created

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107 in memory heap, and a corresponding memory heap is also created hypothetically on
108 top of the object. Initially, such memory heap would be filled by zero to conform to
109 the rule, no unused memory contains non-zero value [10]. In this work, an associative
110 array structure is proposed to contain the series of changes; such an associative array
111 structure is possible for both hardware and software (logical). In this section, we

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112 present the concept in terms of logical implementation. The memory is assumed to
113 be created just top of the data to accommodate the associative array into working
114 memory. The memory representation of the memory structure is specified in Fig. 1.
115 The associative memory contains the list of operations that is applied on data v in the
116 first level of the array. In the second level, the series of changed values are contained.
117

118

119
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Initially, the hash function is applied to reach to each operation. If the same
operation is applied multiple times, a time probed from the system clock is appended
with each operation to make applicable the hash function.
120 The challenge is to make optimize policy for the dynamic growth of the associative
121 array [11–19]. Several possible solutions exist. Few of them are described below:
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122 • Double the size—This is a completely logical scheme. The size of the associative
123 array can hold eight values. After exhausting the space, the growth of the asso-
124 ciative array will be doubled. The run time environment of the Instruction Set
125 manages such growth.
• Physical Implementation—Eight registers are internal could be used to accom-
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126

127 modate changes. After exhausting the space, the changed values are copied to the
128 logical unit of the associative array, and the registers are ready to handle the recent
129 changes. The size of the associative array grows with the multiple of eight. The
130 logical array works as a virtual unit of the physical registers of the associative
array. The schematic diagram of the scheme is depicted in Fig. 2.
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131

132 In accordance with the scope of the application, operations could be substituted
133 by values. However, it is strongly recommended that either a very small dataset is
134 chosen for the first-level associative array or each value must be unique. The result
135 section shows that this scheme is best suited for both the above situations. However,
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Fig. 1 The heap memory + v1

location of the object
- v2
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* v3
/ v4
% v5

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 Associative Array Architecture to Use Each Change … 5

+
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v1
- v2
* v3
/ v4
Eight
%

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Registers v5

Fig. 2 The interfacing between registers and logical unit in case of overflow of changes in registers

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136 results are degraded in other cases. In the subsequent paragraphs, the operations of
137 PISA are discussed to support the proposed scheme.
138 Each change contains the previous image of the update operation of the field of
139 the object. The previous image consists of V i implies the value and t j imply the
140 timestamp on which the update operation is occurred. If the system does not require
141

142

143
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reversing the operation without any time constraint, the ti could be omitted. For each
update operation, the previous image is inserted to the top of the list and points to
its immediate next node. The order of node implies the order of changes for the
144 field of object. The list has maintained by header node ObjectName.Fieldname. This
145 Objectame.Fieldname simply identifies the object and the corresponding field that
has changed in series during the lifetime of the object within heap memory. It is true
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146

147 that the object name must be unique in the environment to maintain the consistency
148 of reversibility. ObjectName.Fieldname refers to the latest value that has changed in
149 the field of the object.
150 In PISA, the following operations are documented to update the variable:
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152
151 ++, −, <==>, + =, − =, =, < − >

153 For a detail description of each operation, please refer [20]. In object-oriented
154 paradigm, the field of the object would be refereed with the following syntax:
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155 ObjectName.FieldName
156 The each PISA operation could be used after syntax ObjectName.FieldName to
157 apply the changes.
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158 3.2 Extended Operations and Code Generation

159 The field of the object as referred simply by adding the offset with the base address
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160 of the object. Such object-oriented syntax with the above-enlisted operations are
161 lexically determined the chance of update in the compilation time. In such cases, the
162 compiler generates the following extension code:

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 6 S. Chakrabortyor and A. Deb

--------------------------------------------------------------
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CREATENODE Nodei
ASSIGN Nodei Nodei-1
ASSIGN ObjectName.FiledNameIdentifier Nodei
163 MOVELOC ObjectName.Fieldname Node i
…..

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……
MOVEREG reg ObjectName.FieldName
--------------------------------------------------------------
164 To execute the operation, the following statements have been proposed that extend
the language PISA [20, 21] and translation schema from Jenus to PISA [10].

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165

166 The MOVEREG, MOVELOC are already defined as primitive operations in PISA.
167 The following two operations are advised to be included in the PISA instruction list:
168 • CREATENODE and
169 • ASSIGN.
170

171

172
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The proposed operation CREATENODE crates one new node in the heap memory
following the data structure in Fig. 2. ASSIGN operation provides old value to the
newly created node and adjusts the reference that refers to the newly created node
173 by the header node ObjectName.Fieldname. The change that affects the existing list
174 is as the old node NODEi becomes node Nodei-1 in the list.
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175 ObjectName.Fieldname and ObjectName.FieldName are different things. The first
176 one is the header that maintains the series of changes in heap memory whenas the
177 second one is the reference to the object in the working memory.
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178 3.3 Persistence of Old Image

179 In the documentation of PISA, instruction is not enlisted to store the values persis-
tently. The history of changes that are stored in the top of the object memory could be
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180

181 persistently stored using the integration with the R compiler. The modern R package
182 reader is fast and provides both a wide range of file formats and functions to store
183 values persistently. The R compiler translates the R source code into assembly code
184 of PISA.
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185 4 Experiment and Results

186 A simulation with the proposed techniques has done to generate the result with the
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187 following characteristics:

188 Transistor density 180 × 106 transistor/cm2
189 Chip Size before subsequent shrinks 750 nm2

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 Associative Array Architecture to Use Each Change … 7

On chip local Clock Frequency 10 GHz

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190

191 Supply Voltage for Minimum Logic power 0.6–0.5

192 Maximum power consumption for high-performance processor with heat sink
193 75 W
194 µP drawn channel length 35 nm

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195 DRAM ½ pitch 50 nm
196 T ox equivalent < 1 nm
197 CV/I delay 3–4 ps
198 VT 3σ varia. 40 ± mV
199 Src./drn. Junction depth 10–20 nm

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200 The above values have used to examine the reversibility of the experiment enlisted
201 in Table 1. The column attribute of Table 1 enlisted the details of the experiments
202 and adjacent columns contain the corresponding number.
203 Result of the experiments has depicted in Fig. 3.
204 Reversibility with series of changes has achieved. In the simulation, the heap
205

206

207
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memory for the reversibility has created in multiple of 512 KB. The determina-
tion of the size of heap memory for reversibility at compilation time is possible
only approximately. Figure 3 shows the reversible time consumes less time with the
208 increase number of updates. In accordance with the exhaustive number (400) update
209 operations as an average of 33.33% of time decreased for reversibility.
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210 The access result of different schemes (Logical and Register) following three
211 scenarios are depicted in Fig. 4:
212 • The first-level operations are small comparing over large dataset,
213 • The first-level operations are large enough but unique,
• The first-level operations are large enough but not unique.
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214

Table 1 Details of the experiment

Attributes Number
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Number of objects 5 10 15 20
Existing number of fields 15 30 45 60
Number of update in the same field 5 10 15 20
Number of update in total number of fields 25 100 225 400
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Fig. 3 Reversible time in ms 600

against the number of update 500
in total number of fields 400
Time

300
200
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100
0
25 100 225 400
Number of update in total number of fields

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 8 S. Chakrabortyor and A. Deb

20000
Author Proof

Logical Register
15000 implementation implementation
10000

5000

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0
Runtime (s) Memory (bytes) Runtime (s) Memory (bytes)
a
20000

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Logical Register
15000 implementation Implementation

10000

5000

20000
0
Runtime (s) Memory (bytes)
b
DP Runtime (s) Memory (bytes)

Logical Register
15000 implementation Implementation
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10000

5000

0
Runtime (s) Memory (bytes) Runtime (s) Memory (bytes)
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c
Fig. 4 a The runtime performance comparison for small set of operations (8) between logical and
register implementation on 541,450,384 Bytes with 32,768 changes. b. The runtime performance
comparison for large set of unique operations (1000) between logical and register implementation
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on 541,450,384 Bytes with 32,768 changes. c. The runtime performance comparison for large set
of redundant operations between Logical and Register Implementation on 541,450,384 Bytes with
32,768 changes

215 For each test, three run times have been tested and shown in different colors. The
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216 data set size remains the same, only synthetically design according to the requirement
217 of the above three scenarios.
218 The build time of the associative array is a major constraint. The choice between
219 logical or register implementation is dependent on the performance requirement of
220 the application and the scenarios mentioned above. A build time (s) on the same set
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221 of data is depicted in Fig. 5.

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 Associative Array Architecture to Use Each Change … 9

Fig. 5 The build time

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4000
comparison between logical- 3000
and register-based

Sec
associative array 2000
1000
0

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100 500 1000 1500 22000 2534 32768
Number of First Level Data or Operations
Logical Build Time (s) Regiater Build Time (s)

5 Conclusion

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222

223 The associative array implementation outperforms the performance requirement for
224 a series of changes on large data set. The choice of implementation of the associa-
225 tive array is dependent on the scenario and performance requirement of the appli-
226

227

228
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cation. For the unique set and small set of operations, register implementation is
60% better in performance over logical whereas for non-unique large set of opera-
tions the performance of register implementation degraded substantially over logical
229 implementation.

230 Acknowledgements This document is prepared in support of the resources of AMITY University
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231 Kolkata.

References
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232

233 1. Yokoyama T, Axelsen HB, Glück R (2008) Principles of a reversible programming language.
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AQ1 Please check and confirm if the author names and initials are
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