Reversible High Speed Binary Content Addressable
Memory array design using Transmission Gate
2023 3rd International conference on Artificial Intelligence and Signal Processing (AISP) | 979-8-3503-2074-9/23/$31.00 ©2023 IEEE | DOI: 10.1109/AISP57993.2023.10134833
Logic
1 Alekhya Yalla, 1 Umakanta Nanda, 1 Chandan Kumar Pandey and 2 Shujun Ye
1 School of Electronics Engineering, VIT-AP University, Amaravati, 522237, Andhra Pradesh, India.
2 Advanced Research Institute of Multidisciplinary Sciences, Beijing Institute of Technology, Beijing 100081, China
Abstract—In this work, Energy efficient Binary content ad-
dressable memory (BiCAM) is designed using reversible logic
which is in high demand in fields of quantum computing, nano
technology, data centric computing, software-defined networks
and wide variety of high speed applications. BiCAM performs
search operation in a single clock cycle. Binary content address-
able memory (BiCAM) design based on reversible logic reduces
power dissipation. Due to minimum heat dissipation, Reversible
logic has gained its interest in recent years. A novel design
of BiCAM array using reversible logic gates with transmission
gate logic improves speed and reversibility ensures low power.
The proposed reversible logic based 4x3 BiCAM array using
transmission gates is implemented using mentor graphics at
130nm technology with Vdd=1.2V shows 95.2% efficiency in
power compared to CMOS based BiCAM design. All reversible
logic gates used in BiCAM design as analysed using transmission
gate logic and compared with conventional gates.
Index Terms—BiCAM, Reversible logic, SRAM, Quantum cost,
energy efficiency, Low power
I. I NTRODUCTION
Binary content addressable memory (BiCAM) is a special
type of memory used to perform search operation in single
clock cycle [1]. BiCAMs are used in applications like data
compression, networking, in-memory computing and neural
networks [2]. Computer networking performs look up table
function in a single clock cycle [3]. BiCAM operates at
high-speed compared to other memories but heat dissipation
is more due to which power dissipation is high [4] [5].
Increase in power dissipation effects junction temperatures
of the chip and also reduces performance [6]. So proposed
work investigates on designing reversible logic based BiCAM
cells using transmission gate logic. Information lost due to
every computation will generate heat in the system [7]. The
information will loss when the data transmit from input to
output [8].
According to R. Landauer’s research in the 1960’s, Energy
lost for every computation will be KTln2 Joules and it will
be dissipated in the form of heat, where K is the Boltzmann’s
constant and T is the operating temperature [9]. According to
Bennett, Heat dissipated is zero when a circuit is designed
using reversible logic, If information lost is zero then such
circuits are called reversible [10]. Reversible logic devices
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are used in the design and implementation of nanotechnology
and quantum computing [11]. Design challenge is to design
a reliable system with high integrity of signal [12]. Power
consumption of circuits can be reduced by using reversible
logic [13].
Reversible logic allows us to generate outputs from inputs
and vice versa which is known as logical reversibility [14]. In
BiCAM cell, power dissipation increases during matching op-
eration due to its high-speed characteristics [15]. So, proposed
work uses reversible logic gates using transmission gate logic
for designing BiCAM in order to improve energy efficiency,
Quantum cost, the number of garbage outputs and delay.
The rest of this work is arranged as follows. Section 2
represents review work on BiCAM. Section 3 shows simula-
tion and analysis of reversible logic gates implemented using
transmission gate logic and 4X3 BiCAM array. Section 4 and
5 describes about discussion and conclusive summary.
II. R ELATED W ORKS
A technique was proposed to reduce power consumption
of match lines contains addressable memories called selective
pre-charge technique [16]. In this work, the match line is
separated into two segments [17]. In the first segment, the
search operation is conducted for first few bits of a word. In
other words, a small portion of the CAM cell is searched.
After this if the data is found in this first search, then
remaining bits searching operation will be activated in the
second search. As per it’s name, CAM is a storage memory,
where the conventional memory access is not followed where
the memory address is required, rather the content of the
memory is required here to access the memory block. Here
the CAM first receives the input word and then search it in
the table of data words present in the BiCAM. If the data
is found in the table, the CAM returns the address where
searched word is stored. The proposed reversible logic gate
based BiCAM design using transmission gate logic improves
energy efficiency of memory without degrading speed.
Fig. 1: Input-Output mapping and truth table representation of
Fredkin gate

III. I MPLEMENTATION OF 4 X 3 B INARY C ONTENT

A DDRESSABLE M EMORY ARRAY USING R EVERSIBLE
L OGIC G ATES
A. Fredkin Gate
It is a Universal gate which can be programmed as various
logic gates. It has one to one mapping as in Fig. 1. The input
and output vector are denoted as I (A, B, C) and O (P, Q, (a) Schematic of Fredkin gate using CMOS Logic
R). The output of Fredkin gate is denoted as P=A, Q=AB
xor AC and R=AC xor AB. Quantum cost of a Fredkin Gate
is 5. It is also called “CONTROLLED SWAP GATE”. Truth
table and block diagram of Fredkin gate is as in Fig. 1. The
following Fig. 2a and Fig. 2b shows schematic of Fredkin
gate implemented using both CMOS and Pass Transistor logic.
Transient analysis of Fredkin gate is simulated at Vdd=1.2V
is indicated in Fig. 3.
B. Feynman Gate
Feynman Gate is also called as copying gate or controlled
NOT gate or fan-out gate. It is one of reversible gate which
can act as buffer. The input vector is I(A, B) implements logic
functions P=A, Q=A xor B using Truth table shown in Fig. 4.
Here B acts as a control signal and generated complemented
output if B=1. The outputs are defined by Quantum cost of a
Feynman gate is 1. Feynman Gate can be used as Quantum xor
gate. This gate is used for duplication of outputs. Schematics
of Feynman gate using CMOS logic and Transmission gate
logic are shown in Fig. 5a and Fig. 5b. Transient simulation
of Feynman gate is performed at Vdd=1.2V as in Fig. 6.
C. Peres Gate
The inputs are denoted with A, B, C and outputs are
represented as P = A, Q = A xor B and R=AB xor C using
truth table as in Fig. 7. Quantum cost of a Peres Gate is
4. In BiCAM cell design, Peres Gate is used as number of
primitive gates required to realize circuit are less. Peres gate
is implemented using CMOS and Transmission gate logic as
in Fig. 8aand Fig. 8b. Fig. 9 shows transient simulation of
Peres gate is performed at Vdd=1.2V.
D. Toffoli Gate
Toffoli Gate is a self-reversible gate. It is a 3x3 mapped
logic function with input and output vectors indicated as I (A,
B, C) and O (P, Q, R). In Toffoli gate two inputs B and C are (b) Schematic of Transmission gate logic based Fredkin gate
unchanged and other input A inverts when B=1 and C=1. The
Fig. 2: Fredkin gate implemented using CMOS and Transmis-
sion Gate Logic

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 Fig. 3: Transient simulation of Fredkin Gate at Vdd=1.2V

(a) Schematic of CMOS logic based Feynman gate

Fig. 4: Input-Output mapping and truth table representation of

Feynman gate

outputs are defined by P=A, Q=B, R=A.B XOR C according

to truth table in Fig. 10. Quantum cost of a Toffoli Gate is
5. Schematics of Toffoli gate implemented using CMOS and
Transmission gate logic are shown in Fig. 11a and Fig. 11b .

E. 4X3 BiCAM Array design using reversible logic gates

BiCAM cell consists of 5 reversible gates. They are Fredkin,
three Feynman gates and Peres gate as in Fig. 13. SRAM cell
designed using Fredkin and Feynman gate is used to store
data [18][19]. Search line is given as input to 2x2 Feynman (b) Schematic of Transmission gate logic based Fredkin gate
gate. Ex-or of data input and search line is given as input to Fig. 5: Feynman gate implemented using CMOS and Trans-
one more 2x2 Feynman gate. Search line data is compared to mission Gate Logic
data stored in cell, if both the data are same then data will
be passed to next BiCAM cell of same column. Here, A 2x2
Feynman gate with constant input 1 is used as NOT gate.
Peres gate is used to compare match line data from current
state and previous state. If both are low then output will be
low. Fig. 14 shows 4x3 BiCAM array formed by connecting all
the peripheral circuits and BiCAM cell, with match-line sense
amplifiers and Encoder circuit. Transient analysis is performed
for BiCAM array as in Fig. 15.

IV. R ESULTS AND D ISCUSSIONS

All the simulations mentioned above are performed using
Mentor Graphics tool at 130nm technology with Vdd=1.2V.
This tool supports full custom Integrated circuit layout. Mentor
graphics tool is a computer aided design as ASIC’s approach. Fig. 6: Simulation analysis of Feynman Gate at Vdd=1.2V
This is to employ design and simulate new ideas in IC’s before

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Fig. 7: Input-Output mapping and truth table representation of
Peres gate
(a) Schematic of CMOS logic based Peres gate
(b) Schematic of Transmission gate logic based Feynman gate
Fig. 8: Peres gate implemented using CMOS and Transmission
Gate Logic
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Fig. 9: Simulation analysis of Peres Gate at Vdd=1.2V
Fig. 10: Input-Output mapping and truth table representation
of Toffoli gate
going to the consuming and expensive process of chip fabri-
cation. Using Mentor Graphics’ design environment S-Edit,
one can enter designs in schematic or Verilog-A format, and
then move on to simulate in eldo simulator. Eldo simulation
is used to put some source at the input to get IV curve, once
u get that in EZ waves, there are tools built in to EZ wave to
calculate different parameters.
BiCAM array is implemented using reversible logic gates as it
dissipates zero heat virtually if a system is able to return to its
initial state. Reversible logic gates have one to one mapping
between inputs and outputs. It has to be inverse or dual. All
the simulations of reversible gates is carried out and compared
as shown in Fig. 17. Power dissipated in reversible logic
gates is further reduced by implementing reversible gates in
CMOS and Transmission gate logic. It is observed that power
dissipated is improved using Transmission gate logic by 95.2%
compared to CMOS logic for Fredkin Gate. Power Delay
Product of two logic’s is compared for Feynman gate, it shows
that Transmission gate logic has improved efficiency. Peres
gate simulation shows that power dissipation has improved by
98.9% for transmission gate logic compared to CMOS logic.
It is observed that power is improved using Transmission gate
logic by 95.2% compared to CMOS.
A 4x3 BiCAM array is implemented using CMOS and trans-
mission gate logic, it is observed that number of transistors
are reduced using transmission gate logic to 728 where using
CMOS logic is 1264. 98.6% efficiency in PDP is achieved
using transmission gate logic over CMOS logic as shown
 Fig. 13: BiCAM cell design using various reversible logic
gates
(a) Schematic of CMOS logic based Toffoli gate

Fig. 14: Schematic of 4x3 BiCAM array using reversible logic

gates
(b) Schematic of Transmission gate logic based Toffoli gate
Fig. 11: Toffoli gate implemented using CMOS and Transmis-
sion Gate Logic

Fig. 15: Transient simulation of 4x3 BiCAM array using

Fig. 12: Transient simulation analysis of Tofolli Gate at reversible logic gates at Vdd=1.2V
Vdd=1.2V

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Fig. 16: Power Delay Product of reversible BiCAM array
design using transmission gate logic simulated at Vdd=1.2V
Fig. 17: Power Delay Product of reversible logic gates is
compared by simulating at Vdd=1.2V
in Fig. 16. The total quantum cost and power dissipation of
the proposed reversible logic based transmission gate BiCAM
cell is reduced compared to conventional CMOS logic based
BiCAM cell.
V. C ONCLUSION
In this paper, using BiCAM cells a 4x3 reversible logic
based BiCAM array with improved speed using transmission
gates has been designed operating with Vdd=1.2V at 130nm
technology. It is observed that performance indices like
quantum cost, garbage output, delay, constant inputs and gate
count are reduced compared with conventional CMOS based
BiCAM array. Power delay Product of proposed BiCAM
array is improved by 98.6% using transmission gates in
reversible logic gates ensuring improved speed with low
power dissipation due to its reversibility. An overall decrease
in PDP for BiCAM cells is making it best suitable for high
performance and low power applications. operation.
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