RAJEEV INSTITUTE OF TECHNOLOGY

VISVESVARAYA TECHNOLOGICAL UNIVERSITY

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION

A PHASE-1 PRESENTATION
ON
“Design and Implementation of carry Look-ahead adder using
reversible Logic gates”
Under the Guidance of:
Mr. Ravi L S
Assistant professor, Presented by:
Dept. of ECE, Ms. Dhamini S L (4RA20EC006)
RIT , Hassan Ms. Bhoomika N (4RA21EC400)
Ms. Shashikala M k (4RA21EC405)
Co-guide:
Ms. Supriya Ananth K A
Assistant professor,
Dept. of ECE,
1
RIT , Hassan
CONTENT:-

 INTRODUCTION
 LITERATURE SURVEY
 PROBLEM FORMULATION
 OBJECTIVES
 METHODOLOGY AND FLOWCHART
 SOFTWARE REQUIREMENTS
 APLLICATION AND ADVANTAGES
 REFERENCES

2
Introduction:-
Carry look-ahead adder are fastest adder of all adders because it calculates the
carry bits before the summation.
Carry look-ahead adder actually determines the carry bit by two modules first is
“generate a carry” and second is “propagate a carry”.
Reversible circuits are effectual than irreversible because of information loss
which leads to energy loss.
Due to information loss in irreversibility, it dissipates more power. To reduce
power, circuit designed with reversible logic.
 At last, reversible circuits can be viewed as distinct instance of quantum circuits
since quantum progression must be reversible.
Literature Survey:-
Neela Shirisha et al., (2021) - “Design of a reversible Carry Look-Ahead Adder
using Reversible Gates” this paper proposed a novel design methodology of a
reversible nbit carry look-ahead adder (RCLA) circuit
Agarwal K. K et al., (2020) - “Design and implementation of reversible carry look
ahead adder and array multiplier” this paper proposed that logical irreversibility is
associated with physical irreversibility
Bennett C H (2019) - “Logical Reversibility of Computation” this paper proposed
that if a computation carried out in Reversible logic zero energy dissipation is
possible, as the amount of energy dissipated in a system is directly related to the
number of bits erased during.
Majid Haghparast et al., (2019) - “Design of a Compact Reversible full Adder
Using Dynamic Programming” this paper proposed a design for a new reversible
full adder circuit that requires only 1 reversible MKG gate and produces 2 garbage
output.
Problem Formulation:-
 Existing System: - Though the paper considered a reversible design of carry look-ahead
adder, it was actually the representation of carry lookahead adder using quantum gates. As
the existing design had a huge number of gates and complex circuit structure, it affected
severely on the adder circuit in terms of number of gates, quantum cost, garbage’s and delay

 Proposed System: - These deals with the Design and operation of the proposed look ahead
carry adder architecture using Peres gate based on the existing adder architecture. The
proposed architectures are implemented by replacing the three block’s (Peres full adder)
Peres gates and Peres full adders with reversible logic gates to obtain the better performance
compared to conventional logic
Objectives:-
Efficiency: To create an adder circuit that operates with reduced
power consumption and minimal heat dissipation by utilizing
reversible logic gates.
Speed: Faster computations
Gate Optimization:Reversible gates offer potential for optimization in
terms of gate counts and circuit structure.
Comparative Analysis: Conducting a comparative study between
traditional adders and the reversible gate-based CLA in terms of
performance, power consumption, area utilization to showcase the
advantages and limitations of using reversible gates
Methodology:-
Software Required:-
• Xilinx ISE 14.7
Application and Advantages:-
Applications:-
Quantum Computing
Low-power Computing
Cryptographic Systems
Advanced Computing Architectures
Error Correction
Emerging Technologies
Advantages:-
Energy Efficiency
Information Conservation
Improved Performance
Scalability
Compatibility with Emerging Technologies
Reference:-
• [1]. Neela Shirisha., Choudhary, M. P., Jangid, H. K., & Kasera, A. (2021). Design and implementation
of reversible carry look ahead adder. International Journal of Advanced Research in Basic Engineering
Sciences and Technology (IJARBEST), 3(Special Issue 23).
• [2]. Agarwal k k., Sworna, Z. T., & Babu, H. M. H. (2020). “Design and implementation of reversible
carry look ahead adder and array multiplier” In 29th International Conference on VLSI Design and 2016
15th International Conference on Embedded Systems (VLSID). Kolkata, India.
• [3]. Majid Haghparast., & Babu, H. M. H. (2019). Design of a Compact Reversible Carry Look Ahead
Adder Using Dynamic Programming. In 28th International Conference on VLSI Design. Bangalore,
India.
• [4]. Prashanth, N. G., Savitha, A. P., Anadaraju, M. B., & Nuthan, A. C. (2019). Design and Synthesis of
Fault Tolerant Full Adder/Subtractor Using Reversible Logic Gates. International Journal of Engineering
Research and Applications (IJERA).
• [5]. Raghu kanth., & Umamaheswara, G. (2018). Implementation of Ripple Carry and Carry Look
Ahead Adders Using Reversible Logic Gates. International Journal of Applied Engineering Research.
• [6]. Rajmohan, V., & Ranganathan, V. (2017). Design of counter using reversible logic. In 3rd
International Conference on Electronics Computer Technology. Kanyakumari, India.