CINTI 2011 • 12th IEEE International Symposium on Computational Intelligence and Informatics • 21–22 November, 2011 • Budapest, Hungary

Swarm Intelligence Based Sizing Methodology for

CMOS Operational Amplifier

Revna Acar Vural, Student Member, IEEE, Tulay Yildirim, Member, IEEE
Dept. of Electronics and Communications Engineering
Yildiz Technical University
Istanbul, Turkey
{racar,tulay}@yildiz.edu.tr

Abstract— An efficient design of optimal operational amplifier is a specified topology of an op-amp are aimed to be met by
a cornerstone of an analog design environment. This study adjusting design parameters such as device sizes and bias
introduces a swarm intelligence based methodology for optimal currents with a swarm intelligence algorithm.
sizing of a CMOS operational amplifier. Actually, analog sizing is
a constructive procedure that aims at mapping the circuit Following introduction part, brief information about two-
specifications into the design parameter values. Specifying design stage op-amp structure is given in section II. Section III
constraints, conflicting design specifications are introduced to describes swarm intelligence based design methodology.
optimization algorithm as a constrained problem and CMOS Simulation results are presented in section IV. Finally, section
transistor area is aimed to be minimized. Simulation results V concludes the work with a discussion of results and
demonstrate that proposed method not only meets design suggestions for future work.
specifications and satisfies design constraints but also minimizes
total MOS area with respect to convex optimization method.
II. TWO-STAGE OPERATIONAL AMPLIFIER
Keywords- circuit sizing; operational amplifiers; particle swarm The specific two-stage CMOS op-amp considered in this
optimization; constrained optimization study is given in Figure 1. The circuit consists of an input
differential stage with active load followed by a common-
I. INTRODUCTION source stage also with active load. [9,10]. This architecture has
the advantages of high open-loop voltage gain, rail-to-rail
Analog integrated circuits (IC) are characterized by output swing, large common-mode input range, only one
complex tradeoffs between multiple nonlinear objectives while frequency compensation capacitance, and a small number of
satisfying multiple nonlinear and sometimes non convex transistors. However its main drawback is the nondominant
constraints. The variety of circuit schematics and the number of pole formed by the load capacitance and the output impedance
conflicting requirements and corresponding diversity of device of the second stage that reduces the achievable bandwidth [9].
sizes are also much larger than digital IC design. In addition,
analog circuits are more sensitive to nonidealities and all kinds
of higher order effects and parasitic disturbances [1].
The problem considered here is the optimal selection of
transistor dimensions for two-stage operational amplifier (op-
amp), which is only a part of a complete analog circuit
computer aided design (CAD) tool. Other parts which are
beyond the scope of this work are the topology selection [2,3]
and actual circuit layout [4,5]. The optimal component
selection and transistor sizing of the CAD process remains
between these two tasks [6]. Actually, analog sizing is a
constructive procedure that aims at mapping the circuit
specifications (objectives and constraints on performances) into
the design parameter values [7]. In other words, the
performance metrics of the circuit, such as gain, power
dissipation, occupied area, etc. have to be formulated in terms
Figure 1. Two-stage Op-Amp [10]
of the design parameters [8]. Following, these design
parameters such as device sizes and bias currents should be
Operational amplifiers are generally used in a negative-
adjusted under multiple design objectives and constraints. The
feedback configuration. This configuration provides high
many degrees of freedom in parameter space as well as the
accurate transfer function having feedback elements as the
need for repeated circuit performance evaluation made this a
function components. In order to make the op-amp stable, a
lengthy and tedious process. Here, particular specifications for
compensation capacitance (Cc) is connected between the output

This work was supported by the Yildiz Technical University Scientific

Projects Coordination Department with project number: 29-04-03-KAP01.

978-1-4577-0045-3/11/$26.00 ©2011 IEEE – 525 –

 R. A. Vural and T. Yildirim • Swarm Intelligence-based Sizing Methodology for CMOS Operational Amplifier

and the input of the second transconductance stage. This type g m21
of frequency compensation is very useful to cause the open- (W1 / L1 ) = (W2 / L2 ) = (3)
loop gain to roll off to unity before the output phase shifts by 2 K1' I1
180°. Having rail-to-rail output, op-amp structure depicted in where
Figure 1, achieves high output impedance which causes a
significant phase shift when driving capacitive loads. This extra g m1 = 2π f t Cc (4)
phase shift erodes the phase margin. Therefore, this circuit
structure is aimed to be used as a part of very large scale • Design W3/L3 (W4/L4) to satisfy the upper ICMR
integrated circuit (VLSI) for driving a few tens of picofarads.
VIC (max) =VDD-VSG3+VTN1 (5)
III. SWARM INTELLIGENCE BASED DESIGN PROCEDURE
• Design W5/L5 (W8/L8) to satisfy the lower ICMR
In this subsection, design steps and design equations
utilized for cost functions of particle swarm optimization
VIC (min) =VSS + VDS5 (sat) +VGS1 (6)
(PSO) based analog integrated circuit design are explained.
These design equations will be considered for obtaining MOS • Design W6/L6 assuming balanced conditions
dimensions in Figure 1.
gm6 (7)
(W6 / L6 ) = (W4 / L4 )
A. Particle Swarm Optimization gm4
PSO is an evolutionary computation method based on the where assuming zero z1 is placed beyond ten times ft
social behavior, movement and intelligence of swarms
searching for an optimal location in a multidimensional search g m 6 ≥ 10 g m1 (8)
area which has been developed by Kennedy and Eberhart [11].
The approach uses the concept of population and a measure of
performance, cost function (CF), similar to the fitness value g m 4 = 2 K 4' (W4 / L4 ) I d 4 (9)
used with evolutionary algorithms. Population consists of
potential solutions called particles. Each particle is initialized • Calculate Id6 which will most likely determine the majority
with a random value. In each iteration, final position of a of the power dissipation.
particle is evaluated by taking the current position of the
particle in the solution space and two best values (pbest, gbest). g m2 6 (10)
Personal best value, namely pbest, is the location of the best Id 6 =
2 K 6' (W6 / L6 )
fitness value obtained so far by the particle. Global best value,
namely gbest, is the location of the best fitness value achieved so
far considering all the particles in the swarm [11, 12]. CF is • Design W7/L7 to achieve the desired current ratios between
evaluated with the final values of the particles until the Id5 and Id6
stopping condition is satisfied. I6
(W7 / L7 ) = (W5 / L5 ) (11)
I5
B. Design Procedure for Two-stage Operational Amplifier
Here, design constraints of small-signal differential voltage • Check gain and power dissipation specifications
gain (Av), unity gain bandwidth (ft), maximum and minimum
input common mode voltages (VIC(max), VIC(min)), slew rate (SR) 2gm2 gm6
power dissipation (Pdiss) and design parameters of output Av = (12)
capacitance (CL) and MOS device sizes are provided within I d 5 (λ2 + λ3 )(λ6 + λ7 )
limits. Design procedure is given below [10]:
Pdiss = ( I bias + I d 5 + I d 6 )(VDD + | VSS |) (13)
• Choose minimum value for the compensation capacitor
Cc. Placing the loading pole p2 2.2 times higher than the ft, IV. SIMULATION RESULTS
permitted a 60° phase margin, assuming that the right half
In order to investigate the usage of PSO in analog
plane (RHP) zero z1 is placed at or beyond ten times ft .
integrated circuit sizing, optimal design of a basic analog
circuit structure study is carried out. The aim of this study is to
Cc > (2.2/10)CL (1) minimize total CMOS transistor area while satisfying design
criteria and design parameter constraints. Establishing design
• Determine Id5 (Iss) to satisfy the slew rate (SR) criteria and design parameters to PSO, the optimal circuit
structure was aimed to be designed by the algorithm. Design
I d 5 = C c SR (2) problem has been introduced to PSO algorithm by composing
an equation consists of input variables and design parameters
as a cost CF. In the beginning of the algorithm a certain range
• Design W1/L1 (W2/L2) using the transconductance of the was determined for both design criteria and design parameters
differential input stage by human designer. Input variables were also determined by
the human designer and dependent to preferential technology

– 526 –
 CINTI 2011 • 12th IEEE International Symposium on Computational Intelligence and Informatics • 21–22 November, 2011 • Budapest, Hungary

parameters. PSO should minimize the given CF and obtain limit of 100 iterations. CF is defined as the total area that MOS
design criteria and design parameter values for the given range transistors occupy and given in (15).
which gives minimum CF value.
T
The starting point of design consists of two types of
information. First type of information such as the technology
CF = ∑ (W
i =1
(i ) xL(i ) ) (15)

and the power supply is set by the designer. The other type of
information is the design criteria. The range of each criteria and
design parameter, power supply values and technology
information is set as an input to PSO algorithm (Table I) and
PSO algorithm should obtain the solution set that consists the
exact values of design parameters (Cc, CL, (W/L)i) where
(i=1,…,8) and design criteria (ft, VIC(max), VIC(min), SR, Pdiss, Av)
for given ranges. The design is implemented with the
relationships that describe design specifications to solve for DC
currents and W/L values of all MOS transistors. The
appropriate relationships were provided in the previous
subsection. Simulations are performed with TSMC 0.35 µm
technology parameters.
TABLE I. INPUTS AND OUTPUTS FOR OPTIMIZATION METHODOLOGY
Components
Information
in CF
VDD, VSS
¾ Set by human designer
Vtn, Vtp
INPUT
Target value of CF is aimed to be smaller than 300 µm2.
PSO-based design method resulted in a total MOS transistor
area of 265.8373 µm2 along with exact values of design
specification and design parameters (Wi, Ibias, Cc, CL). Design
process concluded after 100 epochs with a total execution time
of 8.6 s. Exact values of design parameters obtained from PSO
based design are given below:
• W1=W2=4.8926 µm,
• W3=W4=5.8713 µm
• W5=W8=2.0968 µm,
• W6=90.9557 µm, W7=16.2417 µm
• CL=10 pF, Cc=3 pF,
• Ibias=40.39 µA
Two-stage op-amp is redesigned using the resulting design
parameters in SPICE simulator in order to validate the exact
values of design specifications obtained with PSO. Design
specifications for two-stage operational amplifier, convex

¾ Fabrication technology
µnCox, µpCox optimization [9] results and SPICE simulations results of PSO
dependent
based design are tabulated in second, third and fourth column
λn, λp of Table II, respectively.
CL,,Cc
¾ PSO would find exact results TABLE II. COMPARISON OF CONVEX OPTIMIZATION AND PSO BASED
(W/L)1..8 for the given ranges
OUTPUT

DESIGN METHODS BY MEANS OF DESIGN SPECIFICATIONS

ft, SR, Pdiss, Av Convex
Two-stage OpAmp Design PSO
Optimization
VIC(max), VIC(min) Design Criteria Specs (SPICE)
[9]
Output Capacitance
(pF)
≥ 10 3 10
PSO is utilized for a two-stage operational amplifier having Slew Rate (V/µs) ≥ 10 88 11.15
design specifications of SR≥10V/µs (CL=10pF), ft≥3MHz
Power Dissipation
(CL=10pF), Av>1000 V/V, -1.5V≤ ICMR≤2V, Pdiss≤2.5mW (µW) ≤ 2500 5000 2370
with PSO inputs VDD=-VSS=2.5V, Vtn=0.4761V, Vtp=-0.6513V,
K’n= 181.2µA/V2, K’p= 65.8µA/V2, λn=0.04 V-1, λp=0.05 V-1. Phase Margin (o) >45 60 66.45
Constraints for design parameters are set as CL>=10 pF, Unity Gain
100≥(W/L)i≥2. In order to minimize the channel modulation Bandwidth (MHz)
≥3 86 5.3541
effect, MOSFET length values are chosen as Li=2 µm. Gain (dB) > 60 89.2 63.8
Initial population matrix size was 10x7 where row number Vicmin (V) ≥ -1.5 - -0.8
of 10 indicates the number of particles in the population and
column number of 7 is the dimension of particle vector. Vicmax (V) ≤2 - 1.75
Particle vector structure is expressed in (14) where SR is the CMRR (dB) > 60 92.5 83.74
slew rate (V/µm), CL is the output capacitance (pF), Av is the
+
gain (V/V), ft is the unity gain bandwidth (MHz), Pdiss is the PSRR (dB) >70 116 78.36
power dissipation (µW), Vicmin (V) and Vicmax (V) are the lower
PSRR- (dB) >70 98.4 93.56
and upper limits of ICMR, respectively.
Output Resistance
x = [SR, CL, Av, ft, Vicmin, Vicmax Pdiss] (14) >200 - 751
(kΩ)
2 -10 -10
Velocity update parameters c1, c2 and w were selected as Total Area (m ) <3x10 82x10 2.65x10-10
1.7, 1.7 and 0.99, respectively. The algorithm runs for upper

– 527 –
 R. A. Vural and T. Yildirim • Swarm Intelligence-based Sizing Methodology for CMOS Operational Amplifier

V. CONCLUSION
In this work, optimal selection of transistor dimensions has
been performed using a swarm intelligence method. Particular
specifications for a two-stage op-amp are aimed to be met by
adjusting design parameters such as device sizes and bias
currents with PSO algorithm. Design equations of each analog
circuit are utilized for cost function of PSO, since numerous
conflicting design specifications are of concern. Resulting
design parameters are utilized for redesign in SPICE simulator
in order to validate the exact values of design specifications
obtained with PSO. Simulation results proved that PSO based
design not only meets all design specifications but also
minimizes total MOS area with respect to the convex
optimization method.
Consequently, PSO proved its efficiency on CMOS op-amp
design with high accuracy and short computation time. Analog
IC design problem can be considered as a constrained problem
and as a global optimization tool, PSO is very successful with
handling those conflicting objectives as long as design
specification equations are well defined and introduced to PSO.
Figure 2. Frequency response of PSO based two-stage op-amp design
As a further work, the proposed method will be utilized for
optimal sizing of different analog structures.

REFERENCES
[1] G. Gielen and R.A. Rutenbar, R.A., “Computer-Aided Design of Analog
and Mixed Signal Integrated Circuits”, Proceedings of IEEE, vol. 88, pp.
1825-1852, 2000.
[2] P.C. Maulik, L.R. Carley and R.A. Rutenbar, "Integer Programming
Based Topology Selection of Cell-Level Analog Circuits", IEEE Trans.
on CAD, vol. 14, pp. 401-412, 1995.
[3] I. O'Connor and A. Kaiser, "Automated synthesis of current-memory
cells." IEEE Trans. CAD of Integrated Circuits and Systems, vol. 19, pp.
413-424, 2000.
[4] E. Yilmaz and G. Dündar, “Analog Layout Generator for CMOS
Circuits”, IEEE Trans. CAD of Integrated Circuits and Systems, vol. 28,
pp. 32-45, 2009.
[5] G. Van der Plas, G. Debyser, F. Leyn, K. Lampaert, J. Vandenbussche,
G. Gielen,W. Sansen,P.Veselinovic, D. Leenaerts, ”AMGIE-A synthesis
environment for CMOS analog integrated circuits”, IEEE Trans. CAD of
Figure 3. Slew rate of PSO based two-stage op-amp design Integrated Circuits and Systems, vol. 20, pp. 1037-1058, 2001.
[6] F. Medeiro, R. Rodríguez-Macías, F.V. Fernández, R. Domínguez-
Astro, J.L. Huertas and A. Rodríguez-Vázquez, “A Global Design of
Analog Cells Using Statistical Optimization Techniques”, Analog
Integrated Circuits and Signal Processing, vol. 6, pp. 179-195, 1994.
[7] M. Fakhfakh, M. Loulou and N. Masmoudi, “A Novel Heuristic for
Multi-objective Optimization of Analog Circuit Performances”, Analog
Integrated Circuits Signal Processing, vol. 61, pp. 47-64, 2009.
[8] G. Tulunay and S. Balkir, “A Compact Optimization Methodology for
Single Ended LNA”, Proceedings of the IEEE International Symposium
on Circuits and Systems, ISCAS 2004, pp. 273-276, 2004.
[9] M.D. Hershenson, S.P. Boyd and T.H. Lee, “Optimal Design of a
CMOS Op-Amp via Geometric Programming”, IEEE Trans. CAD of
Integrated Circuits and Systems, vol. 20, pp. 1-21, 2001.
[10] P. Allen and D. Holberg, CMOS Analog Circuit Design, 2nd ed., Oxford
University Press, New York, 2002.
[11] J. Kennedy and R.C. Eberhart, “Particle Swarm Optimization”, Proc.
IEEE International Conf. on Neural Networks, pp. 1942-1948, 1995.
[12] M. Clerc, “The Particle Swarm - Explosion, Stability and Convergence
Figure 4. PSRR- of PSO based based two-stage op-amp design in a Multidimensional Complex Space”, IEEE Trans. Evolutionary
Computation, pp. 58-73, 2002.

– 528 –