IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO.

1, JANUARY 2016 369

Tradeoffs Aware Design Procedure for an Adaptively

Biased Capacitorless Low Dropout Regulator
Using Nested Miller Compensation
Ashis Maity, Student Member, IEEE, and Amit Patra, Member, IEEE

Abstract—An adaptively biased, low dropout regulator (AB-

LDR) that uses the nested Miller type frequency compensation
has been explored in the literature for system-on-chip applica-
tions. However, those are mostly focused to solve only specific issues
without accounting for all the design tradeoffs. Due to this, addi-
tional components/circuits are needed to mitigate the issues like
Q-peaking and poor dynamic response in capacitorless condition.
In this paper, the various design tradeoffs particularly relevant to
the nested Miller compensated regulator architecture, are clearly
brought out. Then a detailed design procedure for the same ar-
chitecture is proposed to achieve a low quiescent current, wide
dynamic range, desired dynamic response and a high current effi-
ciency over a given load range. An AB-LDR has been implemented
in standard 0.18-μm CMOS technology to validate the effective-
ness of the proposed approach. Experimental results show a very Fig. 1. Typical block diagram of an AB-LDR.
good agreement with the theoretical analysis.
Index Terms—Adaptive bias loop, capacitorless regulator, low
dropout regulator, main feedback loop, nested Miller compensa-
tion, Q-factor reduction.

I. INTRODUCTION
N recent years, the development of a capacitor-free regulator
I architecture [1]–[3] has gained considerable importance for
system-on-chip (SoC) applications because of its higher level of
integration possibility which saves a lot of board space and pin
count [4], [5]. The stability over a wide range of load current
[6]–[9], the fast transient response [10]–[19] and small quiescent
current [20]–[22] are the essential features of the regulator re-
quired for SoC applications. The widely used adaptively biased,
low dropout regulator (AB-LDR) architecture for such appli-
cations is shown in Fig. 1 [6], [7]. In order to get better load
regulation, it uses three gain amplifier stages compensated by a
pole-splitting Miller capacitor Cm 1 . The PMOS power transis-
tor, M98 has the maximum current driving capability required
by the load Io,m ax . Due to its large size, it has a higher parasitic
gate to drain capacitance which is modeled as Cm 2 . This forms
a nested Miller type frequency compensation scheme [6], [7],
[23], [24]. The resistor divider consisting of R1 and R2 , level
shifts the voltage Vref to the desired output voltage Vo . The bias
Manuscript received November 26, 2014; revised January 5, 2015; accepted
January 24, 2015. Date of publication February 3, 2015; date of current ver-
sion September 21, 2015. Recommended for publication by Associate Editor
M. A. E. Andersen.
A. Maity is with the Advanced Technology Development Center, Indian In-
stitute of Technology, Kharagpur 721302, India (e-mail: ashis.iit@gmail.com).
A. Patra is with the Department of Electrical Engineering, Indian Institute of
Technology, Kharagpur 721302, India (e-mail: amit.patra@ieee.org).
Digital Object Identifier 10.1109/TPEL.2015.2398868
Fig. 2. Various tradeoffs hexagon in the AB-LDR topology.
current of the first and second stages has two components: the
fixed bias If and the adaptive bias Iv which is generated by
the M94 − M95 − M96 path. The current Iv increases with Io
as Iv = δIo , where δ is the adaptive bias (AB) ratio and it is
equal to (A/M ). The adaptive biasing [7], [25], [26] scheme
maintains a very low quiescent current at low load conditions
and expands the unity gain frequency (ωU G F ) of the regulator
at high load condition to achieve a faster transient response.
There are several issues that exist in the nested Miller com-
pensated AB-LDR. So, different tradeoffs need to be considered
while optimizing the key performance parameters of the regula-
tor as shown in Fig. 2. Most of the related literature only optimize
a few of them. Therefore, the said topology underperforms as
a regulator. For example, [6] mainly focuses on the Q-peaking
issue which restricts the low load current value Io,m in . The re-
lation between Q-peaking and If is still unexplored and hence
an additional Q-reduction capacitor is required to improve the
same. Moreover, as the Q-reduction capacitor only offers some

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370 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 1, JANUARY 2016

improvements in a narrow region of the load range, the stabil-

ity in [6] is ensured only up-to Io,m in = 100 μA. The study
in [7] uses adaptive biasing on the topology in [6] to improve
the dynamic response. To maintain a high value of current ef-
ficiency at the full load condition, it uses a low value of δ
equal to 0.001. However, the basis of choosing the value of δ to
achieve a fast dynamic response is not critically analyzed here.
So, [27] proposes a dedicated sub-threshold undershoot reduc-
tion circuit along with the spike detection capacitor to improve
the dynamic response. Although, the spike detection capacitor
helps to achieve a value of Io,m in equal to 10 μA, the stability of
the regulation loop at Io,m in is quite susceptible to the value of
the same. In all these designs in [6], [7], [27], the quiescent cur-
rents (IQ ) at the low load condition are still quite high and their
values are 100 μA (Io,m in =100 μA), 30 μA (Io,m in =50 μA)
and 28 μA (Io,m in =10 μA), respectively. This makes them less
attractive for the ultra low-powered SoC applications where the
budget of IQ is even lower. So, further research is still required Fig. 3. Schematic of the conventional AB-LDR topology.
to understand the different tradeoffs of the nested Miller com-
pensated AB-LDR for achieving better performance.
In this paper, the conventional AB-LDR topology is revisited stage. The first and second stages combined together constitute
which uses nested Miller type frequency compensation. This an error amplifier. The substrate of the input transistors M81 and
type of frequency compensation scheme is well explored for the M82 is connected to the ground potential.
amplifier design [28], [29] where the dc operating point is fixed.
However, the same design procedure can not be applied di- A. Understanding the Tradeoffs Between IQ , Q-Peaking
rectly to the AB-LDR design where the dc operating point itself and the Load Range
changes with Io . The dynamic range of Io is nearly spread over
The tail current of the error amplifier is given by It = If + Iv .
4–5 decades. Moreover, as Cm 2 is generated from the parasitic
Since Iv = AIo /M , for each value of the load current, the dc-
capacitor of M98 , it no longer remains as a design variable. To
operating point of the regulator changes and as a result, the small
cover such a large dynamic range of Io , the design tradeoffs as
signal circuit parameters also get altered. The trans-conductance
shown in Fig. 2 are quite different and these issues are explored
(gm ) of the first and second stages is a function of It and it is
in this paper. A systematic design procedure backed by theo-
denoted as gm ,81 (It ) and gm ,87 (It ), respectively. On the other
retical analysis has also been developed here. This helps us to
hand, the gm of the last stage solely depends on Io and hence is
reduce the value of IQ substantially while maintaining a fast and
denoted as gm ,98 (Io ). The parasitic capacitance offered by the
stable dynamic response over a wide load range without using
load is Co,o . The Miller capacitor Cm 1 creates a dominant pole
the additional block (e.g., sub-threshold undershoot reduction
at the node V1 .
circuit) and components (e.g., Q-reduction and spike detection
For regulator design, gm ,98 (Io )  gm ,81 (It ) and gm ,98 (Io )
capacitors). The organization of the paper is as follows: Sec-
 gm ,87 (It ). Under this condition, the two zeros (LHP and
tion II explains different tradeoffs in the conventional AB-LDR
RHP) are placed a few decades higher than the ωU G F and hence
topology. The proposed design procedure is described in Sec-
have very minimal impact on the system stability [28]. Also, the
tion III. The design examples to substantiate different tradeoffs
location of the ωU G F and the two nondominant poles can be
are given in Section IV. Section V validates the design proce-
approximated as follows [28], [29]:
dure with experimental results and the conclusions are given in
Section VI. ωU G F = −gm ,81 (It )/Cm 1 (1)
ωp2 = −gm ,87 (It )/Cm 2 (2)
II. DIFFERENT TRADEOFFS IN CONVENTIONAL
AB-LDR TOPOLOGY ωp3 = −gm ,98 (Io )/Co,o (3)

The schematic of the conventional AB-LDR topology is
shown in Fig. 3. Here, we consider Vref = Vo . So, a unity mode
configuration of the regulator with a feedback factor of 1 is
formed by eliminating R1 and R2 as used in Fig. 1. This does
not create much difference while developing and designing the
regulator topology. The first stage consists of a differential input
pair with active current mirror load, the second stage is a differ-
ential to single ended amplifier and the third one is the power
To understand the Q-peaking problem from the two nondom-
inant poles better, the pole movements through-out the load
current range need to be analyzed carefully. While moving from
the high to moderate load condition, the dc operating point of
M98 moves from the above-threshold to the sub-threshold
√ re-
gion. In√the above-threshold region, gm ,98 ∝ Io and hence
ωp3 ∝ Io . Whereas in the sub-threshold region, gm ,98 ∝ Io
and hence ωp3 ∝ Io . If the same level of channel inversion as
MAITY AND PATRA: TRADEOFFS AWARE DESIGN PROCEDURE FOR AN ADAPTIVELY BIASED CAPACITORLESS LOW DROPOUT 371

Fig. 4. Root-locus of the ω U G F , ω p 2 and ω p 3 under different load conditions.

M98 is maintained in M87 , then their current densities are equal.

Fig. 5. Different regions of load transient response.
As a result, M87 caries exactly a down-mirrored current of Io ,
determined by their sizing ratio. Hence, the transition points of
M98 and M87 from the above-threshold to the sub-threshold re-
split the load transient response of the capacitorless AB-LDR
gion should coincide with each other. Also, for high to moderate
into different time intervals as shown in Fig. 5. When the load
load condition, It is mostly dominated by the load dependent
current switches from Io,m in to Io,m ax , the regulator first enters
bias current Iv and hence, Iv  If . These two conditions help
the slewing mode. Before the loop starts responding, i.e., over
to track the poles ωp2 and ωp3 in a similar way. As the separation
the period [t0 –t1 ], the slew rate at the gate of the power tran-
among them is well maintained, there is no chance of generating
sistor depends mainly on It (= If + δIo ) for the lightest load.
a complex pole pair and hence, no Q-peaking effect. The way to
The amount of undershoot and the response time are mostly
maintain the same level of channel inversion is discussed later.
dependent on the values of If and δ. After the loop starts re-
Now, at a very low load, It is mostly dominated by the fixed
sponding, the adaptive biasing circuit enhances the slew rate as
current component If . So, ωp2 becomes static over the load vari-
Iv increases and Vo starts recovering during [t1 –t2 ]. The AB
ation, but ωp3 ∝ Io due to the sub-threshold region of operation
ratio δ in the midrange of the load current controls this recovery
as per (2) and (3), respectively. So, with the decrease of the load
time. Once the error reduces, the regulator enters the small sig-
current, ωp3 comes more and more closer to ωp2 at very low
nal region during [t2 –t3 ]. Here, the higher value of Iv expands
load. When ωp3 < 4ωp2 , we get a complex pole pair in the sys-
√ the ωU G F to such a high value that Vo increases linearly with the
tem with an angular corner frequency of ωo = ωp2 ωp3 [29] .
load current which is similar to a ramp response. On the other
The Q-peaking effect from the complex pole pair causes a sharp
hand, for Io,m ax to Io,m in load transient edge, this sequence is
phase degradation near the ωU G F [7]. The pole movements un-
reversed. Initially, the higher ωU G F at Io,m ax helps to track the
der different load conditions are shown in Fig. 4. At Io,m ax ,
Vo as the load changes during [t4 –t5 ]. Once the ωU G F reduces
ωp3 > 4ωp2 and hence there is no Q-peaking effect, whereas
in the midrange of the load current, the loop response becomes
at Io,m in , ωp3 < 4ωp2 and the complex pole pair is located in
slower and due to large overshoot, the regulator goes into the
the system at ωo . At the critical load Io,cric , ωp3 = 4ωp2 and up
slewing mode during [t5 –t6 ]. Here, the AB ratio δ controls the
to this point, all the poles are real and the stability is guaran-
amount of overshoot. Once the maximum peak of the overshoot
teed with the 2.2ωU G F ≤ ωp2 . For Io < Io , cric, the stability
occurs, the expression (If + δIo ) determines the slewing of the
of the overall system gets affected by the high Q-factor and it
gate of the power PMOS transistor initially. The error slowly
essentially puts a constraint on the value of Io,m in for a stable
reduces and the regulator enters the small signal region. The
operation of the regulator. The value of If mostly determines
settling behavior mostly depends on the ωU G F at the minimum
the magnitude of IQ at no load condition. Therefore, there exists
load condition and as expected it is very sluggish due to the
a close relation between IQ and Io,m in , so that we can choose
limited loop bandwidth at low load. So, the settling times for
the latter for a stable operation.
both the transients are different.
There are many advantages of having a higher value of δ in
B. Understanding the Tradeoffs Between Dynamic Response, the low-to-mid range of Io . First, a higher value of δ reduces
AB Ratio and Maximum Current Efficiency the duration of [t1 –t2 ] and improves the settling time. Second,
In the AB-LDR, the transistors may remain either in the the amount of undershoot reduces when the load switches from
above-threshold or the sub-threshold region depending on the some intermediate value to high as Iv becomes larger. Third, the
value of Io . In the sub-threshold region, the regulator responds amount of overshoot reduces during [t5 –t6 ]. Fourth, the interval
more slowly as the transistors carry less current compared to [t6 –t7 ] reduces for intermediate load current. However, the main
the above-threshold region. So, the adaptive biasing should be disadvantage of choosing a higher value of δ is that it reduces
very effective for improving the speed of the regulator in the the current efficiency at high load condition. For the region [t2 –
sub-threshold region. To illustrate this point further, one can t3 ] and [t4 –t5 ], where the loop response is similar to the ramp
372
response, the tail current of the error amplifier is more than
the required value. Therefore, there is a scope of improving the
current efficiency at the high load condition. In a conventional
design approach, a smaller value of δ is mainly chosen not to
degrade the current efficiency at high load condition. However,
this lowers down the current in the low-to-mid range of the load
current. Therefore, the dynamic response is not optimized in the
conventional approach.
III. PROPOSED DESIGN PROCEDURE
In this section, the biasing considerations of the regulator
are thoroughly analyzed. To avoid the Q-peaking effect, i.e.,
Q ≤ 0.5, we have to maintain the relation ωp3 ≥ 4ωp2 even at
the low load condition. Assuming all the poles are real, the phase
margin of the overall system is given by [7]
ω  ω 
P M |Q ≤0.5 = 90o − tan−1 − tan−1
U GF U GF
(4)
ωp2 ωp3
Also, the condition for achieving a phase margin of 60o is
given by [29]
ωp2 ωp3
ωU G F ≤ ≤ The value of K should be chosen in such a way that Cm 1 does
2.2 8.8
gm ,81 (It ) gm ,87 (It ) gm ,98 (Io )
≤ ≤ (5)
Cm 1 2.2Cm 2 8.8Co,o
A. Sizing of the Transistors
The power transistor M98 should be sized at Io,m ax in the
dropout condition where the overdrive voltage Vov = (Vin −
Vo ). Here, M98 operates at the edge of the linear and the satu-
ration regions. So, the aspect ratio of M98 is given by
W 
2Io,m ax
= (6)
L 98 μp Cox Vov 2
where μp is the mobility of the holes and Cox is the gate oxide
capacitance per unit area. For achieving less Vov , we need to
increase the value of (W/L)98 and hence more silicon area is
required.
The sizing ratio of the transistor pair M94 , M98 is 1 : M
which is kept very high (M > 1000) to minimize the current
through this path. The perfect matching of M94 and M98 is
extremely difficult to achieve, although a good layout technique
helps to minimize the mismatch between them.
Once the size of M98 is chosen optimally, the sizes of the
remaining transistors are chosen to set these devices at the
same current density which ensures the same level of chan-
nel inversion. This leads to (W/L)87 = AK(W/L)98 /2M
and (W/L)83,84 = A(W/L)98 /2M . To minimize the current
through M88 , (W/L)87 = 4(W/L)88 is chosen. An even ratio
ensures good matching between them. The dc current balancing
is confirmed by choosing (W/L)90 = 4(W/L)89 . However, the
input transistors, M81,82 are realized by the NMOS devices. The
aspect ratio of M81 (and M82 ) is given by
W  Aμp (W/L)98 (Vsg ,98 − |Vth,98 |)2
= (7)
L 81,82 2M μn (Vg s,81 − Vth,81 )2
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 1, JANUARY 2016
where Vth is the threshold voltage of the corresponding transis-
tor. The sizes of remaining transistors M89 − M90 , M95 − M96
are not very critical, rather their ratios are more important.
Hence, the size of those transistors should be chosen based
on the maximum current flowing through it at Io,m ax .
B. Fixing the Values of Cm 1 and K
Once the sizing of all the transistors is done, the value of
Cm 1 is to be fixed corresponding to Io,m in . In the sub-threshold
region, gm ,81 = I81 /nn VT and gm ,87 = KI81 /np VT . Here, nn ,
np are the sub-threshold region swing parameters of NMOS
and PMOS transistors, respectively, whereas VT is the thermal
voltage. From the first inequality of (5), one can get as follows:
2.2Cm 2 np
Cm 1 = (8)
Knn
While increasing the value of K, one has to decrease the value
of Cm 1 by the same factor to keep ωU G F at the same location as
per (8). This gives a practical limitation for increasing the value
of K. Thus, Cm 1 should not be so small that it is comparable to
the parasitic value which degrades the robustness of the design.
not take much area and also it is less susceptible to the parasitic
effects.
C. Fixing the Values of If and A
As discussed before, the poles track each other at high to
moderate load condition. This continues until Io reaches a level
Io,cric where Iv and If are comparable to each other. Of course,
this happens at a very low load especially, if the value of If is
quite small. For Io ≥ Io,cric , the nondominant poles ωp2 and ωp3
are real and hence, there is no Q-peaking effect in the frequency
response of the regulator. The value of Io,cric is calculated from
the second inequality of (5) which gives
 C A
m2
If ≤ − Io (9)
2KCo,o M
(9) gives the relation between the value If and the achievable
limit of Io to avoid Q-peaking effect from the nondominant
complex poles. In other words, to achieve a minimum value of
Io,cric , If ,m ax should not exceed the value given by
 C A
m2
If ,m ax = − Io,cric (10)
2KCo,o M
For Io < Io,cric , If dominates over the value of Iv and hence
It ≈ If . In this region, ωU G F , ωp2 are almost independent of Io ,
whereas ωp3 ∝ Io . Hence, ωp3 comes closer to ωp2 and makes
ωp3 < 4ωp2 . This creates a complex pole pair in the system. The
angular corner frequency and the Q-factor are approximated as
follows:

If Io
ω0 ≈ (11)
np nn VT 2 Cm 2 Co,o

If nn Co,o
Q≈ (12)
Io np Cm 2
MAITY AND PATRA: TRADEOFFS AWARE DESIGN PROCEDURE FOR AN ADAPTIVELY BIASED CAPACITORLESS LOW DROPOUT
Fig. 6. Schematic of the proposed AB-LDR topology.
√ √
It is interesting to note that, ωo ∝ Io and Q ∝ 1/ Io at Io <
Io,cric region. Therefore, the Q-factor gradually increases with
the fall of Io .
The values of K and A have a direct correlation with If ,m ax
and Io,cric as given in (10). For obtaining a positive value of
If ,m ax , the condition, Cm 2 /(2KCo ) > A/M has to be satisfied.
Now, once the value of K is increased and that of A is decreased
by the same factor, the value of If ,m ax is also decreased by the
same factor. In other words, to achieve a desired value of Io,cric ,
one has to reduce the value of the fixed current component of
the error amplifier. However, putting an arbitrarily high value
of If  If ,m ax pushes ωU G F to a higher frequency at low load
condition. Since, it reduces the separation with ωp2 , a higher
value of Cm 1 is required to compensate the regulator at the low
load. What is more, the regulation loop becomes overcompen-
sated with a high value of Cm 1 which restricts the expansion
of ωU G F at the high load condition. This leads to a poor load
transient response at the high load range. Also, a higher value
of If ,m ax significantly reduces the current efficiency at the low
load condition. While fixing the value of If , A should be chosen
optimally as it also affects the dynamic response.
D. Maximizing the Current Efficiency
The total quiescent current consumption of the regulator with
the different sizing ratios chosen in Fig. 3 is (I89 + If + Iv +
I90 + I95 ) = [ If (1 + 0.625K) + Io {1/M + (1 + 0.625K)
A/M }]. So, the current efficiency, η of the regulator is given in
(13) below.
I  AI  
η=  o 1 A
 (13)
If (1 + 0.625K) + Io 1 + M + M (1 + 0.625K)
Here, η is a monotonically increasing function with Io . At low
load condition, the value of η decreases as the If factor term
dominates in the denominator of (13). So, reducing the value
of If increases η. At high load condition, the value of If is
373
insignificant compared to the Io factor in the denominator. So,
η will mostly depend on the factor “A(1 + 0.625K)/M ” and
is maximized by reducing this expression. To satisfy the second
inequality in (5), one should have AK/M ≤ Cm 2 /2Co,o . Here,
neither Cm 2 nor Co,o is a design variable, as they are deter-
mined from the specification of Io,m ax and the load parasitic,
respectively. For Cm 2 = 3.6 pF and Co,o = 100 pF, the max-
imum value of the factor AK/M = 0.018. For Io,m ax = 100
mA, the maximum contribution from 0.625AK/M factor it-
self is around 1.125 mA. Considering the contribution of other
factors in (13), the value of η will be much less than 99%. There-
fore, to maximize the value of η, one has to choose a much lower
value of the factor AK/M . The values of A, K, M are already
fixed for achieving better dynamic response as described previ-
ously. For the duration, [t2 − t3 ] and [t4 − t5 ], the excess bias
current should be reduced to maximize η at high load condition.
This is done by modifying the adaptive bias loop as shown in
Fig. 6. The aspect ratio of M97 is the same as that of M94 and
they carry the same current. A minimum current selector circuit
[30] consisting of M77 − M80 , clamps the magnitude of Iv to
ILIM IT at higher load condition and improves the current effi-
ciency. The value of ILIM IT has to be decided based on the ex-
pected rise/fall time of the load current step. The sizing ratios of
M77 − M80 are chosen as (W/L)80 = (W/L)79 = (W/L)95
and (W/L)78 = N (W/L)77 . The dc value of ILIM IT adds a
component on the overall quiescent current consumption of the
regulator. To minimize it, a high value of N is preferred. There-
fore, in the proposed topology, the magnitude of Iv is determined
as follows:

Iv = Min.
o
, AN I LIM IT (14)
M
So, for Io ≥ (AN I LIM IT ), the regulator acts as a fixed bias
scheme.
To determine the magnitude of ILIM IT , one has to review the
current source and current sink capability of the error amplifier
374 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 1, JANUARY 2016

TABLE I
ASPECT RATIOS (W/L) IN μm OF ALL THE TRANSISTORS USED IN DIFFERENT
DESIGN VARIANTS

Tran- I f chosen optimally, I f is high,

sistors C m 1 = 9 pF C m 1 = 60 pF
δ = 0.006 δ = 0.00075 δ = 0.006

Without- With- Reduced- Over-

IL I M I T IL I M I T AB Compensated
M98 10000/0.18
M81,82 160/0.36
M83,84 60/0.36
M89 6/0.36
M90 24/0.36
M94 5/0.36
M95 4/0.5
M87 60/0.36 9.1/0.36
M88 15/0.36 2.27/0.36
M96 96/0.5 12/0.5 96/0.5
M97 - 5/0.36 -
Fig. 7. Small signal loop response of the LDR at Io = 10 μA with different
M77 - 4/0.5 -
value of If for “Without-IL IM IT ” case.
M78 - 48/0.5 -
M79,80 - 4/0.5 -

To substantiate the effectiveness of the proposed design pro-

under large signal operation. The current sourcing limit at the
gate of M98 is set as Isource = KIt . However, the value of
sinking current is set by the node voltage V1 and the values of
gm ,88 , K. Obviously, this path has much higher gain compared
to the source path and it is not directly set by the value of It .
So, the value of ILIM IT on It has a major impact only on the
high-to-low load transient edge. Due to poor current sourcing
capability, ILIM IT may introduce more overshoot at the node Vo
for a very fast falling edge of load. But, there is an opportunity
to restrict the bias current with ILIM IT for a relatively slower fall
time. So, the value of ILIM IT should be fixed based on expected
fall time to remove excess bias current without introducing extra
overshoot.
As a final remark, the size of the transistors should be fixed at
Io,m ax based on maintaining the same current density. As the Q-
peaking is more prominent at low load condition and it directly
affects the value of Io,cric , an optimal and realizable value of If
should be chosen at that condition. The value of the AB ratio
should be chosen optimally for the low and mid range of the load
current for better dynamic response. The value of ILIM IT cuts
down the excess bias current at high load condition to maximize
the current efficiency. The adaptive bias loop which changes
the bias current in accordance with Io acts as an attenuator
and the stability of the same is guaranteed by design as discussed
in the study [7] in detail.
IV. DESIGN EXAMPLES
The proposed design procedure is applied to the AB-LDR
topology which is designed in a 0.18 μm CMOS technology
with Vth,n = 520 mV and |Vth,p | = 510 mV. The targeted input
voltage range is 1.4 to 1.8 V and the output is fixed at 1.2 V. The
dynamic range of the load current is 10 μA–100 mA with an
expected rise/fall time of 1 μs. The parasitic capacitance from
the load is lumped as nearly 100 pF.
cedure in simulation, four different variants are designed. The
proposed design procedure considers two cases, namely without
and with limiting the excess bias current at high load condition,
which are termed as “Without-ILIM IT ” and “With-ILIM IT ,” re-
spectively. Similar to the conventional design approach [7], [27],
the use of a small value of δ is termed as “Reduced-AB” case
where the bias current at high load condition is targeted as the
same as “With-ILIM IT ” case for an easy comparison. In these
three cases, If is chosen optimally as per (10). Once If is fixed
arbitrarily more than its optimal value, a higher Miller capacitor
makes it similar to the “Over-compensated” case. The aspect
ratios of all the transistors used in these four cases are summa-
rized in Table I.
Fig. 7 compares the ac loop responses at Io = 10 μA for
If = 100 nA and If = 1 μA conditions for “Without-ILIM IT ”
case. With If = 100 nA, there is no Q-peaking in the system
and it has a phase margin of 70o . However, for If = 1 μA, the
Q-peaking effect and increased value of ωU G F jointly decrease
the phase margin to −26o .
Fig. 8(a) and (b) shows the variation of ωU G F and phase
margin, respectively, for different values of If . We observe
that ωU G F gradually increases with Io . The ωU G F becomes
constant for higher values of If where the phase margin is ap-
proximately between 45–60o . In this range, If dominates over
Iv which makes the gm ,81 and gm ,87 constant. So, ωU G F and
ωp2 become static. As ωp3 comes closer to ωp2 , it increases
Q-peaking and hence decreases the phase margin. However,
ωU G F falls again at lower values of Io where the corner fre-
quency, ωo mainly decides the location of ωU G F . Also, the
effect of RHP zero can not be ignored in this region. Hence,
the phase margin sharply decreases here. From Fig. 8(b), the
value of If is also determined for a phase margin of 60o . For
example, to cover Io,m in = 10 μA, both the cases If = 10 nA
and 100 nA provide stable behavior. However, as If = 100
nA has a higher ωU G F (67.8 kHz compared to 27 kHz), it
should be chosen to achieve a faster transient response. The
MAITY AND PATRA: TRADEOFFS AWARE DESIGN PROCEDURE FOR AN ADAPTIVELY BIASED CAPACITORLESS LOW DROPOUT 375

Fig. 8. (a) ω U G F versus Io . (b) Phase margin versus Io for “Without-

IL IM IT ” case. Fig. 9. Comparison of ac response for the cases “Without-IL IM IT ,” “With-
IL IM IT ,” “Reduced-AB” and “Over-compensated.” (a) ω U G F versus Io .
(b) Phase margin versus Io .

TABLE II
COMPARISON BETWEEN THEORETICAL AND SIMULATED VALUES
OF Io , c ric FOR DIFFERENT VALUES OF If , m a x Fig. 9 shows the comparison of ωU G F and the phase margin
for the four cases listed in Table I. To reduce the excess bias
If , m a x Theoretical value of Simulated value of current at high load condition, ILIM IT = 222 nA is chosen for
Io , c r i c Io , c r i c “With-ILIM IT ” case. With ILIM IT = 222 nA, the adaptive bias
becomes ineffective above Io =10.6 mA. So, ωU G F and ωp2
10 nA 830 nA 900 nA
100 nA 8.3 μA 8 μA become static above Io =10.6 mA, although ωp3 dynamically
1 μA 83 μA 80 μA varies with Io . As a result, the phase margin is increased by 9o
10 μA 830 μA 700 μA (from 69o to 78o ) compared with the case “Without-ILIM IT ” at
Io = 100 mA.
Now, comparing the case “Reduced-AB” with the case “With-
exact value of the load current is calculated numerically here ILIM IT ”, although the value of ωU G F is almost the same at
based on (10). In the “Without-ILIM IT ” case, the values of two extreme points of the load range, it falls in the midrange
Co,o = 100 pF, Cm 2 = 3.6 pF, K = 1, M = 4000 and A = 24. of the load current as shown in Fig. 9(a). On the other hand,
Therefore, Io,cric = 83If ,m ax . Table II compares the theoreti- for the case “Over-compensated,” If is biased at 1 μA rather
cal and simulated values of Io,cric for different numerical val- than the optimal value of 100 nA. Then the value of the factor
ues of If ,m ax for stable operation. There is a reasonably good (If + AIo /2M ) becomes 1060 nA. So, one has to use 6.6 times
agreement between them. From Table II, it is quite clear that, higher value of Cm 1 , i.e., 60 pF to keep ωU G F at the same
the value of If ,m ax fixes the allowable limit of Io,cric . Be- location at the low load condition. Similarly, the value of K
low Io = Io,cric , the phase and gain margins fall drastically is decreased by the same factor to keep the location of ωp2
and the regulator enters into an unstable region. To cover unaltered. With Cm 1 = 60pF, ωU G F is decreased by 6.6 times
Io,m in = 10 μA, a value of If = 100 nA is chosen as the optimal at Io,m ax as shown in Fig. 9(a). So, the LDR is overcompensated
value. at high load condition and it has more phase margin as shown in
376
Fig. 10. Comparison of load transient response for the four cases for a load
step of 1–100 mA with rise/fall time 100 ns.
Fig. 11. Microphotograph of the proposed regulator.
Fig. 9(b). What is more, having a smaller value of K, the slew
rate is expected to reduce at the gate of M98 . All four designs
have almost the same ωU G F of 70 kHz and the same phase
margin of 66o at Io = 10 μA. Also, at Io = 100 mA, they have
approximately the same ωU G F of 12 MHz and the phase margin
is quite close to 80o for all these cases.
Fig. 10 shows the comparison of the load transient response
for these four cases. For 1–100 mA load step, the cases “With-
ILIM IT ” and “Without-ILIM IT ” have almost the same settling
behavior even with a faster rise/fall time of 100 ns. However,
the other two cases “Reduced-AB” (smaller δ) and “Over-
compensated” (higher If ) provide large settling time for both
the load transients. Also, the amount of undershoot and over-
shoot are also more for the latter two cases. Due to the optimal
choices of δ and If in the cases “With/Without-ILIM IT ,” the
settling behavior is much better than the other two cases.
V. EXPERIMENTAL RESULTS
To validate the proposed design procedure, the cases “With-
ILIM IT ” and “Without-ILIM IT ” have been fabricated in silicon
in 0.18 μm CMOS technology. The microphotograph of the
proposed regulator is shown in Fig. 11. It occupies an active
area of 0.07 mm2 excluding the PAD area.
Fig. 12 compares the load transient response for the extreme
load step of 100 mA–10 μA with a fall time of 50 ns for different
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 1, JANUARY 2016
Fig. 12. Measured load transient response for a load step from 100 mA–10
μA with a fall time of 50 ns for the case “Without-IL IM IT ” for different values
of If .
Fig. 13. Measured load transient response for a load steps of 100 mA–10 μA
with a fall time of (a) 50 ns for “With-IL IM IT ” (Ch-1), “Without-IL IM IT ”
(Ch-2), (b) 100 ns for “With-IL IM IT ” (Ch-4), “Without-IL IM IT ” (Ch-5).
values of If . The optimal value of If = 100 nA shows more
stable settling behavior compared to the case If = 200 nA and
If = 400 nA.
On the other hand, Fig. 13(a) and (b) compares the tran-
sient response between the cases “With-ILIM IT ” and “Without-
ILIM IT ” for the extreme load step of 100 mA–10 μA with differ-
ent fall times of 50 and 100 ns, respectively. For a fall time of 50
ns, the overshoots for the cases “With-ILIM IT ” and “Without-
ILIM IT ” are +340 and +170 mV, respectively, whereas for a
fall time of 100 ns, their values are almost equal to +130 mV.
These results confirm that the consumption of high bias current
at maximum load current is not very useful to improve the dy-
namic response for a slower load step. Hence, a judicious value
of ILIM IT should be chosen to reduce the excess bias current.
For the other edge of load transient, i.e., 10 μA–100 mA, the
effect of ILIM IT is minimal for the same rise time. For example,
the amount of undershoot is −360 mV with 50-ns rise time of the
load current for both the cases as shown in Fig. 14(a). However,
the case “Without-ILIM IT ,” provides a little faster settling time
(50 ns versus 80 ns) compared to the case “With-ILIM IT .” For a
rise time of 100 ns, both the cases provide the same undershoot
MAITY AND PATRA: TRADEOFFS AWARE DESIGN PROCEDURE FOR AN ADAPTIVELY BIASED CAPACITORLESS LOW DROPOUT
Fig. 14. Measured load transient response for a load steps of 10 μA–100 mA
with a rise time of (a) 50 ns for “With-IL IM IT ” (Ch-1), “Without-IL IM IT ”
(Ch-2), (b) 100 ns for “With-IL IM IT ” (Ch-4), “Without-IL IM IT ”(Ch-5).
Fig. 15. Measured load transient response with load steps between (a) 10 μA–
100 mA with rise/fall time of 1 μs, (b) 1–100 mA with a rise/fall time of
500 ns.
of −300 mV and the corresponding waveforms are shown in
Fig. 14(b). The amount of undershoot is still high due to the
very low quiescent current at Io = 10 μA and the faster rise
time of the load step. However, the settling time is quite fast due
to adaptive biasing and it is mostly limited by the rise time of
the load current.
The amount of undershoot and overshoot is far improved,
when the load switches either with the desired rise/fall time of
377
Fig. 16. Line transient response at Io = 100 mA with a sinusoidal input
frequency of 1 MHz for the case “With-IL IM IT .”
Fig. 17. Measured PSRR at Io = 100 mA for the case “With-IL IM IT .”
1 μs. For a load step of 10 μA–100 mA with a rise/fall time of
1 μs, the undershoot/overshoot is reduced to −110 mV/+85 mV
as shown in Fig. 15(a). Similarly, for a load step of 1–100 mA
with rise/fall time of 1 μs, the undershoot/overshoot are only
−5 mV/+34 mV as shown in Fig. 15(b).
The measured line transient response is shown in Fig. 16. A
200-mV peak-to-peak sinusoidal signal is superimposed using
a bias-tee [31] with a dc voltage of 1.6 V to generate the input
voltage Vin . For a sinusoidal frequency of 1 MHz, the peak-to-
peak variations of the output voltage is 10 mV at Io =100 mA
for the case “With-ILIM IT .” The measured PSRR at Io = 100
mA for the case “With-ILIM IT ” is shown in Fig. 17.
Fig. 18(a) shows the output voltage variation across the load
current change. The output voltage falls drastically above Io =
10 mA. Due to limited number of available bond pads, only
two pins have been assigned for the node Vo , the ESR of each
bond-wire is approximately 400 mΩ which creates an additional
drop of 20 mV for 100 mA load condition. Therefore, the load
regulation is 0.27 mV/mA. The measured line regulation is 0.6
mV/V as shown in Fig. 18(b).
Fig. 19(a) and (b) shows the comparison of the measured
quiescent current and the current efficiency across the load
current for the cases “With-ILIM IT ” and “Without-ILIM IT .” At
378
Fig. 18. Measured value of V o variation across (a) load current, (b) input
voltage.
Io = 10 μA, their IQ are 610 and 500 nA, respectively. In the
midrange of the load current, both consume almost the same
quiescent current. Above Io = 10 mA, the IILIM IT = 222 nA
clamps the IQ of the case “With-ILIM IT .” At Io,m ax = 100
mA, the IQ for “With-ILIM IT ” and “Without-ILIM IT ” are 141
and 915 μA, respectively, and it shows a reduction of nearly
84.6% in the IQ at Io,m ax . This provides a higher current ef-
ficiency [99.86% versus 99.09% as in Fig. 19(b)] for the pro-
posed “With-ILIM IT ” scheme. Therefore, the adopted design
procedure in the proposed topology offers an ultra low IQ at
lightest load while maintaining very high current efficiency at
maximum load current.
A performance comparison with previously reported regula-
tors is shown in Table III. [6], [27] and this study are stabilized
using the nested Miller compensation among them. However,
[6] uses a fixed biasing scheme, whereas an adaptive biasing
scheme is employed in [27] and this study. [32] and [31] are two
recent studies with different frequency compensation schemes.
In order to compare the various regulators, a figure of merit
2
FOM = Co ΔVo,pp IQ ,m in /ΔIo,m ax is adopted from [33]. Here,
ΔVo,pp is the maximum peak-to-peak transient variation which
includes undershoot (−ΔVo ) and overshoot (+ΔVo ) at the ex-
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 1, JANUARY 2016
Fig. 19. Comparison of the (a) measured quiescent current, (b) measured
current efficiency across the load current for the cases “With-IL IM IT ” and
“Without-IL IM IT .”
treme load step ΔIo,m ax . A lower FOM is always preferable. A
very low FOM in this study is quite attractive compared to the
other designs.
To compare directly with [27], both the regulators cover a
wide dynamic range of 10 μA–100 mA without any stability
issue. However, the salient features of this study are as fol-
lows. First, [27] requires the Q-reduction and spike detection
capacitors to cover the lower dynamic range of Io,m in = 10 μA,
whereas the proposed design procedure itself guarantees the Q-
reduction at the same range of Io,m in . Second, [27] requires a
dedicated sub-threshold undershoot reduction circuit to tackle
the undershoot during a load step of 10 μA–100 mA for a rise
time of 1 μs. A smaller value of AB ratio δ having a value
of 0.001 is chosen to achieve a maximum current efficiency of
99.62%. In this study, almost the same amount of undershoot
is achieved for a rise time of 1 μs by increasing the value of δ
to 0.006. The amount of overshoot is slightly higher because of
the use of only two bond-wires for the Vo pin that creates an
additional drop of approximately 20 mV. Third, the higher value
of δ significantly reduces the undershoot and overshoot for an
intermediate value to high load step (1–100 mA) even with a
MAITY AND PATRA: TRADEOFFS AWARE DESIGN PROCEDURE FOR AN ADAPTIVELY BIASED CAPACITORLESS LOW DROPOUT 379

TABLE III
PERFORMANCE COMPARISON WITH PREVIOUSLY REPORTED REGULATORS

[32] [31] [6] [27] This study

Technology (μm) 0.11 0.18 0.35 0.35 0.18

Active Area (m m 2 ) 0.21 0.14 0.125 0.0987 0.07
Minimum V i n (V) 2.2 1.8 1.2 1.2 1.4
Nominal V o (V) 2 1.6 1.0 1.0 1.2
Dropout Voltage (mV) 200 200 200 200 200
Load Range (mA) 200 50 0.100–100 0.01–100 0.01–100
Load Reg. (μV/mA) 108 160 338 78.2 270
Line Reg. (mV/V) 8.9 - 0.344 0.39 0.6
Decoupling Cap. C o (pF) 40 100 100 100 100
Compensation Cap. (pF) 3.2 28 5 5.4 9
Q -reduction Cap. (pF) - - 1 3.6 No
Spike Detection Cap. (pF) - - No 1 No
AB ratio δ - - - 0.001 0.006
I Q , m i n (μA) at I o , m i n 41.5 55 100 28 0.61
I Q , m a x (μA) at I o , m a x 41.5 80 100 380.01 141
Max. Current Eff. (%) 99.97 99.8 99.9 99.62 99.86
PSRR (dB) @ Freq. (Hz) - −70 @ 1M - −13.15 @ 1 M −26 @ 1 M
Edge time (n s) 500 100 1000 1000 1000 1000 500
Load step Δ I o , m a x (mA) 0.5–200 0–50 0.1–100 0.01–100 1–100 0.01–100 1–100
Undershoot −Δ V o (mV) −385 −80 −40 −105 −78 −110 −5
Overshoot +Δ V o (mV) +200 +120 +40 +50 +45 +85 +34
FOM (fs) 24.4 440 80 43.4 - 1.189 -

faster rise/fall time. Fourth, the current efficiency at high load
range is still maintained high by cutting down the excess bias
current in the proposed topology. Finally, the key advantage of
the proposed design procedure is the significant reduction of IQ
at minimum load condition. As the proposed procedure offers
an IQ of 610 nA at minimum load conditions, it is very attrac-
tive for ultra-low-powered SoC and battery-operated portable
applications.
VI. CONCLUSION
This paper first investigates various design tradeoffs and is-
sues of an AB-LDR topology which uses nested Miller com-
pensation. With a better understanding of that, a detailed design
procedure is also proposed in this paper. Some of the key con-
tributions of the proposed design procedure are as follows. A
relation between the fixed current bias component of the er-
ror amplifier and the minimum value of load current for stable
operation is derived. An optimal value of AB ratio is chosen
to improve the dynamic response. It is also shown that the ex-
cess bias current at high load condition does not improve the
dynamic response significantly over certain speeds of the load
transient. To reduce the excess bias current, a modification is
suggested in the proposed topology. The benefits of the pro-
posed design procedure are many. A regulator implemented in
0.18 μm CMOS technology, has a wide dynamic range of load
current (10 μA–100 mA), ultra low quiescent current of 610
nA, maximum current efficiency of 99.86% with a good tran-
sient response. The elimination of additional circuit/components
required in previously reported works, proves the effectiveness
of the proposed design procedure.
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Ashis Maity (S’15) received the B.E. degree from
Bengal Engineering and Science University, Shibpur,
India, in 2002, and the M.S. degree from the Indian
Institute of Technology, Kharagpur, India, in 2009.
He is currently working toward the Ph.D. degree at
Advanced Technology Development Center, Indian
Institute of Technology, Kharagpur.
During 2002–2005, he was working with Al-
liance Semiconductor, Bangalore, as a Member De-
sign Team. Then, during 2006–2008, he was working
as a Research Consultant in Advanced VLSI Design
Laboratory, Indian Institute of Technology, Kharagpur. During 2008–2009, he
was with National Semiconductor, Tokyo, Japan, as a Senior Design Engineer.
His research interests include power management ICs for portable applications
and low power, high performance analog ICs.
Amit Patra (M’87) received the B.Tech., M.Tech.
and Ph.D. degrees from the Indian Institute of Tech-
nology, Kharagpur, India, in 1984, 1986 and 1990,
respectively.
During 1992–1993 and in 2000, he visited the
Ruhr-University, Bochum, Germany, as a Postdoc-
toral Fellow of the Alexander von Humboldt Foun-
dation. He joined the Department of Electrical Engi-
neering, Indian Institute of Technology, Kharagpur,
in 1987 as a Faculty Member, and is currently a Pro-
fessor. He was the Professor-in-Charge, Advanced
VLSI Design Lab, IIT Kharagpur, during 2004–2007. Between 2007 and 2013,
he served as the Dean (Alumni Affairs and International Relations), IIT Kharag-
pur. His current research interests include power management circuits, mixed-
signal VLSI design and embedded control systems. He has guided 17 doctoral
students and published more than 200 research papers in various journals and
conferences. He is the Coauthor of two research monographs entitled General
Hybrid Orthogonal Functions and Their Applications in Systems and Control
(New York, NY, USA: Springer-Verlag, 1996) and Nano-Scale CMOS Ana-
log Circuits: Models and CAD Tools for High-Level Design (Boca Raton, FL,
USA: CRC Press, 2014). He has carried out more than 40 sponsored projects
mostly in the areas of VLSI and power management circuits and control sys-
tems. He has been consulted by National Semiconductor Corporation, Infineon
Technologies, Freescale Semiconductor and Maxim Corporation in the power
management area. As the Professor-in-Charge of Advanced VLSI Design Lab-
oratory, he also took the lead role in the formation of the AVLSI Consortium at
IIT Kharagpur to increase collaboration between the industry and the academic
community in the area of VLSI.
Dr. Patra received the Young Engineer Award of the Indian National Academy
of Engineering in 1996 and the Young Teachers Career Award from the All India
Council for Technical Education in 1995. He has been a Young Associate of the
Indian Academy of Sciences during 1992–1997. He is a Member of Institution
of Engineers (India) and a Life Member of the Systems Society of India.