1D-24
An Adaptively Biased Low-Dropout Regulator with Transient Enhancement
Chenchang Zhan and Wing-Hung Ki
The Hong Kong University of Science and Technology
Abstract—An output-capacitor-free adaptively biased low-
dropout regulator with transient enhancement (ABTE LDR)
is proposed. Techniques of Q-reduction compensation, adaptive
biasing, and transient enhancement achieve low-voltage high-
precision regulation with low quiescent current consumption
while significantly improving the line and load transient responses
and power supply rejections. The features of the ABTE LDR are
experimentally verified by a 0.35-μm CMOS prototype.
I. I NTRODUCTION
Low-dropout regulators (LDRs) are key components for
SoC applications [1]. The elimination of off-chip capacitors
can save pin count and board space and also reduce the bond-
wire-induced noise. However, the trade-off among quiescent
current (IQ ), low-voltage operation, precision, stability, loop
bandwidth, and transient responses imposes critical challenges
on the design of output-capacitor-free LDRs [2-4].
In this work, we propose an output-capacitor-free LDR
with adaptive biasing (AB) and worst-cases load transient
enhancement (TE). The desirable features of low IQ , low-
voltage operation, high-precision regulation, fast transient re-
sponses and high power supply rejections (PSRs) are achieved
simultaneously.
II. P ROPOSED L OW- DROPOUT R EGULATOR
Fig. 1 shows the architecture of the proposed adaptively
biased LDR with transient enhancement (ABTE LDR). It
consists of an error amplifier (EA), a simple current mirror
(SCM) which implements the AB, a TE block, a power MOS
MP and a resistive feedback divider. The CP P in dashed
line stands for the parasitic capacitance due to on-chip power
distribution and load parasitic, which is usually in the range
of 10pF-100pF [2-3]. The multi-stage EA, which is biased by
a fixed biasing current IF B and an AB current IAB , provides
high-precision regulation with low-supply voltage and even
when the MP works in linear region which will lead to a great
saving of chip area [2]. The AB scheme provides enlarged
biasing current IAB (=δIload ) for the EA with heavy load
and hence achieves extended loop bandwidth. By designing
a small current scaling factor δ such as 0.1%, high current
efficiency (ηC ) is achieved. The SCM implementation of AB
is easy to design and is area-efficient. As IAB is small at light
load, the load transient from light to heavy will be poor due
to the small slew rate. The TE block alleviates this problem. It
detects the VOU T undershoot and ignites a large discharging
current IGD to pull down the gate voltage of MP quickly and
hence achieves a fast recovery of VOU T .
The schematic of the ABTE LDR is shown in Fig. 2 (a). The
EA consists of M1 − M8 with the IF B provided by MF B and
the IAB by MAB . CM and CQ are the Miller compensation
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Fig. 1. Architecture of the proposed ABTE LDR.
and Q-reduction capacitors to achieve wide load stability [3].
The SCM is made up by MS1 − MS4 . MS1 senses the current
of MP and its size ratio to MP is 1: N. By designing a large
N value such as 1000 in this work, the current consumed by
SCM is small (compared to the load) even at heavy load and
high ηC is hence achieved [2].
The TE block consists of MT 1 − MT 9 and the detection
capacitor CT . The basic working principle of the TE circuit is
similar to the differentiator-based fast transient path developed
in [1]. When VOU T has a sudden reduction due to the load
step-up, CT will detect the VOU T undershoot and VT 1 hence
VT 2 is also reduced and VT 3 increased. Consequently, MT 9
conducts an enlarged current to discharge the gate of the power
MOS and VGP is reduced to allow quick recovery of VOU T .
MT 1 − MT 9 are biased in weak-inversion region in the steady
state and the current I consumed by the TE block is small
(only 1.2μA in this design). Therefore, the situation when
VOU T has a sudden increase due to load step-down is different.
In this case, MT 9 has an even smaller gate-source voltage
and is hence still in the cut-off region. The excellent transient
responses when load current steps down from heavy to light
is due to the AB scheme: fast charging of the gate capacitance
of MP is achieved as the EA has a large IAB at heavy load.
As a result, the proposed ABTE LDR achieves fast transient
responses in both the load step-up and step-down cases.
III. E XPERIMENTAL R ESULTS
The proposed ABTE LDR is fabricated in a standard 0.35-
μm CMOS process. For comparison, the counterpart FB
LDR without the adaptive biasing and transient enhancement
is also fabricated in the same die. Fig. 2 (b) shows the
chip photograph of the ABTE LDR, with an active area of
0.0957mm2 . Compared to the 0.0824mm2 of the FB LDR,
the area overhead is only 16.1%. A 100pF capacitor is used
to emulate CP P . For both of the LDRs, the minimum VDD
is 1.2V with the preset VOU T =1.0V. The maximum Iload is
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 1D-24

535 µm

735 µm
(a) (b)

Fig. 2. (a) Schematic and (b) Chip photo of the proposed ABTE LDR.

100mA. The measured line regulations at Iload =100mA are

1.77 and 0.95mV/V for the FB LDR and ABTE LDR. The
measured load regulations for the two LDRs at VDD =1.2V
are 32 and 31μV/mA. Fig. 3 shows the measured IQ and ηC
of the two LDRs. The IQ of the FB LDR and ABTE LDR at
no load, including the 10 μA consumed by the resistive divider
(RF 1 and RF 2 ), is 27.4 μA and 27.5 μA. At the maximum
load, the IQ is 25.5 μA and 360.8 μA, while the ηC is 99.98%
and 99.64% for the FB LDR and ABTE LDR, respectively. At
load current above 1mA, the ηC is better than 97% for both Fig. 3. Measured (a) quiescent current and (b) current efficiency.
of the LDRs.
100mA 0mA 100mA
Iload Iload
Fig. 4 (a)–(d) show the measured transient responses of 1mA

the two LDRs under the same load current or line voltage ABTE LDR

scenarios. The VOU T changes (under- and over-shoot) are re- ABTE LDR

duced from -420/+150mV to -50/+55mV, from -780/+155mV FB LDR

to -115/+65mV, from -50/+86mV to -11/+19mV and from - FB LDR 5ȝs 5ȝs

54/+96mV to -8/+14mV, respectively. Fig. 5 shows the mea- 200mV 200mV

sured PSRs of the two LDRs at load currents of 50mA CPP=100 pF, VDD= 1.2 V, VOUT= 1.0 V CPP=100 pF, VDD= 1.2 V, VOUT= 1.0 V
and 100mA, respectively. The PSRs at 100kHz are reduced
(a) (b)
from -10.25dB to -29.67dB and from -9.57dB to -32.87dB,
300mV 300mV
respectively. 1.8V 1.8V

VDD VDD

IV. C ONCLUSIONS ABTE LDR

1.2V
ABTE LDR
1.2V

This paper presents an output-capacitor-free ABTE LDR. 60mV 5ȝs 60mV 5ȝs

By employing Q-reduction compensation and adaptive biasing, FB LDR FB LDR

the loop bandwidth is extended, while low IQ and high ηC are

maintained. The SCM implementation of adaptive biasing is
CPP=100 pF, VOUT= 1.0 V, Iload= 50 mA CPP=100 pF, VOUT= 1.0 V, Iload= 100 mA
area-efficient. An ultra-low power and low-voltage compatible
transient enhancement circuit improves the worst-cases load (c) (d)
transient responses. Experimental results demonstrated that the Fig. 4. Measured transient responses of the two LDRs: (a) load transient
proposed LDR achieves significant improvements in line and between 1 and 100mA with about 0.5μs edge time; (b) load transient between
load transient responses and PSRs. 0 and 100mA with about 0.5μs edge time; (c)line transient when load=50mA
and (d) line transient when Iload =100mA.
R EFERENCES
[1] R. J. Milliken, J. Silva-Martinez, and E. Sanchez-Sinencio, ”Full on-chip
CMOS low-dropout voltage regulator,” IEEE Tran. Circ. and Syst. I, Reg.
Papers, vol. 54, no. 9, pp. 1879-1890, Sept. 2007.
[2] C. Zhan and W. H. Ki, ”Output-capacitor-free adaptively biased low-
dropout regulator for system-on-chips,” IEEE Tran. Circ. and Syst. I,
Reg. Papers, vol. 57, no. 5, pp. 1017-1028, May 2010.
[3] S-K. Lau, P. K.T. Mok and K. N. Leung, ”A low-dropout regulator for
SoC with Q-reduction,” IEEE J. Solid-State Circ., vol. 42, no. 3, pp.
658-664, Mar. 2007.
[4] Y. H. Lam, W. H. Ki and C. Y. Tsui, ”Adaptively-biased capacitor-less
CMOS low dropout regulator with direct current feedback,” IEEE Asia
and South Pacific Conf. on Design Automation, pp. 104-105, Jan. 2006. Fig. 5. Measured PSRs at (a) Iload =50mA and (b) Iload =100mA.

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