IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 58, NO.
4, JULY/AUGUST 2022
Compact Quadratic Boost Switched-Capacitor
Inverter
Mohamed AliJagabar Sathik , Senior Member, IEEE, Marif Daula Siddique , Member, IEEE,
N. Sandeep , Senior Member, IEEE, Arpan Hota , Student Member, IEEE,
Dhafer Almakhles , Senior Member, IEEE, Saad Mekhilef , Fellow, IEEE,
and Udaykumar R Yaragatti , Senior Member, IEEE
Abstract—This article presents a new topology for a single-stage
nine-level (9L) switched-capacitor inverter. The structure of the
proposed topology is not only simple but also compact. The pro-
posed topology is developed with self-voltage balancing and a low
number of power components. The output voltage (vo ) gain is four
times higher than the input voltage (vin ). Each mode of opera-
tion is discussed with a detailed current path. The conventional
sinusoidal pulsewidth modulation technique is used to generate
the gate pulses. Next, the experimental results are obtained from
a 1 kW prototype setup. The proposed topology is tested under
different scenarios such as load change, input voltage changes, and
modulation variations. Both simulation and experimental results
have good agreement in terms of efficiency. Finally, a detailed
comparative study is performed with other recent 9L inverters to
prove the merits of the proposed topology.
Index Terms—Boost inverter, high-gain converter, multilevel
inverter, self-voltage balancing, switched capacitor (SC).
Manuscript received December 10, 2021; revised April 12, 2022; accepted
April 28, 2022. Date of publication May 3, 2022; date of current version July
19, 2022. Paper 2021-IPCC-1280.R1, presented at 2020 IEEE International
Conference on Power Electronics, Drives and Energy Systems, Jaipur, India,
Dec. 2916–19, and approved for publication in the IEEE TRANSACTIONS ON
INDUSTRY APPLICATIONS by the Industrial Power Converter Committee of the
IEEE Industry Application Society. This work was supported by the Renewable
Energy Laboratory (REL), College of Engineering, Prince Sultan University,
Riyadh, Saudi Arabia. (Corresponding author: Marif Daula Siddique.)
Mohamed AliJagabar Sathik is with the Renewable Energy Laboratory,
College of Engineering, Prince Sultan University, Riyadh 11586, Saudi Arabia
(e-mail: mjsathik@ieee.org).
Marif Daula Siddique is with the Energy Harvesting and Mechatronics
Research Laboratory, Department of Mechanical Engineering, Virginia Tech,
Blacksburg, VA 24061 USA (e-mail: marifdaula1@gmail.com).
N. Sandeep and Udaykumar R Yaragatti are with the Department of Electrical
Engineering, Malaviya National Institute of Technology, Jaipur 302017, India
(e-mail: sandeep.n@ieee.org; udaykumarry@yahoo.com).
Arpan Hota is with the Department of Electrical Engineering, Indian In-
stitute of Technology Bombay Mumbai, Mumbai 400076, India (e-mail:
hota.arpan@gmail.com).
Dhafer Almakhles is with the Renewable Energy Laboratory, College of
Engineering, Prince Sultan University, Riyadh 11586, Saudi Arabia (e-mail:
dalmakhles@psu.edu.sa).
Saad Mekhilef is with the School of Science, Computing and Engineering
Technologies, Swinburne University of Technology, Melbourne, VIC 3122,
Australia, also with the Power Electronics and Renewable Energy Research
Laboratory, Department of Electrical, Faculty of Engineering, University of
Malaya, Kuala Lumpur 50603, Malaysia, and also with the Department of
Electrical Engineering, College of Engineering, Universiti Tenaga Nasional,
43000 Kajang, Selangor, Malaysia (e-mail: saad@um.edu.my).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TIA.2022.3172235.
Digital Object Identifier 10.1109/TIA.2022.3172235
0093-9994 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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4923
I. INTRODUCTION
ULTILEVEL inverters, i.e., MLIs have been examined
M for the past several years, are considered as the main
element in renewable energy production for medium/high power
or voltage with improved performance. The multilevel inverters
are well-matured power converters due to their unique fea-
tures and applications such as ac drives, renewable energy,
and other medium-high voltage applications. The main bene-
fits of MLIs refer to the improved harmonic profile of output
voltage, lower stress on switches, dv/dt reduction, lower filter
specifications, and higher modular structure. The conventional,
multilevel topology is available in three types: neutral-point-
clamped (NPC) topology, flying capacitor (FC) topology, and
cascaded H-bridge topology. In addition, auxiliary balancing
circuits, sensors for current and voltage, or algorithms with the
complicated structure are necessary for NPC and FC for main-
taining the voltage balance of the capacitors. These all result
in further complications in the control with deterioration in the
performance. The electricity generated by renewable energies,
such as photovoltaic arrays and fuel cells, is largely low voltage
and has to be turned into higher ac-voltage. One traditional
solution is to cascade a dc–dc booster conversion stage at the
front-end with a conventional back-end MLI. A new perspective
to solving the foregoing problems is extensively investigated as
a switched capacitor multilevel inverter (SCMLI) [1]–[4].
Several efforts are being made to produce high voltage levels
with lower components, reduced isolated sources, and inherent
boost capabilities. As an intermediary level generating device,
capacitors have drawn considerable attention. FCs play a crucial
role in the generation of intermediate voltage levels in the hybrid
MLI. However, a complex control circuit is required, to maintain
the capacitor voltages at their required value. In addition, only
half the source voltage at the load terminals is developed [5].
In other words, such circuits function as converters for the step
down of the source voltage. Efforts are later made to increase
the output voltage without using any inductors and transformers
across the output terminals. In that regard, Marusarz [6] initially
proposed the switched capacitor (SC) concept in 1989. The
SC inverters received more attention from the researcher due
to their advantages like high voltage gain and high stepped
output voltage waveform. Such inverters are more suitable
for medium voltage applications, including distributed power
4924
Fig. 1. Quadruple boost type inverters. (a) Proposed in 2016 [24]. (b) Proposed in 2021 [20]. (c) Proposed CQB-9L inverter circuit diagram.
TABLE I
SWITCHING SEQUENCE FOR PROPOSED 9L INVERTER TOPOLOGY
↑ - Charging the FCs, ↓=Discharging the FCs, vMax,Str - Maximum voltage stress
on switch, iMax,Str - Maximum current stress on switch.
generation systems. The two-level SCI has challenges as high
input voltage, high total harmonics distortion, and bulky LC filter
[7]. Henceforth, there are several topologies with self-balance
and with an ability to perform voltage boosting. Hinago and
Koizumi [8] and Lin et al. [9] presented an SCMLI circuit with
an increased voltage booting factor. These SC structures produce
voltage levels and the H-bridge produces different output polar-
ity. In addition, topologies in [8], [9] require a large number of
capacitors and semiconductor devices to produce higher voltage
levels. However, among the different semiconductor devices,
voltage stress is, moreover, on the H-bridge switches, which are
involved in polarity generation. Single-stage inverter circuits
to address the issue of double-stage boost MLIs have been
suggested in [10]–[12]. These topologies are modular in their
nature and produce zero/negative levels without an H-bridge.
The peak inverse voltage of these topologies are vin and the
increase of unity voltage gain per capacitor. However, these
circuits require more semiconductors and capacitors to extend
the topology to higher levels.
The combination of SCMLI is introduced in [8], [13]–[25]. A
new generalized structure of SCMLI topology is proposed in [8],
[23] with a higher number of output voltage levels, but the total
number of switch counts are increased with a voltage gain of 1: n
(vin : vo ), and it requires three capacitors with a voltage rating of
vin . The topologies [8], [13]–[15], [21], [23], [24] are developed
to generate the dedicated nine-level (9L) output voltage. These
topologies have a common voltage gain of 1:2 and need two
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 58, NO. 4, JULY/AUGUST 2022
SCs to generate a 9L output voltage waveform. However, each
topology has its pros and cons. For example, more components
are needed in [4], whereas authors in [15] successfully reduce
the switch count. However, it needs to emphasize that both
topologies produce the gain of 1:2. Another topology, which
requires eight unidirectional switches and two RB-IGBTs, is
proposed in [21], and eight switches, two diodes, and three
capacitors are used in [14]. A new topology [24] has nine
unidirectional switches, one diode, and two capacitors as shown
in Fig. 1(a). However, these topologies’ voltage gain is 4vin , and
most of the switch voltage stress is high. To reduce the voltage
stress on the switches, new topologies are reported in [16], [22]
with voltage stress of vin , but the number of the semiconductor
device is considerably high. Furthermore, to increase the voltage
gain and reduce the switch count, a new quadratic voltage
boost-type inverter is presented in [18], [19], and [25]. The
topology in [25] uses a maximum of 12 switches with voltage
stress of 2vin and it requires two SCs with a voltage rating of vin
and 2vin . To reduce the switch count, a new boost type 9L-level
inverter topology is proposed in [19]; but still, the switch count
is high and the voltage stress is 4vin . In [18], the three SCs
are used with a voltage rating of vin and 2vin but the on-state
conducting devices, and the total power components count is
high. Also, the voltage stress on the switch is equal to 4vin .
Another quadratic boost topology is proposed in [20] and shown
in Fig. 1(b) and this topology has more power components.
From the above discussion, the component count and voltage
stress on the component are inversely proportional. This article
aims to introduce a new compact quadratic voltage boost (CQB)
inverter with a reduced total power component. The proposed
topology successfully reduces the number of power components,
achieving a low voltage rating of SCs and low power loss with
a maximum of ∼95.2% efficiency.
II. PROPOSED CQB SCI TOPOLOGY
A detailed explanation of the circuit diagram and the modes
of operations are discussed for the proposed CQB-9L inverter.
A. Structure of 9L Inverter Topology
Fig. 1(c) shows the proposed 9L inverter topology structure as
shown, and it has a single dc-source with two SCs (CF1 and CF2 )
rated to vin and 2vin , respectively. The switches S4 and S6 are
SATHIK et al.: COMPACT QUADRATIC BOOST SWITCHED-CAPACITOR INVERTER
Fig. 2. Modes of operation of proposed 9L-inverter. (a) +4vin . (b) +3vin . (c) +2vin . (d) +vin . (e) +0vin . (f) −vin . (g) −2vin . (h) −3vin . (i) −4vin .
connected to the C1 to charge and discharge the voltage based
on the load requirement. Similarly, C2 is connected with S3 and
S4 . The switch pairs (S1 , S2 ), (S3 , S4 ), and (S6 , S7 ) should not
be turned ON simultaneously to avoid short circuit with the same
source. The switches (S1 , S2 ) and (S6 , S7 ) have low switching
frequency and less commutation. The Switching sequence of
proposed Topology is given in Table I.
B. Modes of Operation of Proposed 9L Inverter
Fig. 2(a)–(1) shows the various modes of operation discussed
with the current path for both charging and load. The positive
half cycle is explained and for the negative half cycle charging
directions are the same, but the polarity switches S1 and S7 will
be turned instead of S2 and S8 .
State D (+vin +VC1 +VC2 ): The SC C1 and C2 are discharg-
ing, and simultaneously, the load voltage is equal to +4vin, as
shown in Fig. 2(a).
r For load: S5 ↓ C1 → vin → S4 ↓ C2 → S8 → S2 → C1 .
State C (+vin +VC2 ): The SC C1 is not connected with either
load or +vin, but the C2 is connected with load and discharging.
The load voltage is equal to +3vin, as shown in Fig. 2(b).
r For load: vin → S4 ↓ C2 → S8 → S2 → D2 → vin .
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4925
State B (+vin +VC1 ): The SC C1 is discharging, but the C2 is
charging to +2vin, and simultaneously the load voltage is equal
to +2vin, as shown in Fig. 2(c).
r For charging of C2 : ↓ C1 → S5 ↓ vin → D1 ↑ C2 → S3 →
C1 .
r For load: ↓ C1 → S5 ↓ vin → D1 ↑ C2 → S2 → S8 →
C1 .
State A (+vin ): The SC C1 is charging to vin (C1 = vin ), and
simultaneously the load voltage is equal to +vin, as shown in
Fig. 2(d).
r For charging of C1 : vin → D1 → D2 ↑ C1 → S6 → vin .
r For load: vin → D1 → D2 ↑ C1 → S2 → S8 → vin .
State O (+0vin ): The SC C1 is discharging, and simultane-
ously the load voltage is equal to +0vin, as shown in Fig. 2(e).
r For charging of C1 : vin → D1 ↑ C1 → S6 → D2 → vin .
III. PULSEWIDTH MODULATION SCHEME
A. Pulse Generation
The conventional multicarrier level-shifted pulsewidth mod-
ulation scheme is adopted in the proposed topology, as shown
in Fig. 3. The carrier signal amplitudes are Ar, 2Ar, 3Ar, and
4Ar. Each triangular carrier signals have the same frequency and
4926 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 58, NO. 4, JULY/AUGUST 2022

with θ3 to find the ΔVrip and Copt for C2

4vin
ΔVrip = × (π − 2θ2 ) (6)
2πff RL C
4vin
Copt = × (π − 2θ2 ). (7)
2πff RL ΔVrip
When the capacitor is connected parallel to the dc-source, the
voltage across the capacitor equals the dc-source. Here worth
mentioning that the SCs have equal charging and discharging
periods in both positive and negative cycles, which reduce the
size of the capacitors. The charging current and capacitor voltage
is calculated based on the parasitic and discharging path, as
shown in Fig. 4. For unity power factor load, the iC1 and iC2
Fig. 3. Typical 9L voltage waveform. are obtained as
vin − VC1 − VF D
iC1 = (8)
phase with an amplitude increment of one. The carrier signals rDS + rESR1 + rD
reference signal (Aref ) and fundamental waveform reference vin + VC1 − VF D − VC2
(Vref ) are compared, where the carrier magnitude is (Ar ), and iC2 = . (9)
2rDS + rD + 2rESR1
θ1 –θ4 are the switching angles. The corresponding pulse signals
are generated based on the logic functions are S5 = X2 X3 + X4 , The capacitor voltages during the charging are obtained from
S4 = X3 , S3 = S4 , and S6 = X1 X2 . (10) and (11). Where rESRi , rD , rDS, VFD , VD,sw , and VD
For the positive half cycle, the switches S2 , S8 will be turned are capacitance equivalent resistances, diode-resistance, switch-
ON, and for the negative half cycle S1 , S7 will be turned ON with
resistance, a forward voltage drop of the diode, ON-state voltage
a low switching frequency. drop of the switch, ON-state voltage drop of the diode. τ and
iC,avgi (i = 12) are the time constant equal to the product of
B. Designing of Capacitors total circuit resistance and capacitance and average current in
The maximum discharging period occurs for SC2 during the the path, respectively
time interval [θ3 - (π-θ3 )] (state C) and for the SC1 [θ2 - (π-θ2 )] VC1 = [vin − ((Von,sw + VD ) + ((rDS + rD ) + rESR1 )
(state D). The capacitor requires the maximum charge given in  
(1), where iL represents the load current and ω = 2πff . As θ2 is × iC,avg1 )] 1 − exp−t/τ (10)
obtained in (7). Similarly, θ3 can be obtained
 π−θ3 VC2 = [vin + VC1 (t) − (2 (Von,sw + VD ) + (2rDS + rD
iL  
ΔQ = dωt (1)
θ3 ω + rESR1 + rESR2 ) × iC,avg2 )] 1 − exp−t/τ .
 
sin −1 3At (11)
θ2 = Aref /2πfref (2)
  IV. POWER LOSS ANALYSIS
−1 4At
θ3 = sin /Aref
2πfref (3)
The power losses of the proposed 9L SCMLI, like other power
where At - is triangular signal amplitude and Aref is amplitude electronics systems, can mainly be classified as switching losses
of the reference signal. The maximum voltage ripple occurred and drive losses. The loss of conduction is caused by parasite
at the resistive load and the maximum discharge value for pure resistors and forward voltage drops in power equipment when
resistive load. Therefore, the ΔQ (charge amount flowing out current flows through them. As there are two types of current
capacitors) can be calculated as in (4) and (5) for capacitors C1 (one flows into condensers, i.e., charge current, and one flows
and C2 , respectively through the load, i.e., the load current) within the SC-based
inverter, the loss of conduction can, therefore, be further grouped
4vin into condenser load loss caused by the charge current and
ΔQC1 = ((π − θ2 ) − θ2 ) (4)
2πff RL conduction loss caused by the load current.
4vin 1) Conduction losses: For the proposed SC-MTI, steps for
ΔQC2 = ((π − θ3 ) − θ3 ). (5) analyzing power losses are presented in literature which
2πff RL
can be applied conveniently. The conduction losses can
The ripple value (ΔVrip ) across the capacitor C1 is obtained generally be calculated by considering the dissipated
(6) as RL is the resistive load and ff is the inverter output voltage power because of the internal resistance of the switches,
frequency. The optimum value for each capacitor (Copt ) can be the power switches that are used in the proposed topology
given in (7) whose minimum value of capacitance is needed to support the bidirectional current flow and block the voltage
store the required energy. Instead, on the same line, θ2 is replaced in one direction. Therefore, the conduction loss of a switch

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SATHIK et al.: COMPACT QUADRATIC BOOST SWITCHED-CAPACITOR INVERTER
Fig. 4. Parasitic charging and discharging. (a) Charging path for C1 . (b) Discharging C1 and charging path for C2 . (c) Discharging path C2 . (d) Discharging of
both C1 and C2 .
Fig. 5. Power component loss breakdown using PLECS for 1 kW.
combines the losses of the switch and its antiparallel diode
and can be calculated as [26]
Pcon,sw = VO,sw i (t) + Rsw iβ (t)
Pcon,d = VO,d i (t) + Rd i2 (t)
where Pcon,sw and Pcon,d account for the switch and diode
conductive loss with the current i (t), respectively. Vo,sw and
Vo,d are the switch and diode ON-state voltage drop, respectively.
Rsw and Rd are switch and diode resistance in ON mode. β is
constant which corresponds to transistor characters and can be
found in the datasheet.
1) Switching losses: The switching losses (Psw ) of a switch
has a significant effect on the performance of the inverter.
Its calculation is based on the blocking voltage (Vbv ) of
the switch, current though it (Isavg ), the turn ON (tON ) and
turn OFF (tOFF ) time and can be calculated as [27]

tON  tOFF
fs
Psw = × Vbv Isavg dt +
6 o o
(14)
where fs is the switching frequency.
1) Ripple losses: Because of the disparity between charging
voltage and capacitor voltage, ripple losses (Prip ) occur in
the capacitors. The power loss in the charging processes
would be absorbed by switch ON-resistance, capacitor
ESR, and diode forward voltage in the charging loop. The
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4927
ripple losses of the capacitors can be calculated as [28]
fs  2
Prip = × ΔVrip_i × Ci (15)
2 i=1
where ΔVrip _i denotes the ripple voltage of capacitor Ci.
The power loss analysis of the proposed topology has been
carried out in PLECS software. The individual component’s
power loss breakdown is given in Fig. 5. Due to the charging
current, the losses are a little high in SCs and few IGBTs.
V. RESULTS DISCUSSION
The performance of the proposed topology is validated in the
PLECS software tool and practical implementation. The input
dc source voltage is 100 V, the SC C1 = 100 V/1700 μF and C2 =
200 V/1700 μF are chosen based on (10) and (11), in which this
maximum ripple % is selected 5%, and the switching frequency
(12) is 5 kHz. The two different resistive–inductive loads are used
with R = 100 Ω, L = 50 mH and R = 50 Ω, L = 100 mH. The
(13)
output voltage and current waveform with two different loads
are given in Fig. 6(a), and its corresponding capacitor ripple
voltage is shown in Fig. 6(b). The output voltage and current
waveform with two different loads are given in Fig. 6(a), and its
corresponding capacitor ripple voltage is shown in Fig. 6(b).
In an SC inverter, topologies have a drawback of high charging
current which draws more current during charging. However, in
the proposed topology, a loop inductor is inserted, as shown in
μH to maintain the charging current
Fig. 7 with a value of 10 to 50
within the limit (ILI = 21 LFindC
ΔV FC ) [17], where ILI - loop
inductor current, Lind inductor value, SC is capacitor value. The
maximum charging current (ic ) is (3iC − 4iC ≥ io ) as shown
 in Fig. 8. The maximum capacitor current is iC1 = ∼20 A and
iC2 = ∼30 A at load changing from R = 100 Ω, L = 50 mH
Vbv Isavg dt
to R = 50 Ω, L = 100 mH and this is achieved due to the loop
inductor. The charging current C2 is higher than the C1 due to
the high voltage in C2 .
In the experimental prototype, as shown in Fig. 9, the
loop inductor value is chosen as 33 μH. For experi-
mental validation, 1-kW prototype model was rigged up
with the dc-source 0–600 V/0–100 A, the capacitors C1 -
2200 µF/100 V (ALC80(1)222CD100) and C2 -2200 µF/220 V
4928
Fig. 6. Simulation results during load changes. (a) Output voltage. (b) FCs voltages.
Fig. 7. Proposed CQB inverter topology with charging inductor (Lind ).
Fig. 8. Capacitor current during load changes.
(ECET2DP332FA). The power electronics devices are selected
as IGBTs/Diode (600 V, 60 A,) STGW39NC60VD from STMi-
croelectronics, RB-IGBT (600 V,60 A) IXRH50N60 from
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 58, NO. 4, JULY/AUGUST 2022
Fig. 9. Prototype setup.
IXYS, and diode (200 V, 30 A) HER3003 from dc components
is used. The power rating of the designed prototype is 1 kW
The output voltage and current waveforms for R = 50 Ω, L =
100 mH with a power factor of 0.85 are presented in Fig. 10(a),
confirming that the output voltage is 400 V which is four times
higher than the input voltage. Further, the load variation from R
= 100 Ω, L = 50 mH to R = 50 Ω, L = 100 mH is validated in
prototype setup, and the corresponding waveforms are shown in
Fig. 10(b). It shows that the proposed topology can maintain the
SC voltages and output voltage step during sudden load changing
conditions.
The proposed topology performance is tested by varying the
modulation index, and the corresponding waveform is shown
in Fig. 11(a). As said earlier, in SCMLI topology, the inrush
current is a big challenge and the inrush current is significantly
suppressed by inserting a loop inductor. In Fig. 11(b), the inrush
current is a little higher than the actual calculated value.
The waveforms of the output voltage and current have been
analyzed with their harmonic spectrum and are shown in Fig. 12.
The voltage THD is 13.1% without any filter with all the lower
SATHIK et al.: COMPACT QUADRATIC BOOST SWITCHED-CAPACITOR INVERTER 4929

Fig. 10. Experimental results output voltage and current waveform. (a) For Fig. 11. Experimental results output voltage and current waveforms (a) during
R= 50 Ω, L=100 mH. (b) during R = 100 Ω, L = 50 mH to R = 50 Ω, modulation index variations and (b) FCs currents.
L = 100 mH with FC voltages.

order harmonics less than 5%. Similarly, the current THD is

2.5%.
In last, the comparison of the efficiencies of the proposed
topology with simulation and experimental results have been
shown in Fig. 13. The simulation efficiency of the proposed
topology is 96.5%, with a total loss of 34.40 W for ∼1 kW
output power. But in experimental, the measured efficiency is
∼95.2% for unity power factor with a power loss of ∼48.0 W.

VI. COMPARATIVE STUDY

In order to show the improvement of the proposed topology
compared to the existing topologies, a compensative study has
been accomplished in this section. For the comparison, the
topologies with the booting factor have been considered which
produced 9L output waveform across the load. The comparison
of the proposed topology with other recent 9L-level SCMLI is
given in Table II and it is confirming that the total component
count is low in CQB-SCI. Moreover, the contribution of the
maximum component in voltage gain is given as TComp /G. Since
the proposed topology is a family of SC inverters, it should
be evaluated in terms of the number of SCs versus G and it
confirms that the proposed topology is superior than the other Fig. 12. Experimental harmonic spectrum of proposed inverter output
9L topologies. (a) voltage THD and (b) current THD.

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4930
TABLE II
COMPARISON OF PROPOSED TOPOLOGY WITH OTHER RECENT 9L INVERTER TOPOLOGIES
NSW /NGD / ND /NFC - Number of switches/gate driver/diode/floating capacitor, TComp - Total component count, FCMax - Maximum voltage rating of FC, NFCMax -
Number of FCs with maximum voltage rating, G - voltage gain, MSVp .u - Maximum standing voltage, PLoss - Power loss in watts.
Fig. 13. Efficiency plot of the proposed topology.
VII. CONCLUSION
This article has presented a new quadratic boost inverter
topology with reduced total power component counts and it is
confirmed from the above discussion. The performance of the
proposed topology was analyzed in both simulation and proto-
type experimental setup. Both the results were well supported
and it is proved that the proposed topology has self-voltage
balancing and boosting ability. Further, CQB can withstand any
sudden changes at the load and source sides. The proposed
topology is working well at a power factor between 0.79 and
1.0 with a maximum efficiency of ∼95.2%. However, in most
real-time applications, the maximum lagging power factor will
be 0.79–1.0. The comparison between the proposed topology
and similar recent topologies also shows the superiority of the
proposed topology in component count, efficiency, and voltage
gain, which are remarkable advantages of the proposed topology.
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[2] M. Vijeh, M. Rezanejad, E. Samadaei, and K. Bertilsson, “A general
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