2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering
(UPCON)
A Modified Seven Level Cascaded H Bridge
Inverter
Anil Kumar Yarlagadda1 Vargil kumar Eate2
Dept. of Electrical Engineering Dept. of Electrical Engineering
Gudlavalleru Engg. college, India Gudlavalleru Engg. College,
yanilkumar202@gmail.com India
Abstract—Presently Multilevel inverters are extensively used for
high-voltage applications and their execution is exceptionally
better to that of regular two-level inverters due to minimized
harmonic distortion, lower electromagnetic interference and
larger DC link voltages. Nevertheless certain shortcomings are
faced such as adding in number of components and voltage
balancing problem. In order to overcome these, a seven-level
hybrid inverter has been proposed. This topology requires a
lesser number of power switches which results in the decrease of
multifaceted nature, add up to cost and weight of the inverter.
Finally this can be able to generate near sinusoidal voltages and
approximately fundamental frequency switching. The simulation
and the experimental results of a modified cascaded seven level H
bridge inverter with and without LC filter are presented for
validation.
Keywords—Cascaded H-bridge inverter (CHBI), seven level hybrid
inverter, asymmetrical DC sources, Total harmonic distortion
(THD), Pulse Width modulation (PWM), Multi-level Inverter
(MLI), Real time Interface (RTI)
I. INTRODUCTION
In ancient days a two-level conventional inverter had been
used, the output of this conventional inverter is quasi square
wave, and this quasi square wave consists of the lower order as
well as the higher order harmonics, these can be eliminated by
using the passive filters. But it is not advisable to use the
passive filter in order to eliminate the lower order harmonics
because of high cost and large size of inductor and capacitor
has to be used. From the MATLAB/simulation model of a
single phase two level square wave inverter, THD of an output
voltage is 48.21% [8], [9]. Presence of higher harmonic rate,
can deteriorate the performance and may also reduce the
lifespan of the equipment. Minimization of harmonics was
addressed by various methods, of which the PWM and
Multilevel inverters are familiar. In the PWM method copious
switching happens when compared to the multi-level inverter.
Presently multilevel inverters drew more attention and
found their prominence in both research and industry towards
the high and medium range voltage operations, mutually with
other benefits such as in improving the power quality, reduced
size of harmonics, stair case wave form quality, lower dv/dt
variations, minimized losses due to switching, and enhanced
electromagnetic interference[1],[2]. The popular applications of
the multi-level inverters are motor drives, power conditioning
978-1-5386-5002-8/18/$31.00 ©2018 IEEE
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Y.S.Kishore Babu3 Abanishwar Chakraborti4
Dept. of Electrical Engg. Dept. of Electrical Engg.
JNTUK,UCEN,Narasaraopet N.I.T Agartala, India
India
devices, electric vehicles, flexible AC transmission systems
[7], renewable energy harvesting and distribution.
Basically there are three types of MLI’s in the literature.
First one is diode clamped MLI, second one is flying capacitor
MLI, third one is cascaded H Bridge MLI. [3]-[5]. The
classification in cascade multilevel inverter (CMLI) into two
groups namely: 1) Symmetric CMLI - comprising of identical
magnitudes of DC voltage sources; 2) Asymmetric CMLI -
having dissimilar magnitude of the DC voltage sources.
Among the above-mentioned types, cascade H-Bridge MLI are
given importance because of the factors like modularity and
simplicity [8]. Different schemes of modulations may be
applied to CHBI, which offer the flexibility of incorporating
multiple voltage levels at the output by the addition of required
number of H bridges. However, the increase in the number of
voltage levels at the output requires additional switching
devices, which makes the design of MLI more complicated.
But prime advantage of using all the symmetric and
asymmetric structures in CHBI is to minimal the usage of
capacitors, which is one of the prominent features in deciding
the cost of the inverter. Contrarily a number of aforesaid
topologies use the bidirectional devices which pose a
disadvantage. The prime disadvantage of the asymmetric
topology is related to usage of additional bidirectional power
devices (IGBTs) which burdens the inverter in terms of
complexity and cost.
II. METHODOLOGY
The MLI topology CHBI addressed in [4] needs eight
devices along with two asymmetrical dc sources, to attain
seven levels concluded to a THD of 21.69%which is show in
the Fig.4.But the same is improvised to propose a customized
cascaded H-Bridge inverter through a reduced switch sufficient
to get the same output and THD. This reduction in the count of
switches minimizes the losses and better efficiency of the
equipment in their respective power handling system. A
proposal of modified topology with single-phase structure is
shown in Fig.2.
The basic idea of the switching topology is to isolate the
DC sources from the load by using the power electronics
switches. Here two asymmetric DC sources are connected in
series with the help IGBT’s such that lower potential terminal
of source V1 is connected to the higher potential terminal of
other DC source V2. And two isolated asymmetric DC voltages
are chosen in such that V2=2V1. [9],[10].
 State 4, V0(t)=V1+V2=3VDC
Fig.2.Proposed topology of modified cascaded H bridge inverter

State 5, V0(t)=0
State 1,V0(t) = 0

Stage 2, V0(t)=V1=VDC
Stage 6, V0(t)= -V1= -VDC

Stage 3 ,V0(t)=V2=2VDC
Stage 7, V0(t)= -V2= -2VDC

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 State 8, V0(t)= -V1-V2= -3VDC
Fig.3. Different states of the proposed seven level inverter (V1=VDC, Fig.4. MATLAB/ SIMULINK results of existing cascaded H-bridge
V2=2VDC) inverter model

According to above working stages of the circuit the

state switches and their particular voltages are shown below.
The proposed topology has seven level and all the levels of
voltages [6] are shown in Table-1 below[11],[12].

TABLE I: STATES OF SWITCHING

Sl.No. ON state switches Output voltage

1 S1,S2,S3/S1’,S2’,S3’ 0
2 S1,S2’,S3’ VDC
3 S3,S1’,S2’ 2VDC
4 S1,S3,S2’ 3VDC
5 S2,S3,S1’ -VDC
6 S1,S2,S3’ -2VDC
7 S2,S1’,S3’ -3VDC

The operation can be understood by the aid of their

switching states, shown in the Fig.3. The pairs of Switches (Sx, Fig.5 MATLAB/SIMULINK model of proposed model
Sx’) where {x=1, 2, 3} are complimentary triggered to each
other. Switching topology of switches S1, S2 and S3 are
designed to 8 operational states, and are illustrated in Fig.3.
Stage1 and stage 5 are the zero states and six non-zero states. It
is observed that three switches conduct simultaneously to
obtain a given level of voltage. In order to synthesize
VO(t)=3VDC, switches S1, S2’ and S3 are triggered and rest of
switches are commutated. Switch S2’ conducts continuously in
all the states for +ve half cycle, similarly switch S2 conducts
continuously in all the states for –ve half cycle. S2 and S2’ bears
highest voltage stress of 3VDC each.
III. SIMULATION RESULTS
The projected 7 level H-bridge Inverter simulation is
simulated in MATLAB/SIMULINK platform as shown in
fig.5. The spectrum of FFT of the output voltage without filter
is shown in fig. 6, and with filter is shown in fig.7. From the
results it is clear that, with the presence of the filter THD is
Fig.6. Output voltage and its THD of modified seven-level cascaded
improved when compared to without filter. H-bridge inverter without filter

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Fig.7.output voltage and its THD of modified seven level cascaded H
bridge inverter with LC filter
MATLAB/SIMULINK program is interfaced with the
hardware by using Arduino. The six triggering pulses shown in
Fig.8, are given to the IGBT’s by using RTI device, Arduino.
The first (S1) IGBT pulse is taken from the pin-4, second(S2)
pulse from pin-5, third(S3) pulse from pin-6, fourth(S1’) pulse
from pin-7, fifth(S2’) pulse from pin-8, and sixth pulse(S3’)
from the pin-9 in the Arduino. Such that all the triggering
pulses are given to the IGBT’s with the help of RTI device
(Arduino).
Fig.8.Arduino interfacing ports in the mat lab/SIMULINK
Fig.9. Block diagram of proposed seven level cascaded H bridge inverter
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IV. RESULTS OF EXPERIMENTATION
To authenticate the projected topology, a proto type of
single-phase 7-level inverter is developed on a Hardware
platform in the laboratory. An IGBT’s (FGA25N120ANTD)
are used as a switching device, with suitable gate drivers
(TLP250), shown in the Fig.10.Two batteries with
V1=2V,V2=4V were used as isolated DC sources. Two isolated
DC voltage sources are taken from the Regulated power supply
(RPS) one is set at 2V and another at 4V as show in the
Fig.13.MATLAB/simulink program code was loaded into the
Arduino(UNOR3) which was used to generate switching pulse
in the real time is shown in the Fig.8. Switching pulses for the
switches S1, S2, S3, S1’, S2’,S3’ are shown in Fig.11,Fig.12
respectively. It can observed that the switches S1,S1’ are
triggered at high frequency of switching, and the switches
S2,S2’ and also the rest of devices operate at the main switching
frequency of 50Hz., the switches S3,S3’ are operated at a
frequency in between the fundamental and carrier frequency.
The inverter was loaded with a 300Ω Rheostat. The output
voltage and the THD of the inverter without filter are shown in
the Fig.14 (a,b). Output load current of an inverter is 13.8 mA
(scale is in mV) as shown in Fig.15. An LC filter was designed
to eradicate the higher ordered harmonics, by that the output
will get near to the shape of sinusoid voltage. Inductor and
capacitor values were chosen using the formulae
Vdc 1
L= ; fc = (1)
4 f sw Δi pp 2π LC
The specifications for filter design are as follows:
DC voltages of 2V and 4V, switching frequency (fsw) of
individual switches is in the range of 50Hz to 850Hz, cutoff
frequency (fc) is approximately 50Hz, current ripple of 10%.
Using eq. (1) the filter elements are obtained as 18mH, 200µF
respectively. The voltage at the output and the THD of seven-
level-inverter with LC filter as revealed in Fig.16. Output
current of an inverter for a Resistive load with LC filter is
obtained as 11.9 mA ( scale is in mV) shown in the Fig.17.
Fig.10.Experimental setup
 Fig.14(b). Output voltage and its THD (without LC Filter)

Fig.11.Gate Triggering pulses to the IGBT’s(S1,S2,S3)

Fig.15.Output current of proposed inverter (without LC Filter)

Fig.12.Gate Triggering pulses to the IGBT’s (S1’, S2’,S3’)

Fig.13. Input DC voltages V1,V2

Fig.14(a). Output voltage (without LC Filter) Fig.16.Output voltage and its THD(with LC Filter)

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Fig.17. Output current of proposed inverter (with LC Filter)
V. CONCLUSION
A modified cascaded seven level H-bridge inverter was
fabricated which has the benefit of reduced THD, portability,
and cost has compared to normal cascaded H-bridge inverter.
Since the topology requires minimum switches, and low-cost
real time interfacing device (Arduino) compared DSP,
DSPACE, FPGA, etc., the overall expenditure for fabrication
reduces. This paper envisages the working of proposed
structure. An LC filter is introduced which helps in getting
nearer to sinusoidal waveform. The concepts which are
projected are verified through simulation and experimental
results. Satisfactory results are obtained and are tabulated in
Table 2.
TABLE 2. MATLAB/SIMULINK AND HARDWARE RESULTS
COMPARISON
Simulation Hardware
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Without LC With LC Without With LC

filter filter LC filter filter

RMS value 3.47V 3.87V 2.83V 1.60V

THD 21.69% 4.6% 27.7% 6.71%

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