This article has been accepted for publication in IEEE Transactions on Industry Applications.
This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TIA.2022.3191302
A Switched Capacitor-Based 13-Level Inverter with
Reduced Switch Count
Shirazul Islam, Marif Daula Siddique, Member, IEEE, Atif Iqbal, Senior Member, IEEE,
Saad Mekhilef, Fellow, IEEE, and Mohammed Al-Hitmi
Abstract- In this paper, a 13-level SC-MLI based single-phase
inverter is proposed in which desired levels of output ac voltage
are realized with reduced number of switch counts. The proposed
inverter requires 12 switches, three diodes, one input dc source
and three capacitors. The requirement of less number of switches
reduces the requirement of gate drivers which enhances power
density of converter. The second challenge in SC-MLI is to
maintain self-voltage balancing across the capacitors. The self-
voltage balancing capability becomes poor at low values of
modulation index. The capacitors connected in proposed SC-MLI
are capable to maintain the self-voltage balancing without
requiring auxiliary circuits or complex control strategies. The
operation of capacitors is self-balanced at all regions of
modulation index values. The comparison of the proposed SC-
MLI is carried out with state-of-art SC-MLIs discussed in the
literature using the parameters like PIV (Peak Inverse Voltage),
TSV (Total Standing Voltage) etc. The switches connected in the
proposed 13-level SC-MLI undergoes less voltage stress as
compared to the SC-MLI configurations discussed in the
literature. The proposed SC-MLI is highly competent to achieve
good power quality and is capable to ensure voltage balancing of
capacitors even at low values of modulation index. The validation
of the proposed inverter topology is carried out using a laboratory
prototype. The efficiency of the converter claimed using the
simulation results is observed to be 96.2% while the efficiency
evaluated using the experimental results is 94.1% at 500W.
Keywords: Multilevel inverter, boost capability, reduced switch
count, quadruple topology.
I. INTRODUCTION
Multilevel inverters are widely used for power conversion
from dc to ac required in renewable energy-based applications
like solar photovoltaic (PV) and fuel cells. The key advantages
offered by multilevel inverters (MLI) are reduced value of dv/dt
ratio, improved harmonic profile of output voltage, and ease of
high voltage operation with reduced voltage stress on switches.
The most commonly used MLIs are cascaded H-bridge (CHB),
flying capacitor (FC), and neutral point clamped (NPC). These
are conventional topologies used in MLI for dc to ac power
conversion. However, the separate dc sources required in CHB
based MLI, number of capacitors in FC based MLI and number
of diodes in NPC based MLI increase with the increase in the
number of levels of output voltage. Further, the FC and NPC
based MLI require external circuits to balance voltage across
the capacitors. This increases the cost of the system. The control
strategy required to balance of the voltage across these
capacitors becomes complex [1].
S Islam, A. Iqbal, and M. Al-Hitmi are with Department of Electrical
Engineering, Qatar University, Doha, Qatar.
M.D. Siddique is with Department of Electrical and Computer Engineering,
National University of Singapore, Singapore.
S. Mekhilef is with School of Science, Computing and Engineering
Technologies, Swinburne University of Technology, Victoria, Australia, and
also with Department of Electrical Engineering, College of Engineering,
Universiti Tenaga Nasional, Selangor, Malaysia
Corresponding author: Marif Daula Siddique (email: marif@nus.edu.sg)
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For renewable energy-based sources like solar PV,
boosting of voltage is required at the output of solar PV to
enable its use in high voltage applications and to reduce the
number of panels required to generate the specified voltage.
However, the gain of FC and NPC based MLI is unity. FC and
NPC based MLI do not provide any voltage boost action.
Therefore, a dc-dc boost converter connected at the output of
solar PV or transformer at the input of load is required.
However, this arrangement may increase the size and cost of
system. The control of the suggested system may become
difficult [2] - [4].
To overcome abovementioned limitations, switched
capacitor (SC) based MLI is considered as a good option.
Sufficient literature is reported recently which validates the
efficacy of the SC-MLI. Along with boost action for input
voltage, the efficiency of SC-MLI increases with an increase in
levels of the output voltage and voltage balancing becomes
simplified. In the case of SC-MLI, the capacitors are charged
by connecting it in parallel with a voltage source and discharged
by connecting in series with the load. This arrangement
provides boost action for the output voltage and increases the
number of levels in output voltage [5],[6]. However, the
objective is to maximize the voltage gain with fewer number of
capacitors. To fulfill these two objectives, single and double
stage SC-MLI are used which are sufficiently discussed in the
literature.
In case of two-stage SC-MLI, dc voltage is first stepped up
using switch switched capacitor circuit and H-bridge or its
generics is used to converter stepped dc into ac to supply power
to the load. Various two-stage SC-MLI are discussed in
literature. The two-stage SC-MLI topology is suggested in [5].
The suggested topology offers high redundancy. However,
switch count in the suggested topology is more and the voltage
gain is low. The modularity of the topology discussed in [6] is
high. However, the suggested topology requires switches
having high value of PIV. The topology suggested in [7] shows
a high value of CF. The topology reported in [8] requires
switches with low value of PIV and exhibits low value of TSV.
However, the suggested topology requires two capacitors to
produce a five level output voltage. The voltage gain is low.
The topology suggested in [9] shows less value of component
count and CF. However, the suggested topology requires
switches having high value of PIV and shows high TSV.
From above discussion, it is observed that use of two stage
SC-MLI in high voltage applications having switches with low
value of PIV is a serious concern. To overcome this limitation,
single stage SC-MLI are used. Various single-stage SC-MLI
topologies are discussed in literature. The topology discussed
in [10] requires switches having value of PIV equal to the
battery voltage. However, the gain of the suggested topology is
low. The topology suggested in [11] includes various H-
bridges. However, the switch count of the suggested topology
 This article has been accepted for publication in IEEE Transactions on Industry Applications. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TIA.2022.3191302

is high which leads to high value of CF. Further, the control of positive and negative levels of output voltage are shown in Fig.
capacitor voltage to maintain charge balance becomes complex. 2. The states of various switches included in the proposed 13-
In [12], discussed topology has high modularity and requires level inverter are shown in Table I.
switches with less value of PIV. However, the value of S5
S9
D2
component count for the suggested topology is more. In [13], S1
C1 C2
the switched capacitors are required for stepping up of dc
S8
voltage which leads to an increment in the voltage gain of the D1 S10
S3
converter. However, the switch count is more in the suggested
topology. The SC-MLI topology discussed in [14] offers high S2
S4 S7
modularity. However, a trade-off is observed between the Vdc
C3
modularity and switch count as well as PIV value of switches. S6 D3 S11
The topology discussed in [15] requires switches having low
value of PIV. However, the voltage gain of the converter is low LOAD
and switch count is more. Similar trend is observed in the - Vo +
topologies discussed in the [16] and [17]. Single-stage 13-level Fig. 1: Proposed 13 level topology of single-stage SC-MLI
SC-MLI topologies are discussed in [18] - [25].
The gain of converter discussed in [18] is moderate. The “TABLE I:
switch count of topology discussed in [18] is less. However, the SWITCHING STATES FOR THE PROPOSED 13 LEVEL TOPOLOGY
value of TSV evaluated is more. Further, the count of capacitor S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11
Vo
C1 C2 C3
increases with an increase in value of power factor of load. The (×Vdc)
SC-MLI configurations having high value of gain are discussed 0 1 1 0 1 0 1 0 1 0 0 3.0 D D D
0 1 1 0 1 0 1 0 0 1 0 2.5 D ─ D
in [19, 20, 22-25]. In case of the topology discussed in [19], the 0 1 0 1 1 0 1 0 1 0 0 2.0 C D D
component count is more while the topology discussed in [20] 0 1 0 1 1 0 1 0 0 1 0 1.5 C ─ D
requires switches having high value of PIV. The converter 0 1 0 1 1 1 0 0 1 0 0 1.0 C C C
suggested in [25] has highest switch count. The SC-MLIs 1 0 0 1 1 0 1 0 0 1 0 0.5 C ─ D
suggested in [24], [22] and [23] require a capacitor of high 1 0 0 1 1 1 0 0 1 0 0 zero C C C
voltage rating which increases the cost of the converter. 0 1 0 1 1 1 0 0 0 0 1
Further, the charge balance across the capacitors deteriorates at 0 1 0 1 0 1 0 1 0 1 0 -0.5 C D ─
low value of modulation index in case of [19] and [20]. The 1 0 0 1 1 1 0 0 0 0 1 -1 C C C
topology having high value of voltage gain and low value of 1 0 0 1 0 1 0 1 0 1 0 -1.5 C D ─
component count is discussed in [24]. The suggested topology 1 0 0 1 0 1 0 1 0 0 1 -2 C D D
shows low value of CF. However, the suggested topology 1 0 1 0 0 1 0 1 0 1 0 -2.5 D D ─
1 0 1 0 0 1 0 1 0 0 1 -3 D D D
requires switches having high value of PIV and shows high
TSV. Also, the voltage balancing capability of the suggested “Notations: 0 = OFF state of the switch, 1 = ON state of the switch, ─ = no
topology deteriorates at low value of modulation index. The change in capacitor voltage, C/D = charging and discharging of capacitor”
voltage gain of three is achieved in case of SC-MLI topology
B. Self-voltage balancing of capacitors C1, C2 and C3
suggested in [21]. However, the switch count is more in case of
the suggested topology. The current and voltage sensors are not included in case of
To address above mentioned limitations, a 13-level SC-MLI SC-MLIs. Therefore, switched capacitor based topologies
converter topology is proposed in this paper which has high suffers from the limitations of charge balancing across
value of gain, less switch count and requires switches with less capacitors. To resolve this issue, the charge balancing in the
value of PIV. The voltage balance across the capacitors is proposed topology is achieved using series-parallel connection
maintained even at low value of modulation index. The of capacitors, C1, C2 and C3. The capacitor, C1 is connected in
proposed topology is suitable for high voltage applications. parallel with the source during the voltage levels, 0Vdc,
Using the experimental prototype, the proposed topology's ±0.5Vdc, ±1.0Vdc, ±1.5Vdc and ±2.0Vdc. This indicates that the
performance has been tested. The suggested topology is maximum voltage for which C1 can be charged is Vdc. The
compared to various SC-based MLIs in the literature in terms capacitors, C2 and C3 are charged in series by the voltage source
of switching devices, passive elements, and other performance during the voltage levels, 0Vdc and ±1Vdc. This indicates that
metrics. the maximum voltage for which C2 and C3 can be charged is 0.5
II. PROPOSED TOPOLOGY Vdc. The Fig. 3 shows the charging and discharging pattern of
capacitor C1, C2 and C3. From the switching Table I and
A. Description of the proposed 13-level MLI switching states shown in Figs.2-3, a symmetry is observed in
Fig. 1 shows the circuit diagram of the proposed topology charging and discharging patterns of capacitors C1, C2 and C3.
of 13-level inverter. The proposed topology is able to generate This ensures the charge balance across the capacitors connected
the 13-level output voltage which furnishes a voltage gain of 3. in the proposed 13-level SC-MLI. From the switching pattern
The triple gain in voltage is achieved with the help of three shown in Figs. 2 various redundant stages are possible with
capacitors, C1, C2 and C3. The voltage gain of C1 is Vdc, while voltage level ±2.0Vdc. This ensures the balancing in capacitor
the voltage gain of C2 and C3 is 0.5Vdc each. Here, Vdc is the voltage during the transient condition like step variation in
voltage of input dc source connected at the input of MLI. The loads and fault inception.
circuit diagrams to show the direction of current flow during

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S5 S5 S5
D2 S9 D2 S9 D2 S9
S1 S1 S1
C1 C2 C1 C2 C1 C2

D1 S8 S10 D1 S8 S10 D1 S8 S10

S3 S3 S3

S4 S7 S4 S7 S4 S7
S2 S2 S2
Vdc Vdc Vdc
C3 C3 C3
S6 D3 S6 D3 S6 D3
S11 S11 S11

- + - +
LOAD + - LOAD LOAD
Vo = 0 Vo = 0.5Vdc Vo = Vdc
S5 S5 S5
D2 S9 D2 S9 S9
S1 S1 D2
S1
C1 C2 C1 C2 C1 C2
D1 S8 S10 D1 S8 S10 D1 S8 S10
S3 S3 S3
S4 S7 S4 S7 S4 S7
S2 S2 S2
Vdc Vdc Vdc
C3 C3 C3
S6 D3 S6 D3 S6
S11 S11 D3 S11

- + - + - +
LOAD LOAD LOAD
Vo = 1.5Vdc Vo = 2Vdc Vo = 2.5Vdc
S5 S5 S5
D2 S9 D2 S9 D2 S9
S1 S1 S1
C1 C2 C1 C2 C1 C2
D1 S8 S10 D1 S8 S10 D1 S8 S10
S3 S3 S3
S4 S7 S4 S7 S4 S7
S2 S2 S2
Vdc Vdc Vdc
C3 C3 C3
S6 D3 S6 D3 S6 D3
S11 S11 S11

- LOAD + - + - +
LOAD LOAD
Vo = 3Vdc Vo = 0 Vo = -0.5Vdc
S5 S5 S5
D2 S9 D2 S9 D2 S9
S1 S1 S1
C1 C2 C1 C2 C1 C2
D1 S8 S10 D1 S8 S10 D1 S8 S10
S3 S3 S3
S4 S7 S4 S7 S4 S7
S2 S2 S2
Vdc Vdc Vdc
C3 C3 C3
S6 D3 S6 D3 S6 D3
S11 S11 S11

- + - + - +
LOAD LOAD LOAD
Vo = -Vdc Vo = -1.5Vdc Vo = -2Vdc
S5 S5
D2 S9 D2 S9
S1 S1
C1 C2 C1 C2
D1 S8 S10 D1 S8 S10
S3 S3
S4 S7 S4 S7
S2 S2
Vdc Vdc
C3 C3
S6 D3 S6 D3
S11 S11

- + - +
LOAD LOAD
Vo = -2.5Vdc Vo = -3Vdc
Fig. 2: Various states of proposed single-stage SC-MLI topology used to generate 13-level of output voltage.

C. Evaluation of values of capacitors, C1, C2 and C3 the principle of charge balance, the value of capacitor, C1 is
given by
The values of C1, C2 and C3 are evaluated using the
values of voltage ripples present in the average value of voltage Io
C1 = (1)
across these capacitors. While evaluating the values of C1, C2 2π f o ∆ Vc1
and C3, it is assumed that the values of time constant of the where, Io is peak value of load current and fo is the frequency of
charging path due to parasitic components is relatively smaller output voltage. Now, as observed from switching Table I and
than the time constant of each voltage level. This ensures quick and switching states shown in Figs.2-3, the charging and
charging of these capacitors. During the discharge period, the discharging patterns of capacitors, C2 and C3 are similar.
voltage across the capacitors decreases. As shown in Fig. 3, the Therefore, the values of C2 and C3 are given by
values of voltage across the capacitor C1 undergo a variation of
Io
ΔVc1 during the discharge time interval t5 to t’6. There is C 2 = C3 = (2)
similarity in discharge pattern of capacitor C1 during the 2π f o ∆Vc
positive and negative half cycle of output voltage. Now using

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where, ΔVc is the magnitude of ripple voltage of capacitors C2 A1

A2
A1
A2
A2
A4
A5 S7
and C3. B3
B4 S1
A3
A4 A6
B5 A5 A7
S4
B6 B1
C. Modulation Technique B7 B2
B3
B2
B4
B4 B5 S8
B5 B6
To generate the switching pattern for the proposed 13-level A1
B7

SC-MLI, the sinusoidal pulse width modulation technique is A3

A4
A2
A3
A1
A3 S9
A4
used. In the proposed MLI, a sinusoidal reference wave having A5
A6 S2 A5 S5 A5
A7
A7 A6
peak magnitude of unity and 12 level-shifted carriers equally B1
B2
A7
B1 A2
B3 A4
distributed between levels 6.0 and -6.0 as shown in Fig. 4 are A1 A6
B2
S10
A3
used. The modulation scheme for generating the switching B1
B4
B6
B2
pattern is shown in Fig. 5. In this scheme, the frequency of level A6
A7
B3
B4
S6
B1
S3 B5 B3 S11
shifted carrier signal is 10 kHz and the frequency of modulating B6
B7
B6
B7
B5
B7
signal is 50 Hz. Now gate signals for generating desired states
as depicted in Fig. 2 are achieved. Finally, the gate signals are Fig. 6: Generation of gating pulses to switches using OR logic
added to generate the gating signals for various switches III. POWER LOSS ANALYSIS
connected in the proposed 13-level SC-MLI as shown in Fig. 6. In this section, the analysis for evaluation of power losses
occurring in the proposed 13-level inverter is included. As
3.0Vdc discussed in the literature, the total power losses occurring in
2.5Vdc semiconductor switches are given by,
2.0Vdc
1.5Vdc Vo Plosses = Psw + Pc + Pripple (3)
1.0Vdc charging
0.5Vdc discharging In the above expression, Psw, Pc and Pripple are designated as
0 t switching, conduction and ripples losses, respectively. The
t1 t2 t3 t4 t5 t6 t'6 t'5 t'4 t'3 t'2 t'1T/2
algebraic sum of switching and conduction losses (Psw+Pc)
VC1 t represents the losses taking place in the power semiconductor
VC2 t switch while the losses, Pripple represents the losses taking place
No effect
VC3 t
due to effect of ripple in capacitor voltage.
A. Switching Losses (Psw)
Fig. 3: Output voltage of proposed 13-level SC-MLI along with charging and The switching losses are the losses that represent power
discharging pattern of capacitors. dissipation during turn-on and turn-off process of the power
semiconductor switch. These losses are evaluated by
6 Vcr1 integrating product of the voltage and current during the
5 Vcr2
Vcr3 switching period. Switching losses include the losses occurring
4
3 Vcr4 during ON-state and OFF-state of switch. The switching losses,
2 Vcr5 Psw occurring in the SC-MLI topology are given by,
1 Vcr6
0 t Von I onTon Voff I off Toff
-1 Psw =   ( + ) (4)
-2 all switcheswihin1lf o 6 6
-3
-4 where, Von is the voltage across the switch, Ion is the current
-5 through the switch and Ton is the time duration during ON-state
-6 of switch while, Voff is the voltage across the switch, Ioff is the
Fig.4: Reference and carrier waveforms to modulate the proposed inverter. current through the switch and Toff is the time duration during
OFF-state of switch.
==7
Vcar1 > x +
A7
B. Conduction Losses (Pc)
==6 A6
Vcar2 > x + The conduction losses in a power semiconductor switch are
> ==5 A5
Vcar3 x + the losses occurring during ON-state of the switch at steady-
> ==4 A4
Vcar4 x + state. The conduction losses, Pc occurring in a switch are
> ==3 A3
Vcar5 x +
> ==2 A2
calculated using the expression given by
Vcar6 x +
≥ ==1 A1

Vref
<
> x +
==-1 B1
Pc = 
allswitches
I 2 o , switch Ron (5)
Vcar7 ==-2 B2
Vcar8 > x + where, Io, switch is the current flowing through the power device
==-3 B3
> x +
Vcar9 ==-4 B4 and Ron is its internal resistance of the switch in an ON-state.
> x +
Vcar10
x
==-5 B5 C. Ripple Losses (Pripple)
Vcar11 > +
> x +
==-6 B6 The capacitor possesses a non-zero value of internal resistance
Vcar12 ==-7 B7
which is termed as equivalent series resistance (ESR) of the
capacitor. This ESR is mainly responsible for non-zero value of
Fig. 5: Switching scheme of the proposed 13-level inverter.
losses occurring in the capacitor at steady-state. Due to this
ESR, a voltage drop Δvc appears in the output voltage waveform
of SC-MLI which is responsible for ripple power losses, Pripple

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in a capacitor. The ripple losses, Pripple occurring in a capacitor manufacturer. Using these values, the thermal capacitance, Cj-c
is given by, of R-C network is evaluated using,
1 τ (7)
Pripple = f swC ∆vc 2 (6) C j −c = i
2 R j −c
The software, PLECS provides the facility of thermal modeling The value of thermal resistances, Rc-h is specified in the data
of power semiconductor devices. Using thermal model of the sheet of paste material. The junction temperature, Tj due to
devices included in the SC-MLI, the power losses occurring in power loss, Ph is given by
t t
the converter at steady-state can be evaluated. The efficiency ∞ − −
T j = Ta + Ph { R j −c (1 − e
R j −c C j −c
) + Rc − h + Rh− a (1 − e Rh− aCh−a
)} (8)
curve of the proposed 13-level SC-MLI is included in Fig. 7.
n =1
This figure shows the variation in efficiency of proposed
where, Ta is the ambient temperature. Also, when the system
converter with respect to output power drawn from the
reaches at steady state, the effect of exponential terms becomes
converter. From this figure, it is observed that for a level of
negligible. As given in (3), Ph are the losses operating
output power of 100-500W, the converter efficiency is more
temperature. To accurately model these losses, simulation
than 97% and its value is 96.2% for the converter output of 1
approach using PLECS is used [27]. For this purpose, the IGBT
kW.
switch, G60N100 IGBT [28] along with its antiparallel diode is
98
used for analysis. The ambient temperature of the switch is
Efficiency (%)

96
94
considered to be 25oC. The switches, S4, S5 and S6 are used to
92 supply charging current. Therefore, these switches are
90 considered for thermal analysis. Fig. 10(a) and 10(b) shows the
88 junction temperature of the switches, S4, S5 and S6 at rated
86 power of 500 W and 1 kW of the proposed 13-level SC-MLI.
100 200 300 400 500 1000 1500 2000 2500
Output Power (W) IGBT Module Z(j-c) : thermal resistance
TSj from junction to case
Fig. 7: Variation in efficiency with respect to variation in output power TDj
IGBT Diode
supplied by proposed converter topology. Switch R(c-h) : thermal resistance
PSh ZS(j-c) ZD(j-c) PDh from case to heat sink

Z(h-c) : thermal resistance

Ta TSc TDc Ta from heat sink to ambient
Thermal
Paste RS(c-h) RD(c-h) Tj : Junction temperature

Th Tc : Case temperature

Heat Sink Th : Heat sink temperature

ZSD(h-a)
Ta : Ambient temperature

Ta
(a)
R(j-c)1 R(j-c)2 R(j-c)3 R(j-c)4 R(h-a)
R(c-h)
Tj
Tc Th
C(j-c)1 C(j-c)2 C(j-c)3 C(j-c)4 C(h-a)
Ph
Four layer RC Foster Network
Fig. 8: Distribution of power losses
Ta Ta
The analysis for the distribution of losses on various elements (b)
of the proposed MLI is carried out. The parameters of the Fig. 9: (a) Thermal models of the IGBT switch and diode used to calculate
junction temperature, Tj. (b) Electrical equivalent of thermal model of the IGBT
proposed 13-level SC-MLI are specified in table I and the losses switch and diode [27].
occurring in various elements like switches, diodes and S4 S4
40 40
capacitors of the proposed MLI are evaluated. The distribution
Tj (oC)

Tj (oC)

of losses on various switches, diodes and capacitors is for the 30 30

proposed MLI is shown in Fig. 8. From this figure, it is 20 20

S5 S5
observed that the losses occurring in components in the 40 40

charging loop are higher as compared to other switches.

Tj (oC)

Tj (oC)

30 30

D. Thermal Analysis of Converter

20 20
To carry out the thermal analysis of the switches, the electro- 40
S6
40
S6

thermal model of semiconductor devices like IGBT used in

Tj (oC)

Tj (oC)

30 30
charging loop of proposed 13-level SC-MLI is used. The
thermal model of IGBT switch and diode is discussed in [26]. 20
4.5 4.6 4.7 4.8 4.9 5.0
20
4.5 4.6 4.7 4.8 4.9 5.0
Time (s) Time (s)
The thermal model of a single IGBT switch and diode is shown Fig. 10: Estimated junction temperature, Tj of G60N100 IGBT for output
in Fig. 9(a). The thermal impedance, Z(j-c) is modeled as a four- power of (a) 500 W. (b) 1 KW supplied by 13-level SC-MLI.
layer Foster thermal resistor-capacitor, (R-C) network as shown
E. Design of Elements of Proposed SC-MLI
in Fig. 9(b). Thermal parameters of R-C network like thermal
In this subsection, the design method for selection of passive
resistance, Rj-c and thermal time constant, ꞇi of each stage are
components like capacitors and active components like
specified in the data sheet of device provided by the

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switches and diodes is discussed.
i. Selection of Capacitors
Using (1), the value of capacitance C1 is selected. In (1), fo is
the operating frequency of SC-MLI, Io is the load current and
∆Vc1 is the magnitude of ripple voltage. The 13-level SC-MLI
is designed for power rating of Po = 1 kW. The peak value of
load voltage is Vo=300V (peak). The value of Io is 4.71 A. The
frequency of output voltage of SC-MLI is 50 Hz. The voltage
stress appearing across the capacitor, C1 is Vdc =100 V. As
discussed in the literature, the maximum permissible value of
∆Vc1 is 10% of Vdc. Using these values, value of C1 is
Io 4.71 (9)
C1 > = = 1500µ F
2π f o ∆Vc1 2π × 50 × 10 × 100
100
To satisfy above constraint, the value of C1=2200uF (ESR, rc1
=87.9 mΩ) and of voltage rating 450V is selected as the desired
value of C1. Using (2), the values of C2 and C3 are
Io 4.71 (10)
C2 = C3 > = = 3000 µ F
2π f o ∆Vc 2 2π × 50 × 10 × 50
100
To satisfy above constraint, the values of C2=C3=3300uF (ESR,
rc2 = rc3 = 65.3 mΩ) and voltage rating 450V each are selected
as the desired values of C2 and C3.
ii. Selection of Semiconductor Switches and Diodes
The maximum value of voltage stresses appearing across the
switches, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, and S11 are given
by,
vs1 |stress , vs 2 |stress , vs 3 |stress , vs 4 |stress , vs 5 |stress , vs 6 |stress ,
(11)
vs 7 |stress , vs 8 |stress , vs 9 |stress , vs10 |stress , vs11 |stress = Vdc
The value of switch currents must be chosen more than the
maximum value of source current, ib. For a typical power rating,
Po= 1 kW and source voltage, vb = 100 V of the proposed MLI,
the maximum value of source current, ib supplied by the source
is 10A. To fulfill these requirements, the G60N100 IGBT is
selected as the desired switching device. The value of PIV
(Peak Inverse Voltage) appearing across the freewheeling
diodes, D1, D2, D3 and D4 are given by,
vD1 |PIV = vD 2 |PIV = vD 3 |PIV = Vdc (12)
The current ratings of freewheeling diodes D1, D2, D3 and D4
must be greater than the source currents, ib respectively.
Therefore, to satisfy the PIV and current constraints, Schottky
diode STTH30R04W (400V/30A, Vf = 0.97 V and rD = 19.8
mΩ) is selected as the desired diode for the proposed MLI.
iii. Selection of Optimal Value of Capacitor
Resistive Load: The procedure for selection of the optimal
value of capacitance for SC-MLI with R-L load is discussed in
11(a). From this figure, it can be observed that for a given value
of ∆Vc, the magnitude of the load resistance, RL increases, the
optimal value of the capacitance Copt decreases.
Resistive and Inductive Load: The procedure for selection of
the optimal value of capacitance for SC-MLI with R-L load is
discussed in [25]. For R-L load, the optimal value of
capacitance required for MLI is
Io (14)
Copt ≥ [Cos(0.8481 − φ ) − Sin φ ]
2π f o ∆Vc1Vdc
where, ϕ is the angle by which the load current lags the
fundamental load voltage, Io is the load current, Vdc is the
nominal value of dc voltage of source. The 13-level SC-MLI
is designed for power rating of Po = 1 kW. The peak value of
load voltage is Vo =300V for Vdc =100V. The rms value of Io is
4.71 A. The variation in optimal value of capacitor, Copt is
carried out with respect to variation in phase angle ϕ, of the
proposed SC-MLI for different values of ∆Vc shown in Fig.
11(b). From this figure, it can be observed that for given value
of ∆Vc, optimal value of capacitance, Copt decreases with
increase in the value of phase angle, ϕ for R-L load connected
across the SC-MLI.
Fig. 11: Selection of the optimal value of Capacitor for (a) Resistive load and
(b) R-L load.
F. Harmonic Analysis of the Proposed SC-MLI
To observe the Total Harmonic Distortion Performance of the
proposed 13-Level SC-MLI converter with a voltage gain of 3
is simulated in PLECS. The value of dc input voltage is 100 V.
The switching frequency of the converter is 5 kHz. The load
connected at the output of the proposed converter is 1 kW. The
value of R-L load connected at the output of the proposed
converter is RL = 45Ω, L = 10 mH. The values of capacitors are
C1= 2200µF and C2 = C3= 3300µF. The Fig. 12(a) shows the
Waveforms of output voltage and load current supplied by the
proposed 13-level SC-MLI. The Fig. 12(b) shows harmonic
spectrum of output voltage and load current supplied by the
proposed 13-level SC-MLI. The THD in case of source voltage
is observed to be 9.66% while in case of load current its value
is 2.7%.
400
Load Voltage (V)

300
Fourier: Load Voltage (V)

[25]. The optimal value of capacitor for a given MLI is 200

200
Voltage (V)

8 (13) 0
Copt = 100

2π f o ∆Vc RL -200 0

where, RL is the load resistance and ∆Vc1 is the magnitude of the -400 -100
Load Current Fourier: Load Current
ripple voltage. From (13), it can be observed that the optimal of 10 8

6
C for a given a given resistive load is inversely proportional to 5
Current (A)

4
the load resistance (RL) and magnitude of ripple voltage (∆Vc) 0
2

of the capacitor. The increment in the value of the RL or ∆Vc -5 0

will lead to decrement in the optimal value of the capacitor. To -10

-2
0 200 400 600 800 1000
0.00 0.02 0.04 0.06 0.08
capture this, variation in optimal value of capacitor, Copt is Fig. 12: Waveform of (a) output voltage and load current of the proposed 13-
Frequency

carried out with respect to variation in load resistance, RL of the level SC-MLI. (B) Harmonic spectrum of output voltage and load current
proposed SC-MLI for different values of ∆Vc shown in Fig. supplied by the proposed 13-level SC-MLI.

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IV. COMPARATIVE ASSESSMENT The topology suggested in [18] requires two capacitors each of
voltage rating equal to Vdc. The SC-MLI configurations
The SC-MLI are preferred as compared to FC and DC based
discussed in [19, 22, 23] require three capacitors out of which
MLI due to gain more than unity offered by it. Therefore,
two capacitors are of voltage rating of Vdc and one of 3Vdc. A
various types of single and two-stage based SC-MLI are
capacitor of higher rating results in the higher cost, losses, and
discussed in this paper. However, due to additional advantages
complexity to control their charging/discharging. The SC-MLI
offered by single-stage as compared to double-stage SC-MLI,
suggested in [24] requires four capacitors out of which two
the single-stage based SC-MLI are compared in this section
capacitors are of voltage rating, Vdc and two of 3Vdc. The SC-
[10-21]. The various parameters used for performance
MLI suggested in [25] requires three capacitors each of voltage
assessment of SC-MLI are NL= Number of levels, NIS= number
rating of Vdc. The proposed SC-MLI topology requires three
of input dc sources, Nsw = Number of switches, Nd = number of
capacitors. The voltage rating of capacitor C1 is Vdc whereas the
diodes in parallel with switches, Nad= number of auxiliary
voltage rating of capacitors, C2 and C3 are 0.5 Vdc each, which
diodes, Ngd= number of gate driver circuit, Nc = number of
is same as the ratings of capacitors required in [21].
capacitor, VRC = voltage rating of capacitors, TSVpu=Total
In Table II, the efficiencies of the SC-MLI reported in reported
standing voltage in per unit.
in [10-25] are listed. From this table, it is observed that the
The comparison of single-stage SC-MLI based topologies is
proposed 13-level SC-MLI and the 13-level SC-MLI suggested
listed in table II. From this table, it is observed that the gain of
in [18, 21-24] offer high efficiency which is more than 95%.
proposed topology is 3 which is same as that of the topology
The efficiency of the 13 level SC-MLI reported in [22] is the
proposed in [21]. The proposed topology uses only 12 switches
highest as compared to 13-level SC-MLI configurations
and generates 13-level output ac output voltage. In contrast to
suggested in [18, 21, 23, 24] and the proposed converter.
the topologies discussed in [19], [20] and [21], requires less
However, the proposed SC-MLI offers high efficiency at low
number of controlled switches to generate 13-level output
load conditions. From Fig.7, it can be observed that the
voltage. The values of PIV and TSV of switches and diodes are
efficiency of the proposed converter at a load of 500 W is more
higher in case of [19] and [20] are higher as compared to the
than 97%. The efficiency of the proposed converter at load of 1
topology discussed in [21]. However, the
kW is 96.2%. This comparison validates the viability of the
proposed topology makes it possible to achieve the same
proposed 13-level SC-MLI.
number of levels of output ac voltage with switches having a
The power density of SC-MLI is characterized by the reduced
reduced value of PIV and TSV.
size of elements and ability to supply more power. In this paper,
The voltage gain of the 13-level SC-MLI configurations
specifically two parameters are used to specify the power
discussed in [19, 22-25] is 6 while the voltage gain of the SC-
density of a given configuration of SC-MLI which are Total
MLI discussed in [18] is 4. The MLI suggested in [21] and the
Harmonic Distortion (THD) and reduced number of gate
the proposed SC-MLI has a voltage gain of 3.
drivers. Less THD in the output voltage of SC-MLI reduces the

TABLE II:
COMPARISON TABLE FOR DIFFERENT SC-BASED TOPOLOGIES WITH PROPOSED TOPOLOGY

VRC ɳ fs
Reference NL G NIS NSw Nd Nad Ngd Nc PIV TSV(p.u.)
0.5Vdc Vdc 2Vdc 3Vdc (%) (kHz) D
[10] 5 2 1 9 9 0 9 1 1 9 0 0 1 0 97.91 2.5 L
[11] 7 3 1 16 16 0 14 2 2 16 0 3 0 0 90.2 1.667 L
[12] 5 4 1 9 9 1 8 1 1 9 0 4 0 0 91.7 1 L
[13] 5 4 1 12 12 0 12 4 1 20 0 2 2 0 88 15 L
[14] 5 2 1 7 7 3 7 2 2 9 0 2 0 0 91.1 3 M
[15] 9 2 1 12 12 0 11 2 1 11 2 0 0 0 80.61 1 L
[16] 9 2 1 11 11 0 10 2 1 10 2 0 0 0 93.2 2.5 M
[17] 9 2 1 12 12 0 12 2 2 22 2 0 0 0 95.24 0.1 L
[18] 13 4 1 14 14 1 14 3 3 28 0 2 0 0 96.7 2.5 L
[19] 13 6 1 13 13 2 13 3 3 33 0 2 0 1 94.5 4.8 M
[20] 9 6 1 11 11 0 10 2 1 10 0 2 0 1 94.18 2.5 H
[21] 13 3 1 13 13 1 12 3 2 17 2 1 0 0 96.53 2.1 M
[22] 13 6 1 13 13 2 13 3 1 32 0 2 0 1 97.3 5 M
[23] 13 6 1 13 13 2 13 3 3 33 0 2 0 1 95.9 5 L
[24] 13 6 1 10 10 4 10 4 3 33 0 2 0 2 95.5 5 H
[25] 13 6 1 15 15 0 15 3 30 3 0 3 0 0 94 5 M
[P] 13 3 1 12 12 3 11 3 2 12 2 1 0 0 96.2 5 M
NL= Number of levels, G= voltage boost ratio, NIS= number of input dc sources, Nsw = Number of switches, Nd=number of diodes in parallel with switches,
Nad= number of auxiliary diodes, Ngd= number of gate driver circuit, Nc = number of capacitor, TSVpu=Total standing voltage in per unit, PIV = Peak inverse
voltage in per unit, VRC = voltage rating of capacitors, ɳ =Efficiency, fs = Switching Frequency, D= Power Density, L=Low, M= medium, H= High.

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size of filter elements and use of less number of gate drivers

reduces the size of the MLI significantly. From this table I, it is
observed that the proposed 13-level SC-MLI and the 13-level
SC-MLI suggested in [18-19, 21-25], the power density of the
SC-MLI suggested in [22] has the highest power density. The
THD of the output voltage is lower than 1% and the number of
gate drivers is lowest. In the proposed topology, the number of
drivers are 11 which is lowest than rest of the 13-level SC-MLI
suggested in [18-19, 21, 23-25]. Additionally, the THD in the
output voltage of the proposed converter is 9.66% which
imposes the requirement of reduced values of filter elements.
Therefore, the power density of the proposed converter is
higher than the converters suggested in [9-10, 21, 23-25].
The switching frequencies of the SC-MLI suggested in [10-25]
are listed in Table I. From this table, it is observed that the
switching frequency of the converter suggested in [13] is the
highest while the switching frequency of the converter
suggested in [17] is the lowest equal to 0.1 kHz. The proposed
13-level SC-MLI is operated at a switching frequency of 5 kHz.
V. RESULTS AND DISCUSSION
The efficacy of the proposed 13-level SC-MLI is validated with
the help of the laboratory prototype shown in Fig. 13. The
power rating of the converter is 1kW. The load connected at the
output terminals of converter is R-L load. A PCB-designed
circuit with discrete components such as switches, capacitors,
diodes, and the like is executed in the laboratory to verify the
effectiveness of the suggested multilevel inverter. Tests have
been conducted on the suggested topology with 1kW rating.
The parameters of proposed converter are listed in Table III.
The results are captured for the modulation index, m =1.0.
200 V/Div
vo
5 A/Div
io
20 V/Div
vc2
20 V/Div
vc3
Time (10 ms/Div)
Fig. 14: Experimental results of a proposed 13-level inverter. Waveforms
of source voltage, load current, capacitor voltages, Vc2 and Vc3
of voltages across the capacitors, C2 and C3. This shows that the
capacitor voltages are balanced.
The transient performance of the proposed 13-level inverter
is observed in Fig. 15. Fig. 15 (a) shows the waveforms of
inverter output voltage, load current, capacitor voltages during
step variation in load demand from no-load condition to 500 W
to 850 W. This is carried by connecting two resistive loads of
80Ω in parallel with the series combination of 100mH inductor.
Fig. 15 (b) shows the waveforms of inverter output voltage,
load current, capacitor voltages for resistive load from no-load
to 80Ω to 40Ω. From these waveforms of Fig. 15 (b), it is
observed that that load voltage and load current are in phase for
resistive load while a phase difference is observed for the
inductive load as illustrated in Fig. 15 (a). The effect of
variation in the modulation index of the proposed 13-level
converter on its performance is observed in Fig. 15 (c). Fig. 15
(c) shows the waveforms of inverter output voltage, load
current, capacitor voltages for the values of m = 1.0, 0.66, and
0.80. From these waveforms, it is observed that the various
levels present in the output voltage waveform goes on
decreasing with decrease in the value of modulation index.

200 V/Div

vo

Fig. 13: Laboratory prototype of the 13-level SC-MLI

5 A/Div
TABLE III: io
EXPERIMENTAL PARAMETER DETAILS 20 V/Div
vc2
Switches G60N100 IGBT 20 V/Div
vc3
Capacitor, C1 PG6DI (450V and 2200µF)
Time (10 ms/Div)
Capacitor, C2, C3 PG6DI (450V and 3300µF)
(a)
Controller FPGA Vertix-5 (XC5VLX50T)
Gate Driver GDA-2A4S1
dc power supply TDK Lambda GEN300-11
Resistive + Inductive loads Two sets of 80Ω -100mH 200 V/Div
Input Voltage 100V
Switching / Fundamental Frequency 5kHz / 50Hz vo

From the waveforms shown in Fig. 14, it is observed that 5 A/Div

io
the output voltage of proposed SC-MLI includes 13-levels. The 20 V/Div
rms value of load current is 3.53 A for a load demand of 500 W vc2
20 V/Div vc3
with a load of 80Ω +100mH. Fig. 8 also shows the waveforms
Time (10 ms/Div)
(b)

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98

Efficiency (%)
97
96
200 V/Div
95
vo 94
5 A/Div
93
100 200 300 400 500
io Output Power (W)
20 V/Div Fig, 17: Experimental Efficiency curve of the proposed 13 level topology
vc2
20 V/Div vc3
Time (10 ms/Div) VI. APPLICATIONS OF PROPOSED 13-LEVEL SC-MLI
(c)
Fig. 15: Experimental results of a proposed 13-level inverter with change in The proposed SC-MLI is able to generate the single-
(a) RL load, (b) R load, and (c) modulation index. phase 13-level ac output with voltage gain of 3. The proposed
topology requires less switch count and voltage stress across
Further, the operation of the proposed 13 level topology has these is less as compared to the SC-MLI suggested in literature.
been validated for change of load type. This load change has Further, the proposed converters is capable of maintaining self-
been depicted in Fig. 16(a). The effect of variation in the output voltage balancing and this features does not deteriorate even at
frequency on the performance of the converter is shown in Fig. low value of modulation index. These features render the
16(b). Fig. 16(a) shows the waveforms of inverter output application of proposed SC-MLI to be used in applications like
voltage, load current, capacitor voltages for the change of solar PV, fuel cell, battery power applications, industrial drives,
output frequency the values of fs varied from 100 Hz to 25Hz. etc., as shown in Fig. 18. The proposed SC-MLI can also be
From these waveforms, it is observed that the performance of used in applications like microgrid used to provide facility for
the converter remains intact even for variation in the output remote electrification.
frequency. From the waveforms shown in Fig. 14 -16, it can be
inferred that the proposed single-stage 13-level SC-MLI is
AC Bus
showing good performance for variation in load demand, Main
grid
modulation, index switching frequency, and various types of
loads. AC
Load
Solar PV Proposed 13-
level SC-MLI
AC/DC DC
Load

Battery Fuel Cell

Storage AC/DC Electric
vehicle
200 V/Div
vo Fig. 18: block diagram of proposed SC-MLI used to interface various sources
and loads
5 A/Div io
20 V/Div VII. CONCLUSION
vc2
20 V/Div vc3 In this paper, a 13-level SC-MLI inverter topology is
Time (10 ms/Div) proposed which includes 12 switches of low value of PIV, three
(a)
diodes and three capacitors. The proposed topology offers a
200 V/Div voltage gain of three. The converter is able to maintain the
balancing in capacitor voltages during positive and negative
vo half cycles of output voltage. The performance assessment of
the proposed converter is carried out using PIV, TSV,
5 A/Div efficiency etc. The comparison of listed values of these
parameters for the proposed and reported topologies reflects
io
that the proposed converter topology requires less switches of
20 V/Div reduced PIV rating. To validate the efficacy of the converter
20 V/Div vc2
vc3 during the variation of various operating conditions like
variation in modulation index, switching frequency and step
Time (50 ms/Div) variation in load demand, experimental results were captured
(b) on a laboratory prototype and included.
Fig. 16: Experimental results of a proposed 13-level inverter with a change in
a (a) load type and (b) frequency
ACKNOWLEDGMENT
The efficiency of the converter was evaluated using the This work is supported by the Universiti Tenaga Nasional grant
experimental set up upto a load of 500W and is shown I Fig. 17. no. IC6-BOLDREFRESH2025 (HCR) under the BOLD2025
At an output power of 500W, the efficiency of the proposed Program.
converter was 94.1%.

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content may change prior to final publication. Citation information: DOI 10.1109/TIA.2022.3191302

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