2862
3, MAY/JUNE 2020
FPA Optimized Selective Harmonic Elimination in
Symmetric–Asymmetric Reduced Switch
Cascaded Multilevel Inverter
Kaibalya Prasad Panda , Student Member, IEEE, Prabhat Ranjan Bana , Student Member, IEEE,
and Gayadhar Panda, Senior Member, IEEE
Abstract—Symmetrical and asymmetrical multilevel inverters
(MLIs) have demonstrated its usefulness in a wide range of appli-
cations. This is accomplished due to the ongoing improvement by
reducing the converter size and enhancement in the voltage quality.
In this article, a generalized cascaded MLI structure is developed,
which can operate in both symmetric and asymmetric modes.
Comparative assessment in terms of the number of components
and voltage stress warrants the design superiority. A new selective
harmonic elimination (SHE) control using flower pollination algo-
rithm (FPA) is investigated for the developed asymmetrical MLI.
The salient features of the FPA such as less burdensome compilation
and ability tos single-stage local and global search ascertain the
elimination of the targeted harmonics through optimum angles
computation. Moreover, the competence of the FPA is verified by
comparing it with well-known SHE algorithms. Simulation analysis
is carried out in MATLAB/Simulink environment, which validates
the workability of the developed system. Experimental tests using
fundamental and high switching frequency control techniques are
further conducted under a dynamic environment to demonstrate
the efficacy of the proposed methodology.
Index Terms—Flower pollination algorithm (FPA), reduced
components, selective harmonic elimination (SHE), switched-diode
multilevel inverter (SMLI), symmetric–asymmetric multilevel
inverter (MLI).
I. INTRODUCTION
ULTILEVEL inverters (MLIs) are dominating over con-
M ventional inverters due to their ability to operate in a vast
range of applications [1]–[5]. Enhanced interference compatibil-
ity, low voltage stress, improved efficiency, and power quality are
the key factors behind the tremendous growth and application of
Manuscript received October 25, 2019; revised February 9, 2020; accepted
March 12, 2020. Date of publication March 18, 2020; date of current version
April 24, 2020. Paper 2019-IPCC-1365.R1, presented at the 2018 IEEE Interna-
tional Conference on Power Electronics, Drives and Energy Systems, Chennai,
India, Dec. 18–21, and approved for publication in the IEEE TRANSACTIONS
ON INDUSTRY APPLICATIONS by the Industrial Power Converter Committee of
the IEEE Industry Applications Society. This work was supported in part by the
Department of Science and Technology (DST), Government of India Project
under Grant EMR/2017/001880 and in part by the Institution of Engineers (In-
dia) R&D Grant-in-Aid scheme under Grant RDDR2017017. (Corresponding
author: Kaibalya Prasad Panda.)
The authors are with the Department of Electrical Engineering,
National Institute of Technology, Shillong, Meghalaya, India (e-mail:
kaibalyapanda@nitm.ac.in; prabhat.bana@nitm.ac.in; gayadhar.panda@
nitm.ac.in).
Color versions of one or more of the figures in this article are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIA.2020.2981601
0093-9994 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO.
MLIs in industries, electric vehicles, and renewable power gen-
eration [3]–[7]. MLIs can synthesize staircase sinusoidal-like
output depending on the number of dc sources, semiconduc-
tor switches, diodes, and capacitors used in the circuit. Three
widely used classical MLI structures are diode-clamped MLI
(DMLI), flying capacitor MLI (FMLI), and cascaded H-bridge
MLI (CMLI) [2], [8]–[10]. Voltage balancing, need of clamping
diodes/capacitors, liability to module failure due to series con-
nection of switches are the major concerns in DMLIs and FMLIs.
Compared to these single dc MLIs, multi-dc CMLIs are gaining
a great deal of interest due to the modularity and reliability fea-
tures. Further, symmetrical CMLIs have more straightforward
control, while asymmetric topologies can significantly enhance
the number of levels using the same number of components [11].
However, a strong limitation of the classical MLIs is the
requirement of more number of semiconductor switches and dc
sources. In recent years, continuous research efforts have been
made to optimize the MLI structure in all possible means. MLIs
are researched in three wide varieties such as switched-dc MLI,
switched-capacitor MLI, and switched-diode MLIs (SMLIs)
[12]. In [13], a switched-dc symmetrical structure has been
recommended using a reduced number of switches compared
to the classical structures. This topology does not require a
back-end H-bridge for altering the polarity; however, it still
requires isolated sources identical to the CMLI for synthesizing
any voltage level. In the switched-dc category, structures pro-
posed in [14], [15] are also competitive and cost-effective. These
reduced switch structures can inherently reverse voltage polarity,
and higher voltage steps can be produced by cascading the basic
units. Using the H-bridge integrated to the basic units, optimal
structures are disclosed in [16], [17] that can produce 15 levels
using 16 number of switches and 7 isolated dc sources. There
is also a possibility of extension to generate any voltage levels
utilizing different magnitudes of dc sources and with a reduced
voltage stress on the switches. Based on the above concept,
symmetrical and asymmetrical MLIs with different pulse width
modulation (PWM) control strategies have also been presented
in [18] and [19], respectively. In [20]–[22], switched-dc compact
module topologies have been analyzed as a suitable replacement
of the conventional MLIs.
The MLIs, as mentioned earlier, reduce the switch count
but do not possess voltage boosting ability. Consequently,
switched-capacitor structures are developed, which can enhance
PANDA et al.: FPA OPTIMIZED SELECTIVE HARMONIC ELIMINATION IN SYMMETRIC–ASYMMETRIC REDUCED SWITCH CASCADED MLI 2863

the voltage levels without the need for additional transform-

ers and inductors [23]. Using the same basic unit, structures
presented in [24], [25] effectively reduce the number of semi-
conducting devices and also feature voltage boosting ability.
Extended switched-capacitor structures with low cost, few dc
sources, and less total standing voltage (TSV) have been pro-
posed more recently in [26], [27]. The self-regulatory capacitor
voltage using the series–parallel charge–discharge technique is
an added advantage of these structures.
The involvement of more switches increases the number of Fig. 1. Generalized structure of the developed cascaded SMLI.
the driver circuits and thus the control complexity. The switched-
diode structures are developed with the motivation of making the
circuit simpler. Circuit topologies presented in [28]–[30] need
for enhancement of the voltage levels by a suitable dc source
much simpler control. For five-level and seven-level operations,
magnitude selection. Section III confirms the practicality of
these structures warrant a reduced number of switch and low
topological advancement by comparing it with prior-art MLI
power loss. These switched-diode structures are suitable for high
structures. Section IV affirms the superiority of the FPA com-
power factor loads, whereas for low power factor, loading spikes
pared to well-known SHE-PWM control schemes in light of
in the output voltage may appear due to the presence of diodes
faster convergence and harmonic suppression performance in
in the reverse current flow path. A feasible trade-off is therefore
the whole modulation range. To verify the workability of the
vital between the circuit simplicity and load handling ability for
developed asymmetrical MLI in conjunction with FPA control,
different applications.
simulation and experimental verifications are incorporated in
Apart from the design issues discussed above, the imple-
Sections V and VIs, respectively. The last section concludes the
mentation of a suitable control technique for MLI is a key
research work.
challenge to improve the voltage and current quality [11], [31].
To effectively reduce the switching power losses and completely
eliminate the dominant harmonic components, the selective II. DEVELOPED CASCADED MULTILEVEL INVERTER
harmonic elimination (SHE) control technique based on fun- The developed SMLI is assembled using the cascaded con-
damental frequency is widely adopted over carrier-based PWM nection of dual-source modules (DSM) [29]. The DSM con-
techniques [19], [22], [32]–[34]. The fundamental level is main- sists of two dc sources (V1 and V2 ), one unidirectional switch
tained in SHE control while eliminating the targeted harmonics (Sa1 ), one power diode (Da1 ), and a polarity changing H-
using the predefined angles. Numerical iterative algorithm based bridge (Ta1 − Ta4 ). When the switch is OFF, the DSM pro-
approaches to find the optimal angles have been attempted duces an output of V1 and when the switch is turned ON, then
extensively in [10], [19], [29], [35], [36]. Literature manifests ro- the output voltage becomes (Va1 = V1 + V2 ). An ac output
bustness of these algorithms considering the practical switching (Va1 , Va2 , . . . , Van ) across each DSM out of the unidirectional
operation, unbalanced sources, solution attainability in extended voltage (Vr1 , Vr2 , . . . , Vrn ) is synthesized by switching the
modulation range, etc. The optimal angles are calculated by H-bridge switches Ta1 and Ta2 in the positive cycle and the
solving harmonic equations with a specific objective. Numer- other two in the negative cycle. The developed SMLI is shown
ical calculation-based approaches have been further analyzed in Fig. 1 which is the cascade connection of several DSMs.
in the literature. To find a solution for different fundamental The output voltage (Vo ) of the SMLI is the summation of
switching voltage patterns, the authors in [37], [38] have re- the outputs of individual DSM as given in (1). For the SMLI,
vealed generalized SHE techniques. Real-time angle calculation generalized expressions are given in (2)–(4) for the switch count
methods have been established [7], [39] for renewable energy (Nsw ) requirement, number of dc sources (Ndc ), and diode count
application and dc voltage variation. Serious challenges such as (Ndd ), respectively, in terms of the number of DSMs (n = 1, 2,
triplen harmonic mitigation from single-phase structures in [22] …), as follows:
and harmonic elimination and total harmonic distortion (THD)
minimization concomitantly in [34] have been subsequently V0 = Va1 + Va2 · · · + Van (1)
analyzed. Selective harmonic mitigation (SHM) technique is Nsw = 5n (2)
another variety of fundamental frequency control scheme that
mitigates more harmonic orders as well as satisfies the power Ndc = 2n (3)
quality standards [40]. Nevertheless, a complete elimination of Ndd = n. (4)
dominant harmonics as in SHE control is unattainable.
In a recent work [35], the authors have analyzed flower
pollination algorithm (FPA) SHE-PWM control approach in a re- The number of output voltage levels (Nl ) can be further
duced switch symmetrical MLI. Including further developments, extended with the appropriate selection of dc source magnitude.
this article investigates the FPA control scheme application In this context, three algorithms that not only enhance the voltage
in an asymmetrical MLI thoroughly. A generalized cascaded level but also optimize the TSV, switching loss (Ploss ), and
MLI structure with a reduced number of components is first overall cost are further proposed. The first proposed algorithm is
introduced in the next section along with different algorithms the symmetrical case. The other two are based on asymmetrical
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2864
Fig. 2. Comparison with prior-art MLI structures (T1 [17], T2 [14], T3 [26], T4 [25], T5 [15], T6 [13], T7 [16], T8 [19], T9 [24], T10 [20], T11 [18], and T12
[27]). (a) Nsw versus Nl . (b) Ndc versus Nl . (c) CLR versus Nl . (d) TSV versus Nl .
TABLE I
DIFFERENT PROPOSED ALGORITHMS FOR THE DEVELOPED SMLI
cases. With a geometrical progression factor of “3,” the topology
is highly asymmetrical, whereas with the third algorithm con-
sidering alternate binary fashion, the structure is more optimal.
For the different algorithms, Nl , TSV, and Ploss are summarized
in Table I. The switching losses are determined based on the
standing voltage and operating frequency of the switches [13].
For the DSM-1, the level generation switch Sa1 operates at
high frequency (fs ), whereas the other four switches operate
at the fundamental frequency (fo ). Accordingly, the losses are
expressed in the table, taking a constant k = 16 Is (tn + tf )
where Is , tn , and tf are the current through the switch, ON,
and OFF intervals of the switch, respectively.
III. COMPARISON OF THE PROPOSED SMLI WITH
EXISTING TOPOLOGY
To appraise the superiority of the SMLI over existing MLIs,
a comparative assessment is performed in terms of Nsw , Ndc ,
components per level ratio (CLR), and TSV. Symmetrical SMLI
(P1 ) is simple in design, whereas the asymmetrical structures
(P2 and P3 ) can synthesize more levels. Considering both Nl
and TSV, the SMLI with P3 offers more optimality. Therefore,
it is considered for comparison purposes. Fig. 2(a) unveils the
switch requirement w.r.t. Nl for the SMLI is minimum among all
the MLI topologies. The number of dc sources adjudicates the
number of levels at the output. The switched-capacitor structures
T3, T4, and T12 greatly reduce the dc source count as it uses
additional capacitors for level generation. Except for this, the
SMLI utilizes comparatively less Ndc than other MLIs, as shown
in Fig. 2(b). Further, a factor CLR is calculated which is the
ratio between the sum of Nsw , Ndc , Ndd , Ndr , Nc w.r.t. Nl ,
where Ndr and Nc are the number of drivers and capacitors.
Fig. 2(c) confirms that minimum CLR of the SMLI up to 35
levels establishes the topological advancement. For Nl > 35,
however, the T5 and T7 topologies have comparable merits.
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO. 3, MAY/JUNE 2020
TSV is another parameter that plays a significant role while
designing the MLI. For high-power and high-voltage appli-
cations, an MLI with less TSV and less loss is preferable.
The variation of TSV with output voltage levels is shown in
Fig. 2(d). For the generation of the same number of levels at
the output, the SMLIs face relatively less TSV except for the
switched-capacitor MLIs T3 and T9.
IV. SELECTIVE HARMONIC ELIMINATION CONTROL
The SHE control approach is a widely adopted fundamental
switching technique for MLIs to get an improved harmonic
profile [33] in spite of the switching loss being reduced and
the fundamental level being retained. The targeted lower or-
der harmonics defined by a set of harmonic equations can be
eliminated by evaluating a specific fitness function (FF). In
this regard, the generalized staircase output voltage waveform
considering single switching per cycle can be expressed in terms
of the Fourier series. Considering the symmetrical property of
square wave and the Fourier coefficient ao = an = 0, the output
waveform can be mathematically expressed as follows:
∞

Vo (ωt) = Vx sin (xωt)
x=1 (odd)
 4Vdc
= {cos xα1 + · · · + cos xαp } sin (xωt) . (5)
xπ
x=1 (odd)
Henceforth, the dc source magnitude as per the P3 algorithm
is considered for the analysis. Thus, the number of switching
angles (SAs) p = 3n, where n is the number of DSMs and Vdc
is the value of each voltage step. The fundamental component
can then be expressed as follows:
4Vdc
V1 = {cos xα1 + · · · + cos xαp } sin (xωt) . (6)
π
Taking into consideration the range of modulation index (Mi)
0–1, the SAs (α1 to αp ) can be evaluated. For a specific Mi, the
computed SAs can eliminate the targeted low-order harmonics.
For a 6n + 1 level SMLI, 3n − 1 numbers of harmonic orders
can be eliminated. Considering the desired fundamental (V1 )
and nominal (Vdc1 ) dc voltage, Mi can be defined as follows:
πV1
Mi = , 0 ≤ M i ≤ 1. (7)
(4pVdc1 )
PANDA et al.: FPA OPTIMIZED SELECTIVE HARMONIC ELIMINATION IN SYMMETRIC–ASYMMETRIC REDUCED SWITCH CASCADED MLI
Fig. 3. Overall block diagram of the implemented PWM control strategies.
The set of generalized harmonic equations are expressed in (8)
that are needed to be solved without losing the fundamental con-
trol and considering the angle constraint given in (9) as follows:
⎧ where
⎪
⎪ cosα1 + · · · + cosαp = p ∗ M i
⎪
⎪ μ ∗ γ (μ) ∗ sin (πμ/2)
⎨ cos 3α1 + · · · + cos 3αp = 0
(8)
⎪ ..
⎪
⎪ .
⎪
⎩
cos (2p − 1) α1 + · · · + cos (2p − 1) αp = 0
0 < α1 < α2 < · · · < αp ≤ π/2.
Literature manifest nonlinear equations involved in the SHE
control scheme can be formulated as an optimization problem
to quickly obtain optimum SAs and continuous solutions for
the whole Mi range [10], [19], [29], [36]. Nevertheless, these
algorithms suffer from shortcomings such as more time con-
sumption in optimizing, discontinuous solution, inaccuracy in
the harmonic suppression performance, etc. Thus, to get the best
performance, this work proposes an FPA-based control scheme
[35] that is analyzed for the asymmetrical SMLI. The nonlinear
transcendental equations are solved and the solutions are stored
in the form of a lookup table. The angles are then decoded
according to the switching logic.
To verify the accurate performance of proposed SMLI and
the controller, both SHE-PWM and SPWM control schemes are
tested in this work. Fig. 3 depicts the overall block diagram
accompanying the control schemes. Considering P3 , the SMLI
with two cascaded DSMs can synthesize a 13-level output. For
the SHE-PWM control, six optimum SAs are calculated using
FPA. For the SPWM control scheme, based on the pulse logic for
the 13-level operation, the carrier signals with a sinusoidal refer-
ence signal are compared, which generates the desired switching
pulses. Pulses with a certain delay period are generated by logic
gates decoder.
A. Proposed FPA Approach for SHE-PWM Control
Yang et al. first observed the characteristics of flower polli-
nation and proposed the FPA in 2012 [41]. Plants follow the
pollination process to produce offspring for the next generation.
Pollination is nothing but the process of transferring pollen
from the male anther to the female stigma of a flower for the
seed formation. Depending on the source of pollen, pollina-
tion can be classified into self-pollination and cross-pollination.
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2865
Self-pollination includes the transfer of pollens from anther to
stigma within the same plant, while cross-pollination includes
two different species of plant for the pollination. Further, on the
basis of the agent of pollination, pollination can be classified
into biotic pollination that involves organisms as the agent
and abiotic pollination, which does not involve organisms. In
FPA, about 90% of pollination is considered as the biotic and
cross-pollination, i.e., pollens are transferred by the pollinator
such as bees, insects, etc. The following three FPA rules are
summarized for optimum SA evaluation.
Rule-a: The global pollination process includes the biotic and
cross-pollination process where the pollinators are supposed to
move by obeying Lévy flights (Lf ). The pollinators travel over
a long distance (xi ) for the pollination which can be expressed
as follows:
 
Ψik+1 = Ψki + Lf ∗ Gbest − Ψki (10)
1
Lf = ∗ 1+μ (S : S > 0) (11)
π S
where Gbest is the current best solution among others, Ψki is the
ith pollen at kth iteration, and γ(μ) is the gamma function that
is distributed over a significant step S > 0.
(9) Rule-b: The update rule for the local pollination process
involving abiotic and self-pollination is given in (12). Ψkm and
Ψkj indicate the pollens of two different local flowers belonging
to the same species of plant and the parameter ρ denotes the
local search distributed uniformly in bound of [0, 1].
 
Ψik+1 = Ψki + ρ ∗ Ψkm − Ψkj (12)
Rule-c: The local pollination process relates to short distance,
whereas the distance is more in the case of global pollination.
Therefore, a switching control between the general global and
profound local pollination process is defined as PS ∈ [0, 1].
B. Working of FPA Optimized SHE Control
For the 13-level SMLI, the 3rd, 5th, 7th, 9th, and 11th or-
der harmonics are selected for elimination. It must be pointed
out that the multiples of third harmonic are self-mitigated in
the three-phase line voltages. A suitable FF is defined in (13)
considering the targeted harmonics and fundamental component
subjected to the condition (9). FPA is programmed to solve the
FF for estimating the optimal SAs.

2p−1
V1∗ − V1
4 2
1 Vx
FF = min 100 + 50 (13)
αp V1∗ x=3
x V1
where V1 ∗ is the reference fundamental component. To obtain
the least THD with a feasible Mi, the first term in (13) is restricted
to 1% error and the second term to 2%. Further, to obtain an
optimal harmonic suppression performance by maintaining the
fundamental level, the first and the second terms are enforced to
powers 4 and 2, respectively [19], [29].
The proposed FPA algorithm summarized below is success-
fully developed in MATLAB R2018a platform to solve the FF
and to calculate optimized SAs for operating the SMLI.
2866
Fig. 4. Programming results for the 13-level SMLI. (a) FF versus Mi. (b) THD versus Mi. (c) CDF versus FF. (d) Harmonics versus Mi. (e) SA versus Mi.
(f) Harmonic spectrum.
TABLE II
COMPARISON OF SHE ALGORITHMS FOR 90 POPULATION SIZES, 400
ITERATIONS, AND 20 TRIAL RUNS
Step-1: Initialize the parameters such as maximum iteration
count (iterm ), PS , and the minimum and maximum range
of the SAs. Randomly initiate the SA population (pollens) for
FF evaluation.
Step-2: To evaluate the stability and quality of the pollens, FF is
evaluated for each αp contingent upon (9). Gbest is initialized
as the optimum FF. For the range of Mi (0:0.01:1), αp is
identified and stored in the memory corresponding to the
optimum FF.
Step-3: All the αp should undergo global pollination (Rule-a) or
the local pollination (Rule-b). Therefore, a uniform distributed
random number (rand) is first generated, and then for each
iteration, if PS > rand, pollens follow Rule-a, else Rule-b.
Step-4: New SAs and corresponding FF are evaluated further to
assess the new Gbest . The optimal SAs in line with the min-
imum FF are updated in the memory. This process continues
until all the pollens converge to minimum FF for the iterm ,
otherwise return to Step-2.
C. Comparison of FPA With Well-Known SHE Algorithms
With the aim to calculate the optimized SAs for eliminating
the targeted harmonics, three recent-art algorithms such as par-
ticle swarm optimization (PSO) [29], teaching learning-based
optimization (TLBO) [36], cuckoo search algorithm (CSA) [10]
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO. 3, MAY/JUNE 2020
are implemented along with the proposed FPA. Parameter set-
tings for all the algorithms are specified in Table II. It should
be noted that the authors have considered several trial runs prior
to the selection of the optimal parameters. The programming is
carried out on a host computer with 8.00-GB installed memory
and an Intel Core, i5, 2.30-GHz processor. Fig. 4(a) shows the
plot between the optimum FF versus Mi. The proposed FPA
is able to minimize the fitness value to below 10−19 for more
than 80% of Mi. The results obtained using CSA are much
closer to the FPA than the other two. Further, the probability of
convergence to the global minima point is evaluated considering
the cumulative distribution function (CDF) [29]. Consequently,
Fig. 4(b) illustrates the superior performance of FPA. Moreover,
the performance parameter THD [11] is taken into account
for comparison among the algorithms. Fig. 4(c) implies that
the THD decreases significantly using the proposed FPA with
the increase in Mi. This also indicates the effectiveness of the
FPA in eliminating low-order harmonics. Out of these algo-
rithms, TLBO and CSA have comparable performance as of
the FPA.
For the 13-level SMLI, the targeted harmonic orders are
evaluated w.r.t. Mi. Fig. 4(d) depicts that, in the range of 0.9–0.95
Mi, the low-order harmonics are completely eliminated and,
at the same time, the fundamental level is maintained which
satisfies the elementary SHE principles. The optimum SAs
obtained using FPA are depicted in Fig. 4(e) that satisfies (9),
and the continuous solution for the full range of Mi is ensured.
The objective of the SHE-PWM control technique is to eliminate
the targeted harmonic orders, whereas the SHM-PWM tech-
nique satisfies the power quality standard grid codes. Nonethe-
less, Fig. 4(f) shows that the low-order harmonic that resulted
using the SHE technique also fulfills the grid-code standards EN
50160 and CIGRE WG 36-05 except the 15th order harmonic
that is not targeted for the 13-level SMLI. This implies that the
use of large-sized filters at the load side can be obviated from
different applications viewpoint.
PANDA et al.: FPA OPTIMIZED SELECTIVE HARMONIC ELIMINATION IN SYMMETRIC–ASYMMETRIC REDUCED SWITCH CASCADED MLI 2867

Fig. 5. Simulation analysis. (a) Developed 13-level SMLI structure. (b) Standing voltage and power losses in the 13-level SMLI. (c) 13-level output with switching
pulse duration. (d) Terminal voltages in the 13-level SMLI.

Fig. 6. Simulation results: 13-level output voltage with corresponding harmonic spectra under changing Mi condition (a) with SHE-PWM control,
(b) with SPWM control, and (c) output voltage with P1 and P2 algorithms.

V. SIMULATION ANALYSIS
The SMLI circuit topology with two DSMs shown in Fig. 5(a)
is used to validate the workability in simulation. Ten numbers
of switches are used in the circuit. Out of these switches, two
switches (Sa1 and Sa2 ) used to create the levels that block the
minimum voltage that can be inferred from Fig. 5(b). Power
losses of the switches are also pictorially depicted, which is
calculated by a detailed simulation of insulated-gate bipolar
transistor (IGBT) switches in the Simulink platform considering
Vdc = 200 V and 150 Ω load. As SHE-PWM is considered, the
switching losses are almost negligible and conduction losses
are the major contributor to the total power losses. Fig. 5(c)
depicts the kind of 13-level output pattern along with conduction
instances of each switch. The 13-level output (Vo ) and voltages
of each unit (Vr1 , Vr2 , Va1 , and Va2 ) are illustrated in Fig. 5(d).
Further, the competence of the control techniques is demon-
strated by applying both SHE-PWM and SPWM control tech-
niques. SAs corresponding to the Mi values are evaluated offline
by the proposed FPA approach and stored in a lookup table. To
verify the optimum THD obtained at 0.93 Mi (as acquired from
the programming results), low (0.25) and medium (0.55) Mi
values are also considered. The harmonic profile along with Vo
for a purely resistive load is shown in Fig. 6(a) which confirms
low overall THD at high Mi, and the results are in agreement
with the programming findings.
In addition, Vo and the respective harmonic profiles are also
acquired with the SPWM control scheme as shown in Fig. 6(b).
In light of this, six triangular carriers with a frequency of 5 kHz
are arranged in the same phase with a finite offset value and
are compared with a reference sinusoidal signal of a nominal
frequency of 50 Hz to generate the desired switching pulses
(see Fig. 3). Superior performance of SHE-PWM control is
established and the fundamental magnitude declines with change
in Mi for the SPWM control. Further, to endorse all the proposed
algorithms given in Table I for selection of dc source magnitude,
results are also shown for P1 and P2 in Fig. 6(c) considering the
equal output voltage of 1200 V. Considering two DSMs that are
cascaded as shown in Fig. 5(a), the SMLI synthesizes 9-level
and 17-level using P1 and P2 , respectively.

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2868 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 56, NO. 3, MAY/JUNE 2020

Fig. 7. Experimental results of output voltage and current waveform, voltages of different units, and standing voltage of some switches with (a) P1 , (b) P2 , and
(c) P3 .

Fig. 8. Experimental verification of the control schemes. (a) Output voltage with changing Mi. (b) Output voltage and current under R-load. (c) Output voltage
and current under changing RL-load. (d) Harmonic analysis of the output voltage under different Mi. (e) Output voltage with dynamic change in frequency. (f)
Output voltage and current under RL-load with SPWM control. (g) Output voltage harmonic profile with SPWM control.

VI. EXPERIMENTAL VERIFICATION
In order to validate the topological advancement and the
control efficiency of FPA, a scaled-down laboratory prototype
of the SMLI is used which consists of two cascaded DSMs, four
isolated variable dc supplies, ten 12N60A4D IGBT switches,
and two RGP30D diodes. Control techniques are developed in
a TMS320F28335 control card. The controller transfers pulses
to the switches through a TLP250 optocoupler driver that en-
ables the necessary isolation and pulse amplification. Results
are acquired using a ScopeCoder under an RL-load of value
50 Ω–6.3 mH unless otherwise specified.

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PANDA et al.: FPA OPTIMIZED SELECTIVE HARMONIC ELIMINATION IN SYMMETRIC–ASYMMETRIC REDUCED SWITCH CASCADED MLI
A. Validation of SMLI Operation Using Proposed Algorithms
In order to evaluate the operational ability of the SMLI in
relation to the number of levels indicated in Table I, magni-
tudes of the dc sources are selected accordingly. The SMLI can
synthesize 9-level, 17-level, and 13-level using P1 , P2 , and P3 ,
respectively, considering two DSMs are cascaded. In the case of
P1 , P2 , and P3 , the magnitude of the four dc sources are set as
(30 V, 30 V, 30 V, 30 V), (15 V, 15 V, 45 V, 45 V), and (20 V,
40 V, 40 V, 20 V), respectively. Applying the FPA-SHE control,
optimum SAs are programmed in the controller for 9-level,
17-level, and 13-level operations. Consequently, Fig. 7(a)–(c)
shows the successful working of the SMLI. The figure also
includes the voltage across different units (Vr1 , Vr2 , Va1 , and
Va2 ) and the standing voltage across few switches (Sa1 , Sa2 , Ta1 ,
and Td2 ). It is worth to mention that the P2 algorithm appreciably
increases the voltage level with the same component count, but
the switches have to withstand a higher TSV. On that account,
SMLI with P3 offers an optimal Nl and TSV.
B. Validation of the SHE-PWM and SPWM Control Schemes
Considering the 13-level SMLI, six SAs corresponding to
each Mi values obtained using FPA are stored in the form of
a lookup table for getting the desired switching pulses. Similar
to the test performed in simulation, Fig. 8(a) shows the Vo under
a dynamically varying Mi condition. Fig. 8(b) and (c) delineates
the correct functioning of the MLI under a purely resistive load of
50 Ω and with a load variation from RL (50 Ω–6.3 mH) to R1 L1
(20 Ω–6.3 mH), respectively. Fig. 8(d) asserts that the levels
are appropriately synthesized at higher Mi and the dominant
harmonics from 3rd to 11th order are effectually eliminated from
Vo . This implies that the fundamental level is maintained at the
desired level, and, therefore, the % THD value is low. Further,
output frequencies are not same in different parts of the world. In
such a case, the developed MLI should be able to work safely at
any frequency range. To verify this, the proposed SMLI is tested
under a varying output frequency. Fig. 8(e) shows that the voltage
waveform remains unaffected even under a sudden change in
frequency from 50 to 100 Hz which may be required for different
applications. Besides, to compare the performance, the SPWM
control technique is also implemented for the 13-level SMLI.
Fig. 8(f) displays the Vo and Io obtained using the SPWM
control scheme. The associated THD analysis of Vo is depicted
in Fig. 8(g). The % THD in this case is higher than that of SHE
control; yet, the current waveform comparatively attains a more
sinusoidal-like wave shape.
VII. CONCLUSION
This work introduced a generalized cascaded MLI topol-
ogy using a reduced number of components. Three different
algorithms have been proposed for selecting the magnitude of
input sources, which further optimizes the structure. The distinct
characteristics of the proposed asymmetric SMLI configuration
have been ascertained with a fair comparative analysis among
the state-of-the-art MLIs. Both fundamental frequency (SHE)
and high switching frequency (SPWM) control techniques are
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2869
implemented to test the MLI. FPA, as a newly emerging
optimization technique, has been used for the optimal angle
evaluation to eliminate the dominant low-order harmonics from
the output voltage selectively. In comparison with PSO, TLBO,
and CSA, the results reveal fast tracking of FPA towards an
optimal solution, less complicated compilation, and high accu-
racy. The selected 3rd to 11th order harmonics are eliminated
and satisfy the grid-code standards for the 13-level asymmet-
rical MLI, even accounting single switching per cycle voltage
pattern. Extensive simulation and experimental analysis have
been carried out under different dynamic test cases to justify
the proposed method. The developed SMLI works favorably
using different PWM control schemes in both symmetric and
asymmetric modes.
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Kaibalya Prasad Panda (Student Member, IEEE)
received the B.Tech. degree in electrical and elec-
tronics engineering from the Dr. M.G.R. Univer-
sity, Chennai, Tamil Nadu, India, in 2011, and the
M.Tech. degree in power electronics and drives
specialization from KIIT University, Bhubaneswar,
Odisha, India, in 2013.
He is currently a Ph.D. Scholar with the Depart-
ment of Electrical Engineering, NIT Meghalaya, Shil-
long, India.
Prabhat Ranjan Bana (Student Member, IEEE)
received the B.Tech. degree in electrical engineer-
ing from the Parala Maharaja Engineering College,
Berhampur, Odisha, India, in 2016, and the M.Tech.
degree in power and energy systems specialization
from NIT Meghalaya, Shillong, Meghalaya, India, in
2019.
He is currently a Research Fellow with the De-
partment of Electrical Engineering, NIT Meghalaya,
Shillong, India.
Gayadhar Panda (Senior Member, IEEE) received
the B.E. degree in electrical engineering from the
Institute of Engineers, West Bengal, Kolkata, India,
the master’s degree in power electronics from the
Indian Institute of Engineering Science and Tech-
nology, Shibpur, Howrah, West Bengal, India, and
the Ph.D. degree in electrical engineering from Utkal
University, Bhubaneswar, Odisha, India, in 1996,
1998, and 2007, respectively.
Since January 2013, he has been with the De-
partment of Electrical Engineering, NIT Meghalaya,
Shillong, India, where he is currently a Professor.