IET Power Electronics

Research Article

ISSN 1755-4535
Hybrid topology of symmetrical multilevel Received on 2nd February 2015
Revised on 8th April 2015
inverter using less number of devices Accepted on 8th May 2015
doi: 10.1049/iet-pel.2015.0037
www.ietdl.org

Shivam Prakash Gautam, Lalit Kumar ✉, Shubhrata Gupta

Department of Electrical Engineering, National Institute of Technology, Raipur 492010, India
✉ E-mail: lkumar.ele@nitrr.ac.in

Abstract: The interest in development of newer topologies of multilevel inverter has been increasing rapidly in past few
years. Recently introduced topologies achieve higher number of output voltage steps with reduced number of switches,
DC voltage sources, voltage stress across switches and losses as compared with the conventional topologies. In this study,
a new structure of symmetrical multilevel inverter is proposed. The proposed structure offers reduced number of
controlled switches, power diodes and DC sources as compared with classical and recently proposed topologies in the
literature. Reduction of switch count and DC voltage sources reduces the size, cost, complexity and enhances overall
performance. Proposed topology is capable of producing 7, 9 and 11 levels of output voltage with seven switches only.
Moreover, significant reduction in voltage stress across the switches can be achieved. A comparative analysis of
proposed topology with the conventional topology and recently published topologies has been made in terms of
controlled switches, power diodes, driver circuit requirement, DC voltage sources and blocking voltage. Multi-carrier
pulse-width modulation strategy is adopted for generating the switching pulses. Simulation study of the proposed
topology has been carried out using Matlab/Simulink and feasibility of topology has been validated experimentally.

1 Introduction configuration of CHB produces higher number of voltage level as

Multilevel inverter (MLI) was first introduced in 1975, since its
invention the demand has been growing rapidly in the field of
DC/AC power conversion and associated applications [1]. MLI is
a key technology and plays crucial role in AC motor drives,
uninterruptible power supplies, high-voltage DC power
transmission, flexible AC transmission systems, static var
compensators, active filters, electric and hybrid electric vehicles
and integration and utilisation of renewable energy sources [2–14].
In the field of high-power medium-voltage DC/AC conversion,
MLI is receiving tremendous popularity both in terms of topology
and control scheme because of its good power quality, less total
harmonic distortion (THD), reduced voltage stress across the
switches, good electromagnetic compatibility, less switching losses
and dv/dt stress. However, MLI possess some drawbacks, that is,
to increase output levels, the number of semiconductor switch
requirement along with peripherals devices like gate driver circuit,
protection circuit and heat sink increases. Increased device count
makes overall system complex, bulky and costly and reduces the
reliability and efficiency of the converter.
Traditionally, MLIs are classified as cascaded H-bridge (CHB),
flying capacitor (FC) and neutral point clamped (NPC). In past
few decades, most of the literatures published shows the study on
CHB, FC and NPC topologies with respect to their respective
advantages and disadvantages [15] and these topologies are now
widely referred to as the ‘classical topologies’. None of the
classical topologies seem to be absolutely advantageous as
multilevel solutions are heavily influenced by application and
component count, cost and complexity considerations. Among the
classical MLI, CHB has received wide attention because of its
modularity and simplicity; however, the requirement of isolated
source is a limitation of the topology [16]. A CHB MLI is
composed of several H-bridge cell and isolated DC source. On the
basis of voltage magnitude DC source, CHB is classified as
symmetric and asymmetric configuration. In symmetric
configuration, the magnitudes of DC sources are equal (V1 = V2 =
V3…), whereas in asymmetric configuration magnitudes of DC
sources are not equal (V1 ≠ V2 ≠ V3….). The asymmetric
compared with symmetric configuration for same number of power
switches [15]. Along with the exploration of CHB, researchers
paid dedicated effort and attention to evolve newer application
oriented topologies with reduced number of device count and
complexity.
Consequently, in past few years, large numbers of topologies and
control scheme have been proposed with reduced device count
which utilises a combination of unidirectional and bidirectional
switches of different ratings [15–41], some of them are reviewed
here briefly. In [16–21], symmetrical topologies of MLIs are
discussed, the cost of these inverters is less because of low variety
of DC sources, but the modularity of these MLIs is major concern
in various applications. Similarly in [22–35], asymmetrical
topologies of MLI with reduced number of switches are presented,
but the requirement of large number of bidirectional switches is a
major issue in these topologies. A new topology with reduced
number of switches is presented in [32] which is further optimised
in [33]. The main limitation of these topologies is that all the steps
(additive and subtractive) cannot be achieved with proposed
algorithms. Another topology of MLI composed of several
bidirectional switches is proposed in [34]. Owing to bidirectional
switches, device count and voltage stress across switches is higher.
In [35], the topology with reduced switches is proposed but the
variety of DC voltage sources is the main drawback of the
topology. Topology of MLI presented in [36] utilises
low-frequency high-power switches because of which there is
presence of lower order harmonics in output waveform which is
the major drawback. In [37, 38], topology incorporates
multi-winding transformer because of which cost and complexity
of the overall topology increases. A four-level inverter topology is
presented in [39], but the presented topology is unable to provide
zero-voltage level which results in high r.m.s. value and harmonic
energy is concentrated at switching frequency. In [40], another
topology of MLI is presented, but the topology requires switches
of different rating. In [41], another topology is presented for
five-level by utilising four DC sources, whereas in conventional
topologies up to nine-level can be reached by utilising four DC
sources. Existing literature reflects that the most of the published

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MLI topologies in recent years are claiming higher outputs levels Table 1 Different combinations of DC voltage source for higher output
with reduced number of switches. However, great compromise has voltage levels
been made in terms of modularity, simplicity, number of Algorithm Values of DC sources No. of output levels Configuration
bidirectional switch, variety of DC source, voltage stress across
switches, reliability and losses. first VS1 = 2 × VS2 7 asymmetrical
Moreover, use of asymmetrical converters is not really extended, second VS1 = VS2 9 symmetrical
because they are not suitable for industrial applications because 2
third VS1 = × VS2 11 asymmetrical
modularity is lost and it has different type of semiconductors. 3
Hence, this paper focuses on symmetrical MLI topologies and tries
to solve the problems related to it. In this paper, new topology of
symmetrical MLI is proposed which uses hexagon switch cell Table 2 Comparison of different nine-level inverter topologies for
(HSC). The proposed topology is capable of producing 7-/9-/11- symmetrical MLI
output levels by utilising seven controlled switches. It has modular Components Proposed topology-I NPC FC CHB
structure and offers reliable operation with reduced voltage stress
across the switches. The inherent balancing of capacitor voltage main power switches 6 16 16 16
minimises variety of DC source. The symmetrical configuration of auxiliary switch 1 0 0 0
proposed topology generates higher number of output levels with diodes 10 72 16 16
capacitors 2 8 36 –
comparatively less number of switches. The numbers of
bidirectional switches also reduce considerably in the proposed
topology. An exhaustive comparison of proposed topology with
classical topologies and most recent work in the field is carried out
to highlight the novelty and benefit of the proposed topology. To evaluate total number of component count, the topology-I is
The organisation of paper is as follows. In Section 2, the proposed-I compared with classical topologies for nine-level output and
and proposed-II topologies of MLI for symmetrical configuration is summarised in Table 2.
explained and its working is given. Section 3 deals with the Main power switches: The proposed topology-I in symmetrical
simulation and experimental results of the proposed topologies. configuration achieves 56.25% (7 instead of 16) reduction in the
Section 4 gives the comparison of symmetrical topology to the number of main power switches required as compared with
earlier presented topologies. Finally, conclusion is given in Section 5. classical topologies.
Power diodes: The proposed topology-I in symmetrical
configuration achieves 37.5% (10 instead of 16) reduction in the
2 Proposed MLI topologies number of diodes required as compared with FC and CHB,
whereas percentage of reduction increases to 86.11% (10 instead
2.1 Proposed topology-I of 72) as compared with NPC. Similarly, it achieves 74% (2
instead of 8) reduction in number of capacitor required when
The configuration of topology-I is illustrated in Fig. 1a. It consists of compared with the NPC and 94.44% (2 instead of 36) reduction
two DC voltage source VS1 and VS2, along with capacitor C1 and C2 when compared with the FC.
which forms voltage divider circuit. An auxiliary switch is formed by The different operating modes and switching states along with
controlled switch S7 and four diodes D7, D8, D9 and D10 which are corresponding output voltage levels for nine-level inverter are
connected to HSC composed by six switches S1, S2, S3, S4, S5 and summarised in Fig. 2 and Table 3, respectively. Similarly, the
S6. When the values of the DC voltage sources are equal, that is, different switching states of topology-I in asymmetrical
VS1 = VS2 then it can be referred to as symmetrical MLI otherwise configuration for synthesising 7-level and 11-level are summarised
asymmetrical. Topology-I is capable of producing 7-/9-/11-level in Tables 4 and 5, respectively. The generalisation of topology-I in
output with certain combination of DC voltage source while symmetrical configuration for N-level output is given as
incorporating only seven controlled switches. The output voltage
level with particular combination of DC voltage source is Total number of controlled switches required = (N + 19) 4 4
summarised in Table 1. The generalised form of proposed
topology-I is shown in Fig. 1b. (1)

Fig. 1 Configuration and generalised form of topology-I

a Configuration of proposed topology-I for nine-level inverter
b Generalised configuration of proposed topology-I

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Fig. 2 Different operating modes of topology-I for nine-level output

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Table 3 Different switching states of topology-I for nine-level output
Output levels, V ‘ON’ state switches Conducting diodes

1 S4, S7 D6, D7, D10

2 S4, S5 D2
3 S4, S5, S7 D7, D10
4 S1, S4, S5 –
0 – –
−1 S3, S7 D5, D8, D9
−2 S3, S6 D1
−3 S3, S6, S7 D8, D9
−4 S2, S3, S6 –

Table 4 Different switching states of topology-I for seven-level output

(VS1 = 2 V, VS2 = 1 V)

Output levels, V ‘ON’ state switches Conducting diodes

1 S4, S7 D6, D7, D10

2 S1, S4 D6
3 S1, S4, S5 –
0 – –
−1 S3, S7 D5, D8, D9
−2 S2, S3 D5
−3 S2, S3, S6 –

Table 5 Different switching states of topology-I for 11-level output

(VS1 = 2 V, VS2 = 3 V)

Output levels, V ‘ON’ state switches Conducting diodes Fig. 3 Configuration of proposed topology-II

1 S4, S7 D6, D7, D10

2 S1, S4 D6
3 S4, S5 D2
4 S4, S5, S7 D7, D10
5 S1, S4, S5 – high-voltage switches which are turned ‘ON’ and ‘OFF’ once
0 – – during a fundamental cycle, hence switching and conduction
−1 S3, S7 D5, D8, D9
−2 S2, S3 D5
−3 S3, S6 D1
−4 S3, S6, S7 D8, D9
−5 S2, S3, S6 – higher voltage applications. Hence, in order to overcome this
Total number of diodes required = (N + 1)
Total number of DC sources required = 2
Total number of capacitors required = (N − 1) 4 4
2.2 Proposed topology-II, that is, proposed cascade
connected MLI
A MLI synthesises a stepped waveform consisting of the input DC
levels and their additive and/or subtractive combinations. Thus, the
voltage waveform consists of multiple ‘levels’ with both ‘positive’
and ‘negative’ polarities (in positive and negative half cycles,
respectively). Many a times, a MLI topology synthesises the
multiple levels with only one polarity and H-bridge is used as
polarity converter as presented in [17–20, 24, 26, 30, 33–35].
These parts are, respectively, referred to as ‘level-generation part’
and ‘polarity-generation part’. It is important to mention here that
the power switches for the polarity generation part need to have a
minimum voltage rating equal to the operating voltage of the MLI.
Hence, in the topologies presented in [17–20, 24, 26, 30, 33–35]
the H-bridge is used as polarity generator and the switches of
H-bridge must be able to tolerate the voltage equal to rated output
voltage of MLI. These four switches of H-bridge turn ‘ON’ and
‘OFF’ once during a fundamental cycle, hence these four switches
restrict the application of presented topologies for high voltage. In
continuation with the above discussion, in proposed topology-I
only two switches (S3 and S4) have to bear the full rated voltage
when compared with four of those topologies presented in [17–20,
24, 26, 30, 33–35]. These two switches are low-frequency
losses decreases by considerable amount. Still the problem persists
with the two switches, that is, S3 and S4 have to bear the full rated
voltage which resists the application of proposed topology-I in
problem cascade connection of the proposed topology-I is used
which is shown in Fig. 3.
The configuration of proposed topology-II is shown in Fig. 3. It is
(2) modification of topology-I in order to overcome the problem of
voltage stress across the switches so that the proposed topology
(3) can be applied in higher voltage application. Topology-II is also
composed of one auxiliary switch connected to HSC. The
(4) composed switch network is supplied by two DC voltage source
along with two capacitors. It contains cascade connection of
several fundamental cells that can be operated for higher voltage
applications in symmetrical configuration. Each cell contains seven
controlled switches, ten power diodes, two DC sources and two
capacitors. The DC source on each cell is numbered as VS1,1,
VS2,1, ..., VS1,n, VS2,n (‘where n denotes number of cascaded cell’).
The different operating modes and switching states along with
corresponding output voltage levels for 17-level inverter are
summarised in Fig. 4. The generalisation of topology-II in
symmetrical configuration for N-level output is given as
7
Total number of controlled switches required = × (N − 1) (5)
8
5
Total number of diodes required = × (N − 1) (6)
4
1
Total number of DC sources required = × (N − 1) (7)
4
1
Total number of capacitors required = × (N − 1) (8)
4

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Fig. 4 Different operating modes of topology-II for 17-level output

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Table 6 Simulation and experiment parameters 3 Simulation and experimental results
Parameters Topology-I Topology-I Topology-II
9-level 11-level 17-level 3.1 Modulation scheme

source-I 24 V 12 V VS1,1 = 10 V, Multi-carrier pulse-width modulation technique has been employed

VS2,1 = 10 V with carrier frequency of 100 and 5000 Hz, whereas reference
source-II 24 V 18 V VS2,2 = 10 V, signal frequency is kept at 50 Hz. In multi-carrier pulse-width
VS2,2 = 10 V
capacitor, µF 1200 1200 1200
modulation scheme, carrier signals are compared with reference
R, Ω 50 50 50 signal and pulses so obtained are used for switching of devices
switching 100 and 5000 100 100 corresponding to their respective voltage levels. Number of carrier
frequency, Hz increases as the number of levels increases and the increment is
modulation index unity, 0.9, 0.8 unity unity
and 0.5
directly proportional.

3.2 Simulation results

To examine the performance of the proposed topologies, simulation

has been carried out using Matlab/Simulink. Different simulation
and experimentation parameters for topology-I and topology-II are

Fig. 5 Simulink block diagram for nine-level proposed-I topology

a Multi-carrier pulse width modulation strategy
b Logic operators for generating gate pulses
c Nine-level proposed-I inverter Simulink model

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given in Table 6. Topology-I is simulated for symmetrical and
asymmetrical configurations as 9-level and 11-level inverters,
respectively. Simulink block diagram for nine-level proposed-I
topology is given in Fig. 5 in which Fig. 5a shows the switching
strategy employed for nine-level inverter, Fig. 5b shows the logic
operations in order to obtain gate pulses and Fig. 5c shows the
Simulink model of proposed-I nine-level inverter. The simulation
result at 100 Hz carrier frequency for 9-level and 11-level inverters
and their corresponding THD are shown in Figs. 6a and b.
Topology-II is simulated in symmetrical configuration to obtain
17-level. The simulation result for 17-level is shown in Fig. 6c.
Fig. 6d shows the balanced voltages on series connected capacitors
for 9-/17-level inverters. The simulation result at 5000 Hz carrier
frequency for nine-level inverter is given in Fig. 7 at different
modulation index. A comparison of THD obtained for both
topology-I and topology-II has been presented in Table 7.
3.3 Experimental results
To validate the concept and ensure the feasibility of the proposed
topologies, an experimental setup of the proposed 9-level and

Fig. 6 Simulation results for 100 Hz carrier frequency

a Nine-level output voltage and corresponding THD
b Eleven-level output voltage and corresponding THD
c Seventeen-level output voltage and corresponding THD
d Balanced voltage in series connected capacitors for 9- and /17-level inverters

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Fig. 7 Nine-level simulation results for 5000 Hz carrier frequency
a At modulation index of unity
b At modulation index of 0.9
c At modulation index of 0.8
d At modulation index of 0.5
Table 7 Analysis of THD for 9-/11-/17-level inverters
MLI topology Controlled Output Simulated THD,
switches levels % the full rated voltage of the inverter. Hence, topology-II is best
topology-I 7 9 12.14
symmetric
topology-I 7 11 10.11
asymmetric
topology-II 14 17 5.89
symmetric
11-level inverters has been developed and validated experimentally.
dSPACE DS1103 real-time digital controller has been used for
generating switching pulses. To provide DC voltages for 9-level
inverter, two identical 24 V batteries are used for input voltage
and for 11-level inverter two batteries of 12 and 18 V are used.
Experimental results are obtained at two different carrier
frequencies of 100 and 5000 Hz. All the waveforms are measured
and recorded with the help of power quality analyser (Fluke
434-II) and Agilent’s dual channel oscilloscope.
Fig. 8 shows the experimental results obtained at two different
carrier frequencies of 100 and 5000 Hz. Fig. 8a shows the
experimental output voltage waveform and its corresponding THD
for proposed-I nine-level inverter at carrier frequency of 100 Hz.
Fig. 8a also depicts the current waveform as well as voltage across
the two capacitors. It can be seen that both the capacitors maintain
VDC/2 (i.e. 12 V each) voltage. Hence, voltage balancing is not an
issue in proposed-I topology. Fig. 8b shows the experimental
results obtained at carrier frequency of 5000 Hz. Fig. 8b shows the
output voltage, current and capacitor voltages for nine-level
inverter at modulation index of 1.0 and 0.8, respectively. From
Figs. 8a and b, it can be seen that irrespective of modulation and
switching frequency, the voltage across the capacitors always
remains balanced. Fig. 8c shows the output voltage waveform for
11-level inverter along with its corresponding THD.
4 Comparison study
To show the novelty and benefits of the proposed topologies over the
classical topologies and recently proposed topologies, a comparison
is made in terms to number of switches, driver circuits, diodes and
DC source required. It can be seen that the proposed topology-I
has superior performance in symmetrical configuration as
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compared with topology-II and rest of the other topologies, but it
has been already mentioned that for high-voltage application
topology-I is not an ideal one because two (S3 and S4) have to bear
suited for high-voltage applications. The generalised comparison
for symmetrical configuration is summarised in Table 8.
It is noted that the topology-I in symmetrical configuration requires
the least amount of switches to generate particular output levels as
compared with topology-II and others topologies. A comparison
based on number of output levels against number of insulated gate
bipolar transistor (IGBT) required is made between proposed
topology-I and topologies presented in [17–21, 31] and plotted in
Fig. 9a. Similarly, the number of diode required in topology-I is
less as compared with [17, 18, 20, 31] and topology-II and equals
to topologies presented in [19, 21] as shown in Fig. 9b. In addition,
number of DC sources required is significantly less as compared
with the recently proposed topologies as depicted in Fig. 9c. It can
be observed that the proposed topology-I produces higher number
of output levels with reduce number of part count.
In comparison of proposed topologies with existing topologies, it
can be observed that, topology-I offers less number of switches,
driver circuit, diodes and DC sources requirement. Consequently,
cost, complexity and size of the topology-I is reduced. However,
the main drawback of topology-I is that two of its switches limits
its high-voltage applications. It is noted here that the same
problem occurs in topologies presented in [17–20, 24, 26, 30,
33–35] where four switches have to bear the full rated voltage
which limits their applications for high-voltage applications.
Although in topology-I the number of switches that need to bear
the full rated voltage has been reduced to two, the problem still
remains unsolved. Hence, the solution is provided in topology-II
where the cascaded connection is used. Hence, it depends on type
of application, that is, for low-to-medium voltage application
topology-I is best suited, whereas in high-voltage application
topology-II is preferred. Moreover, DC source requirement is best
among the other compared topologies, and hence offers reduced
cost and complexity. The detailed summary of comparison of total
number of component required is presented in Fig. 9d and Table 8
where ‘N’ denotes number of output levels.
5 Conclusion
In this paper, a novel topology of symmetrical configuration of MLI is
proposed. For a wide range of application (i.e. medium–to-high
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Fig. 8 Experimental results obtained at two different carrier frequencies of 100 and 5000 Hz
a Nine-level experimental output voltage and current along with its capacitors voltages and its corresponding THD at 100 Hz of carrier frequency
b Nine-level experimental output voltage and current waveform along with its capacitors voltage at 5000 Hz of carrier frequency at modulation index of unity and 0.8
c Eleven-level experimental output voltage and its corresponding THD

voltage) topology-I has been modified to topology-II and its operation
is explained. First, the topology in symmetrical configuration is
presented and a comparison is drawn for nine-level inverters. Then,
symmetrical version of the proposed topology-II is given along
with its operating states. The proposed topologies reduce the
number of controlled switches significantly when compared with
conventional ones and other topologies presented recently. A wide
range of comparison is made between the proposed topology and
some of the recent published topology. The comparison shows that
the minimum number of IGBTs, diodes, capacitors and blocking
voltage of switches to maximum number of levels for output
voltage is obtained. Finally, the proposed topologies have been
verified through simulation and electrical feasibility has been tested
experimentally.

Table 8 Components requirements for single-phase symmetrical MLI

Components MLI type

Topology-I Topology-II NPC FC CHB [17] [18] [19] [20] [21] [31]

main switches (N + 19)/4 7(N − 1)/8 2(N − 1) 2(N − 1) 2(N − 1) (N + 5)/2 (N + 3) (N + 5)/2 (N + 1) (N + 1) 3(N − 1)/2
main diodes (N + 1) 5(N − 1)/2 2(N − 1) 2(N − 1) 2(N − 1) 2(N − 1) (N + 3) (N + 5)/2 (N + 1) (N + 1) 3(N − 1)/2
clamping diodes 0 0 (N − 1) × (N − 2) 0 0 0 0 (N − 3)/2 (N − 3)/2 0 0
DC bus capacitor/ (N + 7)/4 (N − 1)/2 (N − 1)/3 (N − 1)/3 (N − 1)/2 (N + 1)/2 (N − 1)/2 (N − 1)/2 (N − 1)/2 (N − 1)/2 (N − 1)/2
isolated supply
FC 0 0 0 (N − 1) × (N − 2)/2 0 0 0 0 0 0 0
total (3/2)(N + 5) (21/8)(N − 1) (N − 1) × (3N + 7)/3 (N − 1) × (3N + 20)/3 (9/2) × (N − 1) (3N + 1) (5N + 11)/2 (2N + 3) 3N (5N + 3)/2 7(N − 1)/2

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Fig. 9 Comparison based on number of output levels against
a Number of IGBTs
b Number of diodes
c Number of DC sources
d Total number of components required
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