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Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Analysis and design of a two-stage amplifier

with enhanced performance
Alireza Mesri a,n, Javad Javidan a, Mahmoud Mahdipour Pirbazari b
a
Engineering Department, University of Mohaghegh Ardabili, Ardabil, Iran
b
Microelectronics Research Laboratory, Urmia University, Urmia, Iran

art ic l e i nf o a b s t r a c t

Article history: A high gain two-stage amplifier is presented in this paper, with detailed theoretical analysis. The proposed
Received 25 March 2015 topology employs positive resistive-capacitive feedback to introduce an extra left half plane zero to cancel a
Received in revised form non-dominant pole at the output of the first stage. Since the dominant pole is at the output of the
29 September 2015
amplifier, stability of the amplifier will not be sensitive to load variations. The proposed amplifier is
Accepted 4 October 2015
designed in a 0.18 mm complementary metal-oxide-semiconductor process with a core area of 2597 mm2.
The amplifier dissipates 0.896 mW from a 1.8 V power supply. Also, DC gain, gain bandwidth (GBW), phase
Keywords: margin and slew rate for a 10 pF capacitive load are 79.5 dB, 93.6 MHz, 66.9° and 18.2 V/mS, respectively.
Two-stage amplifier Moreover, the proposed amplifier topology and the adopted compensation scheme provide 35.3 dB for
Frequency compensation
common-mode rejection ratio and 27.1 dB for positive power supply rejection ratio at GBW frequency. For
Slew rate
1% and 0.1% accuracy, settling times of the proposed two-stage amplifier are 31.2 and 47.3 ns for 0.5 V input
PSRR
CMRR signal and 10 pF capacitive load. Simulation results confirm convenient performance of the circuit at all
process corners, in the presence of a mismatch, power supply noise and input common mode variations.
& 2015 Elsevier Ltd. All rights reserved.

1. Introduction
Amplifiers are fundamental blocks in many applications such as
wireless receivers, high-accuracy sigma–delta modulators, or
pipeline and flash analog to digital converters (ADCs). On the one
hand, high gain is an important specification of amplifiers and has
a decisive role in many applications. For example, switched
capacitor (SC) integrators used in the loop filter of sigma–delta
modulators usually need 70–80 dB gain to reduce phase error and
other nonidealities [1–3]. On the other hand, intrinsic gain of
transistors and power supply voltage are both reduced in modern
complementary metal-oxide-semiconductor(CMOS) technologies.
Therefore, achieving high gain and high swing simultaneously, is a
fundamental challenge in amplifier design [4,5].
Two-stage and three-stage amplifiers are good candidates to
achieve high gain and high swing together. These amplifiers
usually have multiple poles and zeros and need frequency com-
pensation. Miller compensation is the most conventional method,
but the compensation capacitor creates a right half plane (RHP)
zero which degrades phase margin(PM) [5–7]. Voltage and current
buffers can be placed in series with the compensation capacitor to
n slew rate and settling behavior of the amplifier are moderate.
Corresponding author.
E-mail addresses: a.mesri1369@gmail.com (A. Mesri),
javidan@uma.ac.ir (J. Javidan), m.m.pirbazari@gmail.com (M. Mahdipour Pirbazari).
eliminate the effect of the RHP zero. However, voltage buffers limit
the output swing and current buffers decrease the voltage gain,
increase offset and noise, and sometimes require higher current
consumption [7].
Dependence of the stability of two-stage amplifiers to capaci-
tive load variation is a serious drawback in applications such as
multi-mode ADCs and filters with programmable bandwidth.
In [8], simultaneous use of positive and negative feedbacks causes
stability to be insensitive to capacitive load variations. But the
voltage gain of the amplifier is low and approximately equal to
that of single-stage amplifiers.
We have proposed a high gain two-stage amplifier in [9], where
a positive capacitive feedback was used for frequency compensa-
tion. Similar to single stage amplifiers, increasing the capacitive
load even improves the stability. Moreover, it has convenient
performance in process corners due to the adopted structure.
In addition, high positive power supply rejection ratio (PSRR þ )
and common-mode rejection ratio (CMRR) and not requiring a
common mode feedback (CMFB) are other advantages of the our
previously reported two-stage amplifier in [9].
However, due to the stability issues and dependency of the left
half plane (LHP) zero to the bias current of the second stage, the
A high gain two-stage amplifier with improved settling beha-
vior is proposed in this paper. Similar to [9], the performance

http://dx.doi.org/10.1016/j.mejo.2015.10.002
0026-2692/& 2015 Elsevier Ltd. All rights reserved.

Please cite this article as: A. Mesri, et al., Analysis and design of a two-stage amplifier with enhanced performance, Microelectron. J
(2015), http://dx.doi.org/10.1016/j.mejo.2015.10.002i
2 A. Mesri et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
enhanced two-stage amplifier, provides high CMRR and PSRR þ at
high frequency. The performance enhanced amplifier is compen-
sated by a positive resistive-capacitive feedback (PRCF), which
cancels the effect of the non-dominant pole that occurs at the
output of the first stage. Therefore, the dominant pole occurs at
the output node and the amplifier remains stable for larger values
of capacitive load. Putting a resistor in series with the compen-
sation capacitor reduces the distance between the LHP zero and
the non-dominant pole, which can improve the settling time by
reducing the effect of the pole-zero pair [10,11].
Similar to single stage amplifiers, stability of the proposed
amplifier improves with increasing the capacitive load. Therefore,
frequency performance of the proposed amplifier is compared
with single stage amplifiers using mathematical equations, and
some conclusions are drawn.
CMRR and PSRR þ of the proposed amplifier are 35.3 and
27.1 dB at gain bandwidth (GBW) frequency, respectively. These
features are important in mixed-signal systems such as SC filters
and data converters where the supply voltage experiences sever
variations because of the SC and other digital circuits. It is
important to note that PSRR þ approaches 0 dB around the GBW
frequency in Miller compensated amplifiers [12].
When there is a differential swing at the output, symmetry of the
circuit will be violated, especially seen from the output nodes. This
causes the differential CMRR and PSRR þ be finite and reduce when the
output swing increases. Therefore, CMRR and PSRR þ of the proposed
amplifier are shown for different values of the output voltage. Finally,
performance of the circuit is investigated in the presence of a mis-
match, power supply noise and input common mode (CM) variations.
Simulation results confirm convenient performance of the circuit.
The rest of this paper is organized as follows. The proposed
amplifier is presented in Section 2. Section 3 presents simulations
results which demonstrate the circuit performance from various
aspects. Comparisons with our previous work [9] and other works
are given in Section 4. Finally, conclusions are presented in Section 5.
2. Circuit description
2.1. Previous work
Fig. 1a shows our proposed two-stage amplifier in [9]. P-type
metal-oxide-semiconductor (PMOS) devices as input transistors
Fig. 1. High gain two-stage amplifiers: (a) Schematic of our previously reported two-stage amplifier in [9] and (b) Schematic of the proposed performance enhanced two-
stage amplifier.
Please cite this article as: A. Mesri, et al., Analysis and design of a two-stage amplifier with enhanced performance, Microelectron. J
(2015), http://dx.doi.org/10.1016/j.mejo.2015.10.002i
have less flicker noise than n-type metal-oxide-semiconductor
(NMOS) devices, and can be used with lower input CM levels. This
property helps to reduce clock feed-through mismatch of input
switches in SC circuits [1,13,14]. Using the cascode structure in the
second stage, not only increases the output resistance of the sec-
ond stage and the DC gain, but also reduces the Miller effect on
parasitic gate-drain capacitances of M5–M6. Moreover, nodes N3
and N4 in this structure can be used to switch MS  and MS þ ,
which increase the amplifier’s slew rate and settling speed.
In Fig. 1a, power consumption of the first stage is much higher
than that of the second stage. Also, channel lengths of the tran-
sistors of the first stage are shorter than those of the second stage.
For these reasons, the output resistance of the first stage is much
lower than that of the second stage. Hence, the non-dominant and
dominant poles (p2 and p1) occur at the outputs of the first and
second stages, respectively.
As shown in Fig. 1a, fully differential active loads have been
used at the output of both stages. The diode connected devices,
M3a, M4a, M9a and M10a, define the CM level conveniently. Also, the
cross-coupled devices, M3b, M4b, M9b and M10b, provide a large
resistance by means of the positive feedback they apply to the
output nodes.
By choosing the same sizes for NMOS devices in the first stage,
the equivalent resistance of each node will be r O3a =2 for
differential-mode (DM) operation and approximately 1/2gm3a for
CM operation [9]. Same sizes have been chosen for devices Ma and
Mb in the differential active loads to achieve lower parasitic
capacitance at output nodes and also better performance in the
presence of a mismatch. Because of high overdrive voltages of the
differential active load transistors, their transconductances are
quite low. So, they will be less prone to unstable operation [9].
It is worth to mention that no CMFB circuit is required when
this fully differential active load topology is used. In process cor-
ners, CM level of nodes N1 and N2 changes according to the
amount of threshold voltage variation of NMOS transistors of the
first stage. This causes the overdrive voltage of M5 and M6 to have
very small variations in different process corners. Hence, similar to
the bias current of the first stage (defined by Mt1), the bias current
of second stage will remain almost constant at different process
corners. As reported in [9], the specifications of the proposed
amplifier show low sensitivity to process variations, and the
amplifier shows better performance in comparison with other
works, such as [8,15].
 A. Mesri et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ 3

MS  and MS þ are used for slew rate enhancement. Their cur-

rent consumption in a quiescent condition is small. MS  turns on 1 1
for positive inputs and discharges CL (connected to  V od =2 ) faster.
2rOt Vdd Vdd
2gm9a 2gm9a
MS þ has the same role in node V od =2 for negative inputs. Con- Vout Vout
Ry M1 ix
necting MS  and MS þ to nodes N3 and N4 brings poles of the CL+C2 Cc
M7
cascode nodes to lower frequency and degrades the phase margin. Vx 0
However, this effect can be easily compensated by a small increase M5
1 Ry gm5 Vx 1
in the value of Cc.
2gm3a 2gm4a

2.2. Proposed structure Fig. 2. Equivalent half circuit for PSRR þ analysis: (a) Low frequency model and
(b) High frequency model.
Fig. 1b shows the performance enhanced two-stage amplifier.
The main differences to the circuit in Fig. 1a are the removing the
tail transistor, Mt2 in Fig. 1a, and the addition of resistors RC and V1 -Vod -V1 Vod
Rm. Using Mt2 in Fig. 1a, limits the maximum current of M5(M6) to
RC CC RC CC

g m1 (Vid )
the total bias current of Mt2 when node V od =2(  V od =2) is being
discharged for negative inputs (positive inputs). Removing Mt2 in R1 C1 g m5 (V1 ) R2 C2 CL
the new structure allows M5 and M6 to discharge the output nodes
by currents larger than that of the previous work, which improves
the slew rate and settling behavior of the amplifier.
RC is used to move the LHP zero close to the first non-dominant Fig. 3. Half circuit small-signal model of the amplifier.
pole, p2, to achieve pole–zero cancellation and improve phase
margin, similar to the method used in [8]. The combination of Rm noise effect on the output node can be expressed as:
connected to M3a (M4a) and M5(M6) constitutes a high speed !
R
current mirror. The compensation resistor Rm turns the first-order V out ¼ V dd    y   V dd ð3Þ
Ry þ 1=2g m9a
low pass current mirror to a second-order low pass with one zero
and two poles. However, with a proper choice of Rm, one of the According to the definition of PSRR þ , its value is very high at
poles may be canceled and a wider bandwidth be obtained [16]. low frequencies and approximately equals Ad. The equivalent
Recently in [15,17], high speed current mirrors are used to improve small-signal model to calculate PSRR þ at high frequencies is
the speed in amplifiers. depicted in Fig. 2b. Since the small-signal current that flows into
node VX is very small, VX and gm5VX are approximately zero and
2.3. Differential-mode and common-mode analysis negligible. Based on this assumption and also RC ¼Rm ¼ 0, the
dominant pole can be expressed as:
Since the slew-rate enhancement circuit (MS þ and MS  ) only P Vdd   2g m9a =ðC c þ C L þ C 2 Þ ð4Þ
slightly affects the small-signal performance, its effect will not be þ
considered in the following calculations. The DC gain of the Since the dominant pole of the Add is the zero of PSRR , for
frequencies higher than that calculated by (4), slope of the mag-
amplifier Fig. 1b for DM signals is given by:

r  nitude in PSRR þ transfer function will increase and leads to higher
Ad ¼ V od =V id ¼ g m1 
O3a
j j r O1  g m5 PSRR þ at high frequencies.
2

r     
O9a 2.5. Stability analysis
 j j r O7 þ r O5 1 þ g m7 þ g mb7 r O7 ð1Þ
2
Also, The DC gain of the amplifier Fig. 1b for CM signals can be High frequency performance of the proposed amplifier is
expressed as: investigated in this section. In addition, formulas and tips useful
  ! for design procedure are presented.
g m1  1=2g m3a   For moderate to high loads, the non-dominant pole of the
Acm     g m5 =2g m9a ð2Þ
1 þ 2r Ot =r O1 þ 2r Ot ðg m1 þ g mb1 Þ second stage, denoted as p3, occurs at frequencies much higher
than the GBW, so it is ignored in derivations for the systems’
The CMRR is defined as CMRR ¼Ad /Acm. The equivalent resis- transfer function. As will be explained later, if the capacitive load is
tance of the differential active loads for DM is rOa/2 and for CM is small, this pole must be taken into account to have a reasonable
approximately 1/2gma. Moreover, Mt acts as a degeneration resis- phase margin. Moreover, for Rm ¼0 the equivalent circuit of the
tor for CM signals and reduces the DC gain of the first stage. performance enhanced amplifier will be that of Fig. 3.
Therefore, the DC gain is much higher for DM signals than CM, R1 and C1 are the equivalent resistance and parasitic capaci-
which means a higher CMRR. tance at output of the first stage, respectively. R2 and C2 show
these parameters for the second stage [9].
2.4. Positive power supply rejection ratio (PSRR þ ) Writing KCL for the output node and node V1 gives:



V od =V id ¼ Ad 1 þ a0 S þ a1 S2 = 1 þ a2 S þa3 S2 þ a4 S3 þ a5 S4 ð5Þ
PSRR þ is defined as Ad/Add, where Ad is the differential gain and
Add is gain of a noise signal from the positive supply rail to the where Ad is the DM mode DC gain and is given by (1). Also:
output. Fig. 2a is used to evaluate the effect of power supply vol-   
tage variation on the output node. The voltage source Vdd models a0 ¼ RC C C 2 þ 1=RC g m5 ð6Þ
the power supply variation, or power supply noise.   
Since the impedance connected to the source of M1 (2rOt) is a1 ¼ ðRC C C Þ2 1 þ 1=RC g m5 ð7Þ
very high, the gain from the supply to the amplifier output from   
the first stage path is very small. In the second stage, the supply a2 ¼ R2 C 2 þ C L þ C C 1  g m5 R1 þ R1 ðC 1 þ C C Þ þ2RC C C ð8Þ

Please cite this article as: A. Mesri, et al., Analysis and design of a two-stage amplifier with enhanced performance, Microelectron. J
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a3 ¼ RC C C ðR1 C 1 þ R2 ðC 2 þ C L ÞÞ þ ðRC C C þ R1 ðC 1 þC C ÞÞðRC C C By using the half circuit model of the amplifier in Fig. 4a, p3 can
þ R2 ðC 2 þC L þ C C ÞÞ be expressed as:
  " ! #!
 R1 R2 C 2 C 1 þ g m5 RC ð9Þ r þZ
p3 ¼  1=C 3  O7  j j ðr O5 Þ ð17Þ
1 þ g m7 þ g mb7 r O7
a4 ¼ RC C C ½R2 ðC L þ C 2 ÞðRC C C þ R1 ðC 1 þ C C ÞÞ þ R1 C 1 ðRC C C
where C3 is the parasitic capacitance at the cascode node X. Since
þ R2 ðC L þ C 2 þ C C ÞÞ ð10Þ
at GBW frequency, output nodes are bypassed to ground by output
capacitances, p3 can be expressed as:
a5 ¼ ðRC C C Þ2 ðR1 C 1 R2 ðC 2 þ C L ÞÞ ð11Þ   
1 g þg mb7
The transfer function has four poles and two zeros, all in the p3   1=C 3 j j r O7 j j r O5   m7 ð18Þ
g m7 þ g mb7 C3
LHP. In [9], for RC ¼0 and the above assumptions, there were two
poles and one zero, and all occur below the GBW frequency. It is Fig. 4b shows the equivalent half circuit model at GBW fre-
expected that the dominant pole of the improved structure follow quency. Based on this model, C3 is equal to:
the derivation in [9], which is: C 3 ¼ 2C gd5 þC db5 þ C sb7 þ C gs7 þ C gsS  þ C gdS  ð19Þ
  
p1   1=α2   1=R2 C 2 þ C L þ C C 1  g m5 R1 ð12Þ Note that the coefficient 2 in the first term is due to the miller
effect on Cgd5. By substituting (13) and (18) into (15), value of the
This is because in frequencies close to the dominant pole,
capacitive load for a given phase margin can be calculated as:
impedance of CC is much higher than RC. Consequently, assuming
RC ¼0 in (12) is fairly safe. Note that Rm has no effect on the A1 g m5 g þg mb7
  ¼ m7 tan θ ð20Þ
dominant pole frequency. Including Rm in the transfer function C 2 þ C L þ C C 1  g m5 R1 C3
complicates the formulas and the results make no sense about the  
circuit performance. Therefore RC and Rm should be optimized for A1 g m5 g 1þη
  ¼ m7 tan θ ð21Þ
the best performance using computer simulations. Regarding the C 2 þ C L þ C C 1  g m5 R1 C3
best performance, it means the situation in which the LHP zero
where η is g mb7 =g m7 . Since g m5 ¼ g m7 , the required CL for a given
introduced by RC and CC cancels p2 (output pole of the first stage),
phase margin can be expressed as:
and the amplifier works like a single pole system with the domi-
nant pole given in (12). A1   A1
CL ¼   C 3 þ g m5 R1  1 C C  C 2    C3 ð22Þ
It is important to note that since GBW frequency increases for 1 þ η tan θ 1 þ η tan θ
smaller capacitive loads, effect of the non-dominant pole of the
For example, to have PM ¼60°, θ must be 30°, i.e. GBW ¼
second stage (p3) cannot be ignored in amplifier’s transfer func-
0.577p3. For this case the minimum CL is given by:
tion. Therefore, to achieve a reasonable phase margin for smaller pffiffiffi
loads, effect of p3 should be considered. Based on the location of p3 3A1
CL   C 3 ð23Þ
and GBW frequency, a minimum required capacitive load for a 1þη
desired phase margin can be calculated. Assuming zLHP ¼p2, GBW
For loads larger than what (22) suggests, the amplifier works
frequency can be expressed as:
like a single pole system and becomes more stable for larger
A1 g m5 values of CL.
GBW  Adc  p1    ð13Þ
C 2 þ C L þ C C 1  g m5 R1 It is instructive to compare the proposed amplifier with a
telescopic amplifier. It can be shown that in a telescopic amplifier
where A1 ¼ g m1 R1 . For the worst case, i.e. unity gain configuration,
GBW and the minimum CL can be calculated as:
and Assuming zLHP Ep2, phase margin of the amplifier is given by:
  g m1
GBW GBW  Adc  pout  ð24Þ
PM ¼ 1801  901  tan  1 ð14Þ C Pout þ C L
p3
1
where the second and third terms account for effects of p1 and p3 CL    CP ð25Þ
1 þ η tan θ
at GBW frequency, respectively. If p3 introduces the phase shift  θ
° at GBW, then GBW can be calculated as: where CPout, CP and θ are the parasitic capacitance at the output
node, parasitic capacitance of the node associated with the cas-
GBW ¼ p3 tan θ ð15Þ
code pole and the phase shift introduced by the cascode pole at
Fig. 4a is used to obtain p3, where Z is: GBW frequency, respectively.
    For the comparison, assume that the power consumption of the
Z ¼ r O9a =2 j j 1=ðC 2 þ C L ÞS ð16Þ
telescopic amplifier is equal to that of the second stage of the
proposed work. This way, including the first stage, power con-
sumption of the proposed amplifier is 8.5 times higher than that of
the telescopic amplifier. Also, since the first stage has a gain of 39
Z +Vid Z +Vid (A1 ¼39), the proposed amplifier has 39 times higher gain, but
+Vod M1 M1 requires 39 times higher minimum load for a given phase margin.
2 2 2
However, according to (22) and (25), and for an equal load, the
-Vod proposed amplifier has 39 times higher GBW. This is an expected
2 M7 M7
result. Because gain of the first and second stage simply add
M S- X MS- X
together (in logarithm), and raise the magnitude of the transfer
M5 M5
rO3a rO3a function in a Bode plot. If the first stage does not add any poles or
2 2 zeros to the system below the GBW frequency of the overall
amplifier, shape of the magnitude plot does not change below the
Fig. 4. Half circuit small-signal model of the second stage: (a) At frequencies much GBW frequency, and the GBW will be proportionally increased too,
lower than p3 and (b) At frequencies near p3. see Fig. 5. This condition is only met if the zero introduced by the

Please cite this article as: A. Mesri, et al., Analysis and design of a two-stage amplifier with enhanced performance, Microelectron. J
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 A. Mesri et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
Gain(dB)
20 log (A1A2)
A1 GBW A1GBW
20 log (A2) A1
20 log (A1)
p3
Log(ω)
p1
p2, zLHP
Fig.5. Magnitudes of the transfer functions of the first and second stages of the
proposed amplifier, and also the overall amplifier for zLHP E p2.
Fig. 6. Layout of the proposed amplifier.
compensation network cancels the output pole of the first stage,
which is feasible by proper choice of RC and CC.
To increase the gain of a telescopic amplifier by 39 times,
channel lengths of transistors should be considerably increased.
Therefore CP, the minimum load and the required area will be
considerably increased. Note that in this case, the GBW is at least
39 times less than that of the proposed work, since CP is increased.
Moreover, in telescopic amplifiers, it is hard to keep the tran-
sistors in saturation when the input is connected to the output in
applications like unity gain amplifiers. Consequently, folded cas-
code amplifiers are used for such applications [14,18]. (25) can be
used to obtain the minimum load capacitance in folded cascode
amplifiers. However, Cp will be large in these amplifiers, since Cdb
and Cgd of the input transistors are also included. Therefore, the
minimum load for a given phase margin increases, which
decreases the GBW compared to a telescopic amplifier. In addition,
the proposed amplifier has lower offset voltage, compared to the
recycling folded cascode amplifier proposed in [13]. Based on
these reasons, the proposed amplifier is a good choice in modern
technologies
Please cite this article as: A. Mesri, et al., Analysis and design of a two-stage amplifier with enhanced performance, Microelectron. J
(2015), http://dx.doi.org/10.1016/j.mejo.2015.10.002i
5
Table 1
Device sizes of the proposed amplifier.
Devices W/L ( lm/lm)
M1, M2 200/0.18
M3a, M4a, M3b, M4b 10/0.5
M5, M6 4/1
M7, M8 4/1
M9a, M10a, M9b, M10b 6/4
Mt1 500/0.18
MS þ , MS- 36/0.18
Fig. 7. Frequency response of the proposed two-stage amplifier: (a) Gain and
bandwidth and (b) Phase characteristics of the amplifier.
when high gain along with reasonable power consumption,
area, speed and also stability under large loads are desired.
As mentioned before, for small capacitive loads, phase margin
of the proposed amplifier depends on the location of p3 and
consequently sizes of the slew rate enhancement transistors.
Therefore, based on the load value, sizes of these transistors can be
chosen to meet the desired slew rate and phase margin.
3. Simulation results
All of the simulations presented in this article have been per-
formed in HSpice using level 49 models with parameters of a
0.18 um CMOS process with 1.8 V power supply voltage. The layout
of the proposed amplifier shown in Fig. 6 was prepared in a
0.18 μm CMOS process which has an area of 2597 μm2. The pro-
posed amplifier works with a 1.8 V supply voltage and consumes
0.896 mW power of which, 0.802 mW is consumed by the first
stage, and the rest by the second stage. Also, Values of Cc, Rc and
Rm are 0.5 pF, 1.8 kΩ and 12 kΩ, respectively. Table 1 summarizes
component sizes of the proposed two-stage amplifier.
Fig. 7 shows the frequency response for CL ¼10 pF. Open loop
DC gain, phase margin and GBW are 79.5 dB, 66.9° and 93.6 MHz,
respectively. The contributions of the first and second stages to the
open loop DC gain are 31.8 and 47.7 dB, respectively.
Pole-zero pairs (doublets) can affect frequency response and
settling time of amplifiers. In [10,11] it is shown that reducing the
doublet spacing can reduce the settling time. Adding RC in this
proposed work, reduces the space between the compensation zero
and the output pole of the first stage as compared to our previous
work in [9], hence reduces the settling time.
PSRR þ at low frequency and at GBW is 80.4 and 27.1 dB,
respectively. Also, CMRR at low frequency and at GBW is 101
and 35.3 dB, respectively. The  3 dB bandwidth of PSRR þ is
6 A. Mesri et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎

Fig. 8. Variation of CMRR and PSRR þ with output swing: (a) At low frequencies
and (b) At GBW frequency.

Table 2
Effect of CL on some of the performance of the amplifier specification.

CL, pF GBW (MHz) PM (deg.) CMRR at GBW (dB) PSRR þ at GBW (dB)

25 43.6 71.2 41.8 37.6

50 24.4 75.6 47.4 42.6
75 17.1 78.8 50.5 42.3
100 13.1 81 52.8 41.9

Table 3
Corner simulations of the proposed amplifier.

Process corners AV (dB) GBW (MHz) PM (deg.)

TT 79.5 93.6 66.9

FF 75.1 104.5 73.5
FS 78.2 88.6 66.9
SF 80.4 96.1 68.3
SS 83.9 80.5 64.8

Fig. 10. Differential unity gain sampler and its Monte Carlo simulation result:
(a) Differential unity gain sampler in Sampling mode (CK¼ VDD) and (b) Monte
Carlo simulation results.

14.7 kHz which is higher than that of the Miller compensated

amplifiers [12].
It is worth to mention that the differential active loads show
Fig. 9. Input referred noise as a function of frequency. lower impedance for common mode signals than differential mode

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Table 4 Table 5
Mismatch effect in different process corners. Amplifier characteristic results.

Process corners GBW (MHz) PM (deg.) Description Previous work [9] This work

Min Nominal Max Min Nominal Max Technology (μm) 0.18

Supply (V) 1.8
TT 82.6 93.6 104 61 66.9 71 Capacitive load (pF) 10
FF 91.4 104.5 116 66.1 73.5 80.1 Power consumption (mW) 0.86 0.896
FS 79 88.6 98 60.2 66.9 72.1 DC gain (dB) 82.7 79.5
SF 84.5 96.1 108 62.7 68.3 71.9 Compensation capacitor (pF) 0.75 0.5
SS 72 80.5 89.1 59.1 64.8 68.3 GBW (MHz) 53.8 93.6
PM (deg.) 61.7 66.9
slew rate (V/μs) 5.63 18.2
Area (mm2) 3038.5 2597
maximum input offset (mV) 3.2 3.42
Vinp–p ¼ 0.5 V 1% settling time (ns) 93.4 31.2
0.1% settling time (ns) 102 47.3
PSRR þ (dB) Fin ¼5 KHz 83.2 80.4
Fin ¼GBW 29.1 27.1
CMRR (dB) Fin ¼5 KHz 127 101
Fin ¼GBW 31 35.3
Input noise (nV/Hz1/2) Fin ¼10 KHz 39.9 39.8
Fin ¼1 MHz 4.67 6.64

Table 2 presents effect of CL on some of the amplifier specifi-

Fig. 11. Step response of the amplifier for CL ¼ 10 pF: (a) Unity gain configuration
and (b) Step response of amplifier in Figs. 1a [9] and 1b.
ones. This has resulted in 55.68 and 77.2 dB improvements in PSRR
and CMRR respectively, when compared to the case of using
conventional active loads. In [19] a current source has been pro-
posed which employs an internal feedback to increase the output
impedance, which results in a high CMRR. Also subregulated
biasing source is used to improve PSRR by 20 dB. Therefore, the
differential active load and the proposed method in [19] can be
used together if even higher CMRR and PSRR are required.
The values reported for PSRR þ and CMRR are obtained for
single ended output, and obviously will be infinite for differential
output, due to the symmetry of the structure. However, when a
differential input is applied, the symmetry no longer exists when
the circuit is viewed from the output nodes’ point of view. Con-
sequently, differential CMRR and PSRR þ both are functions of the
output swings. Fig. 8 shows differential CMRR and PSRR þ for
different values of the output. It can be seen that when the output
swing increases, the differential CMRR and PSRR þ decrease. This is
a result of the reduction of the circuit’s symmetry.
cations. As seen in Table 2, phase margin, CMRR and PSRR þ
improve at large capacitive loads.
Table 3 lists simulations results of the proposed amplifier at
different process corners for CL ¼10 pF. The largest variation of
GBW is at SS corner, where GBW is decreased by 14%. This is
significantly smaller than the reported value in [8], where the
GBW of the amplifier is decreased by 49.5% in FS corner. It seems
that the main reason for such large variation in [8], is variation of
the bias current of the second stage at different process corners. In
our design, the adopted active load topology alleviates this pro-
blem by decreasing variation of the bias current of the second
stage at different process corners.
Fig. 9 shows the input referred noise as a function of frequency.
Input referred noise of the amplifier at 10 KHz and at 1 MHz is 39.8
and 6.64 nV/Hz1/2, respectively.
To investigate performance of the proposed amplifier in the
presence of a mismatch, Monte Carlo analysis has been performed.
Modeling and simulation of mismatch are done similar to [9]. Note
that in [9] and also in this paper, the standard deviation of the
threshold voltage of devices, σvt, are considered higher than values
reported for 0.18 mm CMOS process [9].
Monte Carlo analysis results of the proposed amplifier are listed
in Table 4 for 10 pF capacitive load. It is worth to mention that the
largest variation in the open loop DC gain occurs at TT corner and
is equal to þ2.8 dB. Also, the highest open loop DC gain occurs at
SS corner and is 86.5 dB. Moreover, the lowest open loop DC gain
occurs at FF corner and is 72.8 dB. Finally, the largest input refer-
red offset voltage is associated with FS corner and is 3.42 mV.
Also, offset drift of the proposed amplifier is less than 1μV = 1C.
Fig. 10 shows the proposed amplifier in a differential unity gain
sampler configuration with its simulation results in the presence
of a mismatch, supply noise and input CM noise. The peak to peak
noise amplitude for the power supply and input CM level are 10%
of supply voltage (VDD), which is 180 mV. Fig. 10a shows the circuit
in sampling and offset cancellation mode where CK ¼VDD and
switches S1–S4 are closed [14]. The circuit works in amplification
mode if CK¼ 0 and S5–S6 are closed and other switches are open.
As depicted in Fig. 10b, the DC offset for 30 Monte Carlo runs is
around 71.35 V, which is canceled before applying the input.
After offset cancellation, input is amplified with 0.1% accuracy, and
maximum and minimum settling times at different runs in the
presence of a mismatch, supply noise and input CM noise are 62.7
and 46.1 ns respectively for CL ¼ 10 pF and C ¼1 pF.

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Table 6
Performance comparison with other works.

Parameter [8] Measured [19] Measured [20] Measured [21] Measured [9] Simulated This work Simulated

Technology (mm) 0.065 0.5 0.065 0.13 0.18 0.18

Supply (V) 1.2 12 1 1 1.8 1.8
CLoad (pF) 1 20 2 5.5 10 10
Power (mW) 0.75 48 1.6 0.11 0.86 0.896
DC Gain (dB) 442 120 56.1 70 82.7 79.5
GBW (MHz) 780 25 450 35 53.8 93.6
Phase Margin (deg.) 60 N/A 77 45 61.7 66.9
Area (mm2) 3240 N/A 1800 12351 3038.5 2597
1% settling (ns) at Vinpp (V) N/A N/A 10@ 0.5 134@0.1 39.7@ 0.18 14.8@ 0.18
178@ 0.9 58.7@ 0.9
SR (V/ms) 254 30 N/A 19.5 5.63 18.2

As simulation results show, the proposed amplifier has a good
performance in the presence of mismatch, supply noise and input
CM noise. Note that for the sake of safety, the standard deviation of
the threshold voltage used in simulations is chosen to be larger
than those reported in the literature.
As shown in Fig. 11a, the proposed amplifier is used in a unity
gain configuration, where C ¼ 1 pF, R¼5 Meg and CL ¼ 10 pF.
Fig. 11b shows the step response of the proposed amplifier and our
previous work in a unity gain configuration for a 1.8 Vp–p input
swing. Note that in Fig. 1b, the slew rate enhancement circuit
(MS þ and MS  ) increases the slew rate of the amplifier from
5.85 V/ms to 18.2 V/ms for CL ¼10 pF.
To investigate linearity of the proposed amplifier, it is used in a
unity gain configuration with a 500 kHz, 1.8 Vp–p sinusoidal input
voltage. The lowest linearity occurs at FF corner, and is 55.52 dB.
Also, for 1 Vp–p, the lowest linearity occurs at SS corner, and is
75.6 dB.
Although gain of the proposed amplifier in this paper is 3.2 dB
lower than that of our previous work in [9], but simulations show
that it has 1.63 dB better linearity for a 1.8 Vp–p signal.
Table 5 shows the overall results for the proposed amplifier in
this paper and also our previous work in [9], for 10 pF load
capacitance.
4. Comparison
A comparison between the proposed amplifier and some of
other published works is provided in Table 6. The output swings
are half and 0.1 times of the supply voltage in [20,21], respectively.
Therefore, the data in Table 6 are provided for both cases of the
output swing being 0.9 and 0.18 V. The two-stage amplifiers
reported in [20,21], similar to conventional Miller compensated
amplifiers, become unstable if the capacitive load is increased. In
[8], resistive-capacitive negative and positive feedbacks are used
simultaneously to achieve a load insensitive two-stage amplifier.
However, similar to single-stage amplifiers, this topology has a
small DC gain. The reported amplifier in [19] provides higher DC
gain, PSRR, CMRR and also slew rate, but its power consumption is
much higher than those of other works. The proposed amplifier in
this work, not only provides significantly higher DC gain, but also
becomes more stable if the capacitive load is increased. It can be
seen that the proposed two-stage amplifier achieves 74% higher
GBW, 14.5% smaller area and 3.23 times higher slew rate than our
previously reported work in [9], at the cost of only 4.18% higher
power consumption.
5. Conclusions
Design and analysis of a performance enhanced high gain two-
stage amplifier have been presented in this paper. The effect of the
first stage output pole is considerably reduced by applying a PRCF
around the second stage. Using the PRCF compensation allows to
design the LHP zero closer to the output pole of the first stage,
hence reduce the effect of the pole-zero doublet on the settling
behavior of the amplifier. Moreover, the proposed two-stage
amplifier is robust against process variations, and large supply
and CM input noise, and also provides higher CMRR and PSRR þ at
high frequencies close to GBW. Finally, simple structure, high lin-
earity, small area, low offset and robustness against process var-
iations and device mismatch are other advantages of the proposed
amplifier.
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(2015), http://dx.doi.org/10.1016/j.mejo.2015.10.002i
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Please cite this article as: A. Mesri, et al., Analysis and design of a two-stage amplifier with enhanced performance, Microelectron. J
(2015), http://dx.doi.org/10.1016/j.mejo.2015.10.002i