Traditional ASICDesignFlow

• Pre Layout Timing/STA Simulation:

• Two types of Timing Delays:
• Cell delay (input to output of a cell)
• Propagation delay (output of cell1 to input of cell2).
• Delays are specified as min,max,typ depending on PVT
(Process,Voltage,Temperature) condition.
• Wireload models are used to estimate propagation delay based on fanoutsbecause
at this stage Layout is not done.
• Setup violations must be addressed to Pipelining , Register retiming (balancing
combinational logic)
• Hold violations can be ignored at thisstage.
• Post Layout Timing/STA Simulation:
• Back Annotated SDFwith post-layout netlist is simulated at min,typ and maxcondition.
• All interface timing (ex: ROM/RAM access timing , PCIbus timing etc.) should be modeled as
Bus Functional Model (BFM).
• The simulation should be free from all Setup & Holdviolation.
• Whenever data is crossing clock domain , metastable conditions should be checked.
• Floor Planning:
• Floor Planning is a mapping between the logical description (hierarchical netlist) andthe
physical description (the floor plan).
• The goals of Floor Plan are:
• Arrange the blocks on achip.
• Decide the location of the I/Opads.
• Decide the location and number of the powerpads.
• To minimize the chip area anddelay.

• Placement:
• Placement is arranging all the logic cells withinthe flexible blocks on a chip.
• Objectives of Placement:
• Guarantee the router can complete the routing step
• Minimize all critical net delays
• Make the chip as dense as possible
• Clock Tree Synthesis (CTS):
• Clock Tree is defined by its start point (source) and endpoint(sink).
• During CTS, delay and skew from source to sink are optimized.

• Back Annotation & RCExtraction

• Delays are extracted from physical & RC information in SDF(Standard DelayFormat).
• Back Annotated SDFfile is used during post layout timing simulation andSTA.
Routing
• Routing is done in 2steps:
• Global Routing:
• Plans channels for routing between blocks . Its goalsare---
• Minimize the total interconnectlength.
• Maximize the probability that the detailed router can complete therouting.
• Minimize the critical pathdelay.

• Detailed Routing:
• Complete all the connections between logiccells.
• Exact location and layers for each interconnect aredetermined.
Mixed Signal ASIC
• Digital + Analog Blocks
• Analog Blocks : ADC, DAC, Amplifiers, Modulators & Demodulators
etc..
Mixed Signal ASICDesignFlow
Proto ASICTesting
Source of Problems
• Design Problems:
• Logic design incorrect.
• Physical design incorrect.
• Manufacturing Problems:
• Processing faults:
• Missing contact windows.
• Parasitic transistors.
• Material defects:
• Bulk defects (cracks, crystal imperfections etc.)
• Surface impurities.
• Electrical defects:
• Shorts (Bridging faults)
• Opens
• Transistor Stuck-On/Open
• Logical defects:
• Logical stuck-at-0/1
• Slow transitions.
• Defects: Imperfection or flaw that occurs withinsilicon.
• Faults: Representation of a defect.
• Failures: Non-Performance of the intended function of thesystem.
• Error: The manifestation of Failure.
• Examples:
• A Physical short is considered as a defect.
• A Physical short resulting in stuck-at behavior might be modeled as astuck-at-
1/0 fault.
• Non-performance of the system due toerror is failure.
Design Levels from Testability Perspective
Importance of Testing
• According to Moore’s law , featuresize is decreasing.
• Defects are unavoidable.
• Testing is required to guarantee fault-freechips.
• Product quality depends on the followingparameters:
• Test cost
• Test quality
• Test time
• To IncreaseProductivity:
• Shorter time-to-market
• Reduced design cycle
• Reduced cost
• ToImprove Quality:
• Reduced Defects per Million (DPM)
• Improved quality of test.
Testability
• The ability to put a design into a known initial state, and thencontrol
and observe internal signal values.
• DFTrefers hardware design styles , or added hardware that reduces
test generation.
• Test generation complexity increases exponentially with the sizeof
the circuit.
• Two basic properties determine the testability of a node:
• Controllability:
• The ability to set node to a specific value through primary input.
• Observability:
• The ability toobserve the node’s value from primary output.
 Scenario of Manufacturing Test
Test Vectors

Manufactured
circuits

Circuit Responses

Correct Responses Comparator Pass/Fail

Functional VsStructural Testing
• Functional Test:
• Generates complete set of tests for circuit input-output combinations. Example: 64-bit ripple carryadder

1/0 stuck-atfaults.

▪ 129 inputs , 65 outputs

▪ 2**129 patterns.
▪ Using 1GHz ATE, would take 2.15x10**22 years.
• Structural Test:
• #redundant adder hardware , 64-bit slices.
• Each with 27 faults (using faultequivalence)
• At most 64x27=1728(faults/tests).
• Takes 0.000001728 seconds on 1 GHzATE.
• Sofrom the above example , it is difficult to test even 64-bit adder as it takes lot of time. That is the reason to check manufacturing defects we use
small/few test vectors which drastically reduces time.
• Test generation for sequential circuits are even more difficult due to the lack of controllability & observability atflip-flops.
Quality of ChipsMeasurement
• Fraction (%ge) of good chips produced in a manufacturing process is
called YIELD. It is denoted by “Y”.
Cost of a chip = (Cost of fabricating and testing a wafer) / (Yield) * (Number of Chips in wafer)

• DEFECTLEVEL(DL) is the ratio of faulty chips among the chips that

pass tests. It is measured in PPM (Parts Per Million). DLis a measure
of the manufacturing quality.
DL< 500ppm is considered as high quality as seen fault coverage~99%.
Measurement::
DLor RR(Reject Ratio) = 1-Y**(1-d) where d is Test Coverage.
Design Approaches:
• Top-Down Approach:
• Targets the complete design for scan , test synthesis andATPG.
• Advantages:
• No or little manualeffort.
• Automatic scan chain balancing.
• Lockup latches and other logic related tointerconnect between modules handled automatically.
• Disadvantages:
• Difficult todebug testability issues for large designs.
• Need entire design.
• Bottom-Up Approach:
• Scan , test injection , and ATPG one block at a time , combine blocks at top.
• Advantages:
• Divide and conquer complex design.
• DFTwork and DRCdebug can start easily.
• Design change on a block affects DFTonly on that block.
• Works well with designteams.
• Disadvantages:
• Top-level connectivity and chain balancing becomesdifficult.
• ATPG must be re-done at toplevel.
• DRCcannot detect inter-block problemseasily.
• May introduce redundant testlogic,
DFTTechniques:
• Adhoc Techniques:
• Is a temporary technique
• Minimizing redundant logic.
• Minimizing asynchronous logic.
• Isolating clocks from logic.
• Is a strategy to enhance the design testability without making much change to
design style.
• Good Design Practices are used as guidelines for ad-hoc techniques.
• Structural Techniques:
• It provides more systematic & automatic approach to enhance the design
testability.
• Targets manufacturing defects.
• Most common method is scandesign.
• Type of ScanChains
• Full-Scan

• Partial-Scan

• Partition-Scan
Scan & Scan Architectures
Scan Groups
Scan Architectures
• Three Types: Mux-DFF , Clocked Scan , Level Sensitive Scan Design

• Mux_DFF:

• Application: Typically used with edge-triggered designstyles.

• Advantages: simplest and most widely usedmethod.
• Disadvantages: Additional delay caused by the multiplexor in the functional
path. Hold-time &clock skew problems can occur on the scan path because of
a short path from a scan cell’s scan-output pin to the next scan cell’s scan-
input pin.
Scan Architecture (contd…)
• Clocked Scan:

• Application: Typically used with edge-triggered design styles. Well suitedto

use in partial-scan designs.
• Advantages: Low area overhead.
• Disadvantages: Hold-time or clock-skew problems can occur on the scan path
because of a short path from a scan cell’s scan-output pin to the next scan
cell’s scan-input pin. Requires the routing of two edge-triggered clocks.
Scan Architecture (contd…)
• Level Sensitive Scan Design (LSSD):

• Application: Typically used for designs that are predominantly level-sensitive.

Well suited to partial-scan designs because of the test clocks.
• Disadvantages: Replacing a simple latch with an LSSDcell can increase
sequential logic area by 100% or more because the new cell adds a slave
latch. Adding the master and slave test clocks also increases the routing area
overhead.
 DFT/ATPG

ATPGConsists of two mainsteps:

• Generate Patterns
• Performing fault simulation to determine which faults the patterns detect.
Common Fault Terminology
• Fault Equivalence
• Fault Dominance
• Fault Collapsing
• Fault Grading (Vector Grading)
• Fault Masking
• Fault Equivalence:
• Two faults f1 & f2 are said to be equivalent in a circuit , if the function under
f1 is equal to the function under f2 for any input combination (sequence) of
the circuit.
• No test can distinguish between f1 & f2.
• In other words , test-set(f1)=test-set(f2)
• Example:
• AND gate : all s-a-0 faults are equivalent.
• ORgate: all s-a-1 faults areequivalent
• NAND gate : all the inputs s-a-0 faults and the output s-a-1 faults are equivalent.
• NORgate : all the inputs s-a-1 faults and the output s-a-0 faults are equivalent.
• Inverter :
• input s-a-1 and output s-a-0 are equivalent.
• Input s-a-0 and output s-a-1 areequivalent.
• Fault Dominance:
• Dominance Relation:
• f1 fault is said todominate another fault.
• f1 is an irredundant circuit , if every test (sequence) for f1 is also a test (sequence) for f2
i.e. test-set(f2) >test-set(f1)
• No need to consider fault f2 for fault detection.
• Example Here:

• AND gate : output s-a-1 dominates any input s-a-1

• NAND gate : output s-a-0 dominates any input s-a-1
• ORgate : output s-a-0 dominates any inputs-a-0
• NORgate: output s-a-1 dominates any input s-a-0
• Fault Collapsing:
• Reducing the set of faults to test for by using equivalence classes is called fault collapsing.
• If a set of faults is functionally equivalent , we only need to use one test to detect any single one of
them.
• Note that a test that detects functionally equivalent faults cannot diagnose which faultis present.
• Simple example: 2-input NAND-gate
• Input s-a-0 is equivalent to output s-a-1 -> collapse it!!

• Fault Grading:
• The act of simulating a target vector against a good circuit description that contains afault.
• The goal being to see if the expected response is different between the two circuits at an
observable point.
• If a difference is detected, then the fault has beendetected.
• If a difference not detected , then the fault is masked for that vector (not detected).
• Fault Masking:
• The fault that is not able to be detected due to a circuit configuration problem such as
redundancy.
• An exercised fault can not be driven uniquely to an observepoint.
• This kind of faults needs to be masked.
ATPG Methods to detect a fault
• Based on Truth Table
• Based on Boolean Equations
• Based on Structural Analysis
• D-algorithm
• 9-valued D-algorithm
• PODEM (Path Oriented DecisionMaking)
• FAN (Fanout Oriented)
Fault Models
• Mathematical model of faulty behavior.
• Can be used to assess the compliance of a circuit to variouscriteria.
For example:
-- Structural compliance can be verified by using a Stuck-at Faultmodel.
-- Timing compliance can be verified by using a Delay Fault model.
-- Current Leakage compliance can be verified by using a IDDQ Fault model.
• Identifies target faults.
• Models faults which are most likely to occur.

❖Fault Modeling is the translation of physical defects into

mathematical representation which works upon algorithmically.
Fault Models (contd..)
• The fault models which industries arefollowing:
• Stuck-at fault model.
• Transition fault model.
• Path-delay fault model.
• IDDQ fault model.
• Bridging fault model.

➢ Stuck-at Fault Model (SAF) :: The node is modeled to be stuck-at some value 0 or 1 depending on what we are
targeting.
➢ Transition Fault Model (TDF) :: This is considered to be SAFwithin a time window. The value of the node
changes but not within time , at which it should change. For detecting such faults , we have 2 vectors for each
pattern ; one for launching the fault and other to capture the fault. This fault is also known asAt-Speed Test
Fault Model.
➢ Path Delay Fault Model (PDF) :: In this fault model, instead of concentrating on a single gate of the netlist , we
generally are concerned with a collection of gates which forms a valid path in the design.
➢ IDDQ Fault Model (IDDQ) :: This is similar to SAFbut instead of measuring voltage , we measure current. In a
CMOS circuits , the ideal value of the quiescent state (Q-state) is zero but there will be some current that
is because of shorted to ground or power which should not be.
➢ Bridging Fault Model (BFM) :: In this case , two close lying net may effect the value of each other, As per Spec ,
we may select some net which have coupling capacitance more than specified values , then these become the
fault locations for the ATPGto detect the fault.
Stuck-At Fault Model
• Assumptions:
• Only one test is faulty
• Faulty line permanently set to 0 or 1
• Fault can be at an input or output of a gate.
Some Quizzes to detect patterns for SAF
• To detect a SAFon a target node:
• Control the node to the opposite value of the Stuck-At value by applying the
data at the primary inputs.
• Make the node’s fault effect observable by controlling the value at all other
nodes affecting the output response , so the targeted node is the active
controlling node.
• The set of logic 0 & 1 is applied to the primary inputs of a design is called the
“input stimulus”. The resulting values at the outputs , assuming the fault-free
design is called “expected response”. The actual values measured by the
primary outputs are called the “output response”. If the output response does
not match the expected response for a given input stimulus , the input
stimulus has detected the fault.
Summary :: Afault can be detected if it is activated & propagated.
• #1.

• #2.
• #3.

• #4.
• #5.

• #6.
Scan Chain Operation
• Scan is a method to make circuit easily testable andaccessible.
• Scan allows to have controllability &observability for FFs.
• It tests combinational circuits using sequential logic.
• With scan , All FFs will form a chain like a shift register.
• With scan , a synchronous sequential circuit works in two modes: Normal
mode and Test mode.
• Steps for Scan Chain Operation:
• Setup the scan chain configuration.
• Shift values into the active scan chains.
• Exit the scan configuration.
• Apply stimulus to the test circuit inputs and measure the outputs.
• Pulse clocks to capture the test circuit response inflip-flops.
• Setup the scan chain configuration.
• Shift values out of the activescan chains.
• Exit the scan configuration.
Scan Chain Operation(contd..)
Delay Faults
• There are 2 types of delay faults:
• Transition Delay Fault (TDF): Models slow-to-rise(STR) and slow-to-fall(STF)
transition on logic gate.
• Path Delay Fault (PDF): Models slow-to-rise (STR) and slow-to-fall (STF)
transition on some path(s) from primary input to primary output.
• Delay Faults requires 2 patterns:
• Two patterns :
• Initialization Pattern (P1) – place initial value at fault site.
• Propagation Pattern (P2) – place the final value and propagate to theobservable fault.
• Delay of all paths through faulty gate exceed specified cycle time. Hence delay
faults reported for this.

• For details of operation , please see the link.

Scan Chain Operation(contd…)
• Two methods of TDF:
• Launch on Capture (LOC).
• Launch on Shift (LOS).
Path Delay Faults (PDF)
• Distributed delay in combinational path
• Propagation delays of all paths in a circuit must be less than one
clock cycle.
• Rising and failing transitions.
• Critical paths from STA(Static TimingAnalysis).
• Robust Path Delay Testing:
• This test guarantees the detection of a delay fault in target path , irrespective of the delay faults on any
other paths.

• Non-Robust Path Delay Testing:

• This test guarantees to detect a path delay fault , when no other path delay fault is present.
PDFTest(contd..)
IDDQ Fault Model
• This is similar to the stuck at fault model but here instead of measuring the
voltage we measure the current in a CMOS design at the quiescent state.

• Ideally there is suppose to low leakage current in the silicon at steady state
But large amount of leakage current flows from VDD to GND in faulty
devices due to manufacturing defects. Quiescent current from VDD to VSS
is shown in Fig.
 Bridging Fault model
• Unintended short between two signal and creates wiredlogic
• Shorts within logic gate are not bridgingfaults
• Fault Classes:
• Testable:
• Detected: A test pattern can be generated to control & observe thefailure
• Untestable: No test pattern can be generated to control & observe the fault.
• Abandoned: Test Compiler has reached its CPUlimit and has not found the pattern.
• Tied: The node is tied low or high , leading to controllabilityproblems.
• Redundant: The design contains redundant logic.
• ATPG_Untestable: This includes all faults for which the test generator is unable to find a
pattern to create a test, and yet cannot prove the fault redundant.

• Test Coverage (TC) Vs Fault Coverage (FC):

• TCis a measure of test quality , which consists of the %ge of all testable faults that the test
patterns set tests.
• TC= (detected faults)/(testable faults)
• FC is the %ge of faults detected among the total faultstested.
• FC= (detected faults)/(testable faults +untestable faults)

• NOTE: Clearly here , TC> FC

OCC(On-Chip Clock Controller)
OCCin Mentor Graphics
• Following are the today’s requirements:
• Independent control by ATPG of each clock domain to improve coverage ,
reduce pattern count , and achieve the safe clocking with minimal user
intervention.
• During capture , deliver correct number ofclock pulses on a per-pattern basis.
• Cleanly switch between the shift and captureclocks.
• Enable slow or fast clocks during capture for application of slow and at-speed
patterns.
• Scan-programmable clock waveforms generated within a wrapper core are
ideal for generating patterns at the core level that can be retargeted to the
top level while simultaneously testing multiple cores without conflicts in how
clocks are controlled within eachcore.
OCCin Mentor Graphics(contd..)
• In order to avoid delay on the clock path due to test logic , a MUX should already exist on the clock source to
the core flops and timed for functional behavior. It is important to only balance the functional clock path of
the MUX in order to avoid over-constraining the clock tree synthesis flow and causing excessive clock
latency.
• The clock control design should supply the clock when in test mode while using the clock output of the PLL
as the fast clock for at-speed capture. A top-level slow clock will be used for shift and slow capture. The
reference clock supplied to the PLLis a free-running clock.
• It is also recommended not to flatten the clock control blocks during layout in order to keep the test
procedure file definition easier post layout.
Clock Control logic Schematic Diagram
Clock Control logic operation of Pins
Timing Diagrams
• Slow-Speed capture (Fig:1)

• Fast capture (Fig:2)

OCC in Synopsys
• On-Chip Clocking (OCC) support is common to all scan ATPGand Adaptive Scan Environments.
This implementation is intended for designs that require ATPG in presence of PLL and clock
controller circuitry.
• OCCsupport includes PLL, clock shapers , clock dividers & clock multiplexers and so forth. In the
scan-ATPG environment, scan chain load and unload are controlled through an ATE clock.
However , internal clock signals that reach state elements during capture arePLL-related.
• For complex designs , often have many different high frequency clock domains , and the
requirement to deliver a precise launch & capture for each of these from the tester can add
significant or prohibitive cost on the test equipment. Furthermore, special tuning is often
required to properly control the clock skew to the device under test. This type of approach
generally reduces tester requirement & cost , and can also provide high speed clock pulses from
the same source as the device in its normal operating mode without additional skews from the
test equipment or test fixtures. To use this approach, additional on-chip controller circuit is
included to control the on-chip clocks in test mode.
• In the scan-ATPGenvironment , scan chain “load_unload” is controlled through an ATEclock.
However, internal clock signals that reach state elements during capture arePLL-related.
OCCin Synopsys(contd..)
• Following definitions needed as they apply to OCC:
• Reference Clocks :: The frequency reference to the PLL. It must be maintained as a constantly pulsing and free-running oscillator or
the circuitry will losesynchronization.
• PLLClocks:: The output of PLL.Afree running source that also runs at a constant frequency which might not be same asthe
reference clock.
• ATE Clocks :: Shifts the scan chain typically slower than a reference clock. You must manually add this signal (a port) when inserting
the OCC. Note that ATE clock cannot be a reference clock, and it does not capture. The period of this clock is determined by the
‘test_default_period’ variable.
• Internal Clocks:: The OCCresponsible for gating and selecting the PLLclocks and ATEclocks, and for creating the internal clocks,
which satisfy ATPGrequirements.. Sameas‘clkOCC’in below figure.
• External Clocks :: The primary inputs of a design which clock flip-flops directly through combinational logic not generated from PLLs.
Waveform & Capture CycleExample
Compression (EDT)
ATPGCompression
• Requires onboard test logic:
• Decompressor
• Compressor
• Bypass (optional)
• Reduces Test Data Volume
• Reduces Test Application Time

Basic Terminology:
Benefit of Compression
Difference between Normal & CompressionScan
Diff Between Normal & Compressed Scan(Contd.)
Results of Scan & Compression
Compression Logic
Block Diagrams of Decompressor & Compressor(Compactor)
Overview of TestCompress Tool Flow
• There are three main activities in thetool’s flow:
• Creating the EDTLogic
• Synthesizing the EDTLogic
• Generating EDTPatterns.
• Creating the EDTLogic:
• Invoke the TestKompress on Gate Level Netlist:
<mcdft tree>/bin/testkompress ../gatelevel_nl.v –verilog –library $ATPG_LIB\
-dofile edt_ip_creation.do –logile ../transcripts/edt_ip_creation.log –replace
• Provide TestKompress Commands:
Overview of TestKompress Tool Flow
report statistics
report scan volume
//close the session and exit
exit

• Synthesizing the EDTLogic:

• dc_shell –f ../created_dc_scripts.scr |& tee ../transcripts/dc_edt.log
• Generating the EDTPatterns:
• Invoke TestKompress on the Netlist with the Synthesized EDTCircuitry
<mgcdft tree>/bin/testkompress ../created_edt_top.v –verilog –library $ATPG_LIB\
-dofile edt_pattern_gen.do –logfile ../transcripts/edt_pattern_gen.log -replace
• Provide TestKompress Commands
/ / Run the *_edt.dofile output from “write edt files” when creating the EDTLogic
dofile ../created_edt.dofile
//Flatten the design , runDRCs
set system mode atpg
Overview of TestKompress Tool Flow (contd..)
//Verify the EDTconfiguration
report edt configuration
//Generate Patterns
create patterns
//Create Reports
report statistics
report scan volume
//Save the Patterns in ASCIIformat
save patterns ../generated/patterns_edt.ascii –ascii –replace
//Save the Patterns in parallel and serial verilogformat
save patterns ../generated/patterns_edt_p.v –verilog –replace –parallel
save patterns ../generated/patterns_edt_s.v –verilog –replace –serial –sample 2
//Save the Patterns in tester format : WGLformat
save patterns fs_out/test_patterns.wgl –wgl –replace
//close the session and exit
exit
 Sharing Issues with functional pins
• EDTaccepts the same fault models as that of ATPG.EDTaccepts deterministic pattern type of ATPG.
EDTcan achieve the same test coverage as that of ATPG.EDToffers no testpoints. or bounding logic
inside the design. Xsources are acceptable as no bounding logic isnecessary
• The default EDTLogic contains combinational logic and flip-flops. All the flip-flops, exceptlockup
cells are +ve edge triggered and clocked by a dedicated clock signal that is different from scanclock.
There is no clock gating within the EDTlogic; the EDTlogic does not interfere with thesystem
clock(s) in any way.
• You can setup the EDTclock to be a dedicated pin (named edt_clock by default) or you canshare
the EDTclock with a functional non-clock pin. Such sharing may cause a decrease in coverage
because TestKompress must constrain the EDTclock pin during the test pattern generation. You
must not share the EDTclock withanother clock or RAM control pin for several reasons:
• If shared with a scan clock , the scan cells could be disturbed when the EDTclock is pulsed in the load_unloadprocedure
during pattern generation.
• If shared with RAM control signals , RAM sequential patterns and multiple load patterns may not be applicable.
• If shared with a non-scan clock , test coverage may decline because EDTclock is constrained to its off-state during the capture
cycle.

• Because the clock used in EDTlogic is different than the scan-clock , the tool can insert lockup cells automatically between
the EDTlogic and the scan chains as needed. TestKompress inserts lockup cells as part of the EDTlogic ; the tool never
modifies the design.
External Flow

Internal Flow
• Default EDTPinNames
Test Proc file generated for EDT
Compactor Logic
Compactor Types
• There are 2 compactors available in TestKompress.
• Basic
• Xpress

1. Basic :: The basic compactor should be used for designs that do not generate many
unknown (X) values. Due to the scan cell masking , the basic compactor is less
effective on designs that generate Xs in scan cells when a test pattern applied. The
EDTlogic generated when the basic compactor used may be upto 30% smaller than
EDT logic generated by Xpress compactor used. However, when X values are
present , more test patterns may berequired.
2. Xpress :: The Xpress compactor optimizes compression for all designs but is
effectively effective for designs that generate X values. The Xpress compactor
observes all chains with known values , and at the same time , masks out scan
chains that contains X values. This X handling results in fewer test patterns being
required for designs that generate X values. Depending on application , this
compactor may need additional clocking cycles. This cycles determined by the ratio
of scan chains to output channels and are relatively few when compared with the
total shift cycles.
Basic Compactor Architecture
Basic Compactor Architecture (contd…)
• Amask code (prepended with a decoder mode bit) is generated with
each test pattern to determine which scan chains are masked or
observed. The basic compactor determines which chains to observe
or mask using the mask code asfollows:
1. The decompressor loads the mask code into mask shift register.
2. The mask code is parallel-loaded into the mask hold register , where the
decoder mode bit determines the observe mode: either one scan chain or
all scan chains.
3. The mask code in the mask hold register is decoded and each bit drives one
input of a masking AND gate in the compactor. Depending on the observe
mode , the output of these AND gate is either enabled or disabled.
Xpress Compactor Architecture
Xpress Compactor Architecture (contd…)
• Amask code (prepended with a decoder mode bit) is generated with each
test pattern to determine which scan chains are masked or observed. The
Xpress compactor determines which chains to observe or mask using the
mask code as follows:
1. Eachtest pattern is loaded into the decompressor through an input maskshift
register on the input channel.
2. The mask code is appended to each test pattern and remains in the mask shift
register once the test pattern is completely loaded into thedecompressor.
3. The mask code is then parallel-loaded into the mask hold register, where the
decoder mode bit determines whether the basic decoder or the XORdecoder is
used on the mask code.
• The basic decoder is used to select only one scan chain per compactor when there is ahigh
rate of Xvalues or for chain diagnosis.
• The XOR decoder is used to mask or observe multiple scan chains per compactor
depending on the mask code. For example , if the mask code is all 1s , then all the scan
chains are observed.
2. The decoder output is shifted through a multiplexer , and each bit drives one.input
on the masking AND gates in the compactor to either disable or enable the output
, depending on the decoder mode and bit value.
Why Masking Needed(X-Blocking)

• An “X” in one scan cell will block the observation of corresponding cells in other scan chains
associated in same channel. This is called X-Blocking.
• Types of Masking:
• 1-hot masking
• Flexible Masking
Why Masking Needed-Solution (1-Hot Masking)

• A masking mechanism allows automatic selection of individual scanchains,

so that Xsources from other scan chains don’t block observation.
• Masking is done only when necessary per patternbasis.
• Masking data is embedded in test pattern set. Masking data shifted into
masking register during shift cycle.
 Fault Aliasing

• Assume that one fault is observed by two scan cells, and that these scan cells are located in two scan
chains that are compacted to the same scan channel. Further , assume that these cells are in the same
locations (columns) in the twochains and neither chain is masked. Fig. above explains this.
• Assume that the good value for a certain process is a 1 in two scan cells. This corresponds to a 0
measured on the scan channel output , due to the XORin the compactor. If a fault occurs on this site ,
0s are measured in the scan cells , which also results in a 0 on the scan channel output, For this unique
scenario , it is not possible to see the difference between a good and a faulty circuit.
Fault Aliasing - Solution

• The solution to this problem is toutilize scan chain masking.

• TestKompress does this automatically.
• An aliased fault will not be classified as detected foran unmasked pattern.
• All aliased faults will be masked and detected automatically by maskedpatterns.
• The other side of the masked observed cell will get another opportunity to be observed.
LOCKUPLatches in EDT
LOCKUPLatches in EDT(contd..)
Handling Scan chains in EDTof different lengths in patterns
• What happens in compactor when two scan chains have differentlengths.
• Suppose two scan chains are compacted into one channel , as in Fig. Below.Chain1 has 6 cells long
and Chain2 has 3 cells long. The captured values of the last 3 bits of Chain1 are going to be
XOR’ed with the first 3 values of next pattern being loaded into Chain2. For regular ATPG, this
problem does not occur because the expected values on Chain2 , after you shift three positions ,
are all Xs. So you never observe the values being loaded as part of next pattern. But , if this is
done with EDT, the last three positions of Chain1 are XOR’ed with Xand faults observed on these
last cells are lost. Because the padding data for the shorter scan chains is derived from the scan-in
of the next pattern, avoid reordering serial patterns to ensure valid computed scan-out data.
•COREWRAPPERS
What is SoC??
• The integration of a complete system on an ICchip.
• Earlier consists of multiple ICchips.
• May include multiple types ofdesign blocks and intellectual property (IP) such
as Digital logic blocks , processors , memories and analogcircuitry.
• Typically SoC’s are designed using embedded reusable cores.

• SoCEvolution:
Core Overview
• SoCcores & UDLare not manufactured and tested individually.
• Cores & UDLare tested together.
• Cores are pre-designed , verified butuntested functional blocks.
• Core is the IP of vendor.
• Core vendor supplied tests must be applied toembedded cores.
• Cores are classified into 3 types , namely:
• Soft core : is a technology-independent synthesizable RTLcircuit description.
• Firm core: is a technology-dependent gate-level netlist that meets timing
constraints.
• Hard core: includes layout and timing information.
• SoCtest integrationrequires:
• Test data provided with each core.
• Core test integration methodology and tools.
Core Overview (contd…)
• Test Challenges in SoCDesign:
• The individual chips are tested separately before being assembled on the board.
• The individual cores are not tested before the complete SoCisfabricated.
• To test each core , we need to provide:
• Core test access , and
• Core isolation mechanism.
• There is no direct access to the core I/O ports from the chip I/Os.
• Use of multiple cores within onedesign.
• Compose an integrated test and its control mechanism for the overall systemchip.
• SoCTestMethodology
• Study functions and architectures in each module of a general SoC.
• Design each module.
• Add WRAPPER to each core(module).
• Integrate the IP testing some standard (ex: P1500)
DFTStrategy
• Since for technology is changing , design size is shrinking further ,ATPG
patterns are increasing and thus power consumption getting more
during test for complex SoCdesigns . So using a core-based divide-and-
conquer approach helps to overcome the challenges of high power
consumption and huge data volume generated during testing.
• Multi-mode approach:
• In a core-based testing strategy , the design is partitioned into reasonable-sized
cores that can be tested independently. At the top-level , a test schedule is
created based on the available I/Os for test and cores’ power consumption. This
strategy enables a DFTapproach , based on IEEE1450 and IEEE1500 standards ,
thatavoids power problems and can also help reduce test costs while improving
test quality.
Multi-mode approach (contd..)
• Each core is to be tested independently and requires a test wrapper cell to isolate the core from the
rest of the design and provide test access at the core’s I/Os. This test wrapper functions in various
modes under the control of a test controller. The modes supported by this wrapper include:
• INTEST (wrp_if) mode:: For testing the core logic. Wrapper cells on the input side isolate the core
from the capturing data from outside , and input wrapper cells capture the scan data. Wrapper
cells on the output side capture data from the core.
• EXTEST (wrp_of) mode :: For testing top-level user-defined logic (UDL). The Wrapper Cells on the
core inputs the data from the UDL , while the wrapper cells on the output side isolate the UDL
from capturing data from the core and also launch test data into the UDL. During capture , the
input wrapper cells capture the scan data from the UDL.
Multi-mode approach (contd..)
• To reduce the test data volume and the test cost , the cores can be tested using scan
compression based on adaptive scan technology. The wrapper chains are configured
(in INTESTmode) asinternal scan channels of scan compression logic.
• Once the wrapper and scan chains are inserted , the DFT team used a custom script
to customize the wrapper cells and created a new CTL(Core Test Language) model for
the macro level of the design for scan compression insertion.
SoCTest Access Architecture

• Test Pattern Source & Sink:

• The source generates the test stimuli for the embeddedcore.
• The sink compares the responses to the expected responses.
• Test Access Mechanism (TAM):
• Test data transport from the test source to the CUTand from the CUTto thetest
sink.
• Core Test Wrapper:
• Connects the terminals of the core to the rest of the IC and the TAM.
A Test-Wrapper (similar to P1500)
wrappers
DFTArchitecture for SoC

• 1. Test Source:
• Provides test vectors via on-chip LFSR, counter , ROM , or off-chip ATE
• 2. Test Sink:
• Provides outputverification using on-chip signature analyzer , or off-chip ATE.
• 3. Test Access Mechanism (TAM):
• User-defined test data communicationstructure.
• May contain bus, boundary-scan and analog testbus components.
• Tests module interconnects via test-wrappers.
• 4. Test Controller:
• Boundary-scan TAP.
• Receives control signals from outside.
• Serially loads test instructions intest-wrappers.
P1500 Standard Wrapper
Wrapper (P1500) Overview

• WIP: Wrapper Interface Port

• WBR : Wrapper Boundary Register
• WBY: Wrapper BypassRegister
• WIR : Wrapper Instruction Register
• Functional inputs & outputs
• Serial Interface: WSI-WSO
• Load Instruction into WIR (test control)
• Load test data to WBRandWBY.
• Parallel Interface: WPI-WPO
• Test data into WBR.
• User defined width.
• Zero or more parallel ports(typically one)
Wrapper (P1500) Examples
• Without Wrapper:

• Hidden:
Wrapper (P1500) contd…
• Normal Operation:

• Bypass Mode:
Wrapper (P1500) contd…
• Intest Mode:
• When you want to target coverage within your core.

• Extest Mode:
• When you want to target coverage outside your core.
ATPGwith Memories
• In DFT, we consider memory as BLACK-BOX and all the combinational
design which interacts directly with this Black-Box will be considered
as a SHADOW LOGIC. This include MUXes also. As memories are
declared as Black-boxes so the inputs are unobservable & outputs are
uncontrollable. So in DFT, we put Test Points (aka Shadow logic)
across memory pins to make observable at input & controllable at
output. So to increase coverage. Picture below saysshow..
PVTInformation
• Worst -> SS(Process) -> L(Voltage) -> H (Temperature) -> Max. Delay -
> Setup Violations -> Decrease the frequency to fix Setup Issue.
• Best -> FF (Process) -> H (Voltage) -> L(Temperature) -> Min. Delay ->
Hold Violations -> Add redundant logic or do some tricks in PVTto fix
Hold Issue.
• Setup Violation occurs when Gate Delays are BIG. Hence use Max
corner.
• Hold Violation occurs when Gate Delays are SMALL. Hence use Min
corner.
• We are fixing Setup Violation at MAX corner and hold at MIN corner
in order toensure that signal is within limits.