IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 67, NO.

1, JANUARY 2020 9

Efficient Supply Modulator for Wide-Band Envelope

Elimination and Restoration Power Amplifiers
Ahmed Mamdouh, Member, IEEE, Mohamed Aboudina , Senior Member, IEEE,
Faisal Hussien, Senior Member, IEEE, and Ahmed Nader Mohieldin , Senior Member, IEEE

Abstract—A fast transient response supply modulator has

been realized and verified in envelope elimination and restora-
tion (EER) power amplifier. The analysis and detailed design
of the proposed architecture is presented. Simulation results, in
130-nm CMOS technology, show that the proposed supply mod-
ulator achieves better linearity and efficiency compared to the
conventional hybrid mode supply modulators or hybrid EER
when signal frequency increases. Adjacent channel leakage ratio
requirements are met for an LTE signal with 5 MHz, 10 MHz,
and 20 MHz BW with error vector magnitude less than 3% and
efficiency of 79%, 73%, and 67%, respectively at an output power
of 0.45 W. Post-layout simulations are performed across different
process corners and the effects of real off-chip components and
routes are taken into consideration to verify the robustness of
the proposed solution.
Index Terms—Class-E power amplifier, supply modulator, Fig. 1. Block diagram of dual switch controlled hybrid supply modulator.
envelope elimination and restoration, wide-band.

A conventional hybrid converter is shown in Fig. 1. It con-

I. I NTRODUCTION
LASS-E power amplifiers (PA) show excellent efficiency
C as well as capability to provide power amplification for
RF signals up to multiple GHz. However, a linearization tech-
nique is essential if the input RF signal contains amplitude
information. The output of a class-E PA is proportional to the
value of the applied supply voltage Vout = γ VDD where γ is
constant [1]. Thus, one of the most commonly used techniques
to linearize class-E PA is envelope elimination and restoration
(EER). Phase signal is applied directly to the input, while the
envelope containing amplitude information is fed through the
supply of the PA. Using this approach, the linearity require-
ment is shifted from the high frequency of the carrier to the
low frequency of the baseband signal; consequently supply
modulation process should be done with highly linear and
efficient amplifiers. The most commonly used supply mod-
ulators, are switching mode regulators. However, they are not
fast enough to amplify the baseband signal; accordingly lin-
ear regulators are usually used together with switching mode
regulators (the hybrid supply modulator [2], [3]).
Manuscript received February 1, 2019; accepted February 11, 2019. Date
of publication February 21, 2019; date of current version December 26, 2019.
This brief was recommended by Associate Editor S. C. Wong. (Corresponding
author: Ahmed Nader Mohieldin.)
The authors are with the Electronics and Electrical Communications
Engineering, Cairo University, Giza 12613, Egypt (e-mail:
anader@eng1.cu.edu.eg).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2019.2900596
1549-7747 c 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
sists of a linear path and a switching path (excluding the extra
path). The switches of the switching path are controlled by
the comparator’s output through some buffers. The compara-
tor forces Mp to conduct when the output needs to charge (the
voltage across Rsense is positive due to the direction of the cur-
rent), and forces Mn to conduct when the output load needs
to discharge. The comparator together with the large buffers
and the big switches form a very slow long loop that is not
able to track fast changes in the envelope signal.
In order to facilitate tracking of the fast envelope signals,
the linear amplifier with class-AB push pull stage is added.
The linear stage will push more current Ilin into the load such
that the output maintains the envelope if the switching stage
is not able to track the fast envelope. The linear amplifier
forms a low-efficiency path which is responsible for tracking
fast changes of envelope signal, while the switching path is
responsible for high-current Isw low-speed changes. This sup-
ply modulator is very efficient for low speed envelopes, while
it can track fast changes with more losses in the linear ampli-
fier; thus lower efficiency [4]. In [5], an extra path has been
added as shown in Fig. 1. In case of high output power where
the envelope signal voltage is higher than a certain threshold
(Vref ), switch Mp2 will supply the required current through LB2
even if the main switching stage is not responding yet due to
the loop delay. Efficiency enhancement of 5% to 9% has been
reported compared to the conventional H-EER. However, dual
switch supply modulator has some drawbacks. First, it uses
two inductors, thus bulky and more expensive. Second, it does
not solve the fundamental speed/efficiency trade-off of H-EER,

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 10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 67, NO. 1, JANUARY 2020
Fig. 2. Architecture of the proposed hybrid supply modulator.
i.e., if high-speed envelope signal is applied, more current is
needed from the linear stage.
II. P ROPOSED E NHANCED S UPPLY M ODULATOR
The architecture of the proposed hybrid supply modulator
is shown in Fig. 2. It enhances the speed of the switching
path; and thus improves the overall efficiency. The idea of the
proposed architecture is developed as follows:
1) The loop controlling the switching path has been
removed; and an additional control circuit is used in
an open-loop configuration. The switching path consists
of digital buffers, non-overlapping circuit, switches MP
and MN , inductor LB and capacitor CB .
2) The proposed control circuit is a replica circuit for the
switching path. The replica circuit consists of two MOS
switches MP−rep and MN−rep that charge and discharge
capacitor C1 through resistor R1 . The effect of resistor
R2 is to emulate the load seen by the switching path. In
the current design, R2 has been made programmable to
account for potential variations in the load.
3) Since the switching path is an open-loop path, it is
required to include a feedback path to correct any errors
introduced by the control circuit. The feedback path is
a high-speed path that consists of a low-power linear
OTA followed by a class-AB output stage. The linear
stage should have minimum hit on efficiency, thus it is
designed with small current (< 10% of the total output
current).
It shall be noted that proposed design uses two versions of
the envelope signal. The delay between the two envelope signal
paths should be accurately calibrated from the digital domain.
The delay does not depend on the instantaneous value of the
amplitude so it does not introduce additional AM-PM distor-
tion. Similar calibration procedures are widely performed in
many H-EER systems to adjust the delay between the envelope
and phase signal paths [1]. The effect of this delay between
the two envelope signals on linearity performance (IM3) is
studied in Section III-A.
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Fig. 3. Output voltage ripples of replica circuit.
Fig. 4. Rising step response of replica circuit & switching path.
A. Design of the Proposed Supply Modulator
1) Estimating Switching Frequency of the Replica: In order
to achieve appropriate linearity performance, the switching
frequency FSW should be much higher than the signal band-
width FENV as shown in Section III-A. This is also desirable to
reduce the size of the external inductor LB but results in larger
switching losses. The value of FSW is chosen as a trade-off
between linearity and efficiency.
In order to find an estimate FSW , the ripples of Vout−rep
are assumed very small (Vout−rep  0) and thus the cur-
rent across R1 , R2 and C1 is approximately constant. It is also
assumed that the envelope Venv is constant for the sake of sim-
plifying the calculations. Thus, as shown in Fig. 3, a constant
current charges and discharges C1 , where tcomp1,2 represents
the required time for the comparator to be able to flip its polar-
ity, while tbuff is the constant delay of the buffers following the
comparator. The term tcharge,discharge is the charging and dis-
charging time until Vout−rep reaches Venv . The time required
to charge C1 through MP−rep and fully invert the polarity
of the comparator is T1 = tcomp1 + tcharge + tbuff . Similarly,
the discharging time of C1 is T2 = tcomp2 + tdischarge +
tbuff . Thus, Vout−rep = T1 Slopeup = T2 Slopedown , where
Slopeup = CV1DD R1 − Vout−rep ( C1 R1 + C1 R2 ) and Slopedown =
1 1
−Vout−rep ( C1 R1 + C1 R2 ).
1 1
FSW = 1/(T1 + T2 ) = 1/Tloop . For Venv = VDD /4 with
R1 = R2 , Slopeup = Slopedown , and tcomp1 = tcomp2 , results
in Tloop = 4(tcomp + tbuff ). The delay of the comparator is
simulated for a differential input amplitude swept from 10 mV
to 200 mV with three values of the bias current IB . For V1,2
of 50 mV, the output of the comparator becomes a healthy rail-
to-rail signal after tcomp of about 13nsec, 7.5nsec, and 3.8nsec
for IB of 0.5 mA, 1 mA, and 2 mA, respectively. tbuff is a
minor contributor of about 1nsec.
2) Design Considerations for Switching Path: In order
to achieve good rejection of the switching frequency and
 MAMDOUH et al.: EFFICIENT SUPPLY MODULATOR FOR WIDE-BAND EER PA 11

Fig. 5. Circuit implementation of the comparator in replica circuit and the Linear stage.

TABLE I
yet allow the envelope signal to pass with no significant atten- I NITIAL C OMPONENT VALUES F ROM A NALYTIC S OLUTION
uation, the LC filter is designed to have a cut-off frequency
close to the signal bandwidth as shown in eq. (1).
1
4π 2 FENV
2
= (1)
LB CB
Since the switching path is designed to work in continuous
current mode (CCM), the value of LB is chosen sufficiently parameters obtained in the first step to obtain similar dynamic
large to avoid large current ripples that leads to losses due performance. This is measured through the step response of
to discharge of the output capacitor [6]. The value of CB each loop and the resulting IM3 by combining the two loops
affects the voltage ripples on Vout ; accordingly it is chosen together. Fig. 4 shows the rising step response of the replica
large enough for low voltage ripples. Equivalent series resis- circuit and the switching path for the case of 5 MHz signal
tance (ESR) of CB degrades efficiency, so it should be chosen BW. A good agreement between the two responses for both
as minimal as possible. cases (rising and falling) is achieved for R1,2 = 10k and
3) Design Parameters for Replica Circuit: First, analytic C1 = 25pF. In Fig. 4, IM3 drawn versus C1 and R1,2 is taken
expressions are found to equate the parameters of the replica as a norm to verify achieving the best solution.
circuit with that of the switching path under the assumption Since the components of the replica circuit are prone to
that both have constant average output voltage, i.e., Vout  0 process and temperature variations, the response of the replica
and Vout−rep  0. The voltage ripples of the replica circuit circuit can deviate. The linear stage in the proposed architec-
and the switching path can be expressed as: ture (Fig. 2) is designed to track very fast envelope changes
VDD 1 1 with minimal degradation of the overall efficiency, in addition
Vout−rep = T1 [ − Vout−rep ( + )] (2) to maintaining good performance in the presence of process
C1 R1 C1 R1 C1 R2
VDD − Vout Vout variations. Performance enhancement due to the linear stage,
Vout = T12 ( ) − T1 (3) even in the presence of process variations, has been verified
2LB CB RL CB
through simulations as shown in Section III-B.
In order to simplify the solution, R1 is chosen to be equal to
R2 and it is assumed that T1 = T2 = Tloop /2. Voltage division
between R1 and R2 in the replica circuit results in halving B. Circuit Implementation of the Proposed Design
Vout−rep . Equating both voltage ripples leads to: In Fig. 5a the detailed structure of the used comparator is
Tloop /2 1 shown. It consists of a high speed cascode differential ampli-
Coeff (VDD ) = = (2) (4) fier stage followed by a differential to single-ended rail to rail
2LB CB R1 C1
grep Tloop /2 1 output stage. A cascode amplifier is used to achieve high gain
Coeff (Vout ) = (2)( )= + (5) and thus good accuracy. The speed of the comparator is a cru-
C1 2LB CB RL CB
cial requirement for achieving good performance; and thus the
where grep = R11
+ R2
1
= R2 . cascode stage consumes about 0.5 mA to 2 mA for different
Equations (1) and (4)-(5) are then solved to find the design signal BW. The input headroom issue is relaxed using R1 = R2
parameters as summarized in Table I for three different values halving the signal swing at input of the comparator.
of signal BW. RL is chosen to be 2.5  to emulate PA loading. The linear stage is shown in Fig. 5b. It consists of a single-
It is noted that the replica circuit is a first-order system ended cascode amplifier followed by a class-AB stage that
while the switching path is a second-order system. Thus, provides the required current for the load. A Miller capacitor
matching the ripple magnitude analytically does not guaran- CC and resistor RZ are added to enhance stability of the linear
tee matching the dynamic behavior. Second, the fine tuning path. The loading effect of the switching stage is added in
step, where the values of C1 and R1,2 are swept around the simulations. RL is the equivalent load resistance in the

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 12 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 67, NO. 1, JANUARY 2020
Fig. 6. Simulation results (IM3 and Transient Response).
Fig. 7. Simulation results (HD, IM3, Power Consumption and Efficiency).
range of few s, thus CB has non-dominant effect on the
overall stability. The BW of the linear stage is chosen slightly
higher than the switching frequency to be able to track the
replica circuit. Cascode amplifier consumes about 1.5 mA. The
linear stage has one dominant pole (wp1  1/rota Cc ), one non-
dominant pole (wp2 =1/RL CB ) and one Zero (wz =Cc (1/gmab −
Rz )). Where rota is the output resistance of the cascade stage
which is in range of 100 k and Cc is about 16pF. Class-AB
stage has small attenuation (about -2dB gain) due to the small
output resistance. gmab is the transconductance of the class-
AB stage, and Rz is 150 . The simulated BW of the linear
stage is 49 MHz with open loop gain of 54dB, wz is located
at 60 MHz to guarantee good phase margin.
III. S IMULATION R ESULTS
The layout of the proposed architecture in 0.13µm CMOS
technology is shown in Fig. 9. It occupies an area of
1000µmx450µm. Post-layout simulations results are shown
with a conventional class-E PA used to test the performance
of the supply modulator in EER system.
A. Two Tone Test
Two tones are applied to the input of the supply modula-
tor. Figure 6a shows the simulated third-order intermodulation
(IM3). It can be noted that the proposed supply modulator
maintains IM3 better than 40dBc for input signal frequencies
up to 5 MHz, while the conventional H-EER can only achieve
3 MHz. In order to study the performance degradation in
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case of non-ideal alignment between the two envelope signals,
the IM3 for different delay mismatch is reported as shown
in Fig. 6a. IM3 has been simulated across different technol-
ogy corners including the effect of mismatch. Since we have
off-chip components (LB and CB ) and on-chip components,
so the worst case mismatch is simulated where the off-chip
components are maximum and on-chip components are mini-
mum and vice versa as shown in Fig. 6b. The slow corner is
an indication of slow on-chip components while the off-chip
components have minimum values, i.e., worst case mismatch
between replica and switching path. The fast corner has oppo-
site conditions. The slow corner has been simulated without
the linear path, shown in Fig. 6b, indicating that the linear
stage enhances IM3 about 6dB at 5MHz.
B. Linear Stage Contribution to Harmonic Distortion
Harmonic distortion (HD) test has been performed using a
single tone signal at 2 MHz and 1.8Vpp amplitude. Figure 6c
shows that the amplitude of ripples at the output is less than
55 mV. The effect of FSW is also simulated as shown in Fig. 7a.
It is noted that the linear stage enhances HD about 3dB when
FSW is low. When FSW is high, the linear stage has lower
contribution due to its bandwidth limitation.
C. Efficiency Test
Fig. 7b shows the efficiency as well as power consumption
of the linear path. The efficiency of the conventional H-EER
is higher than the proposed design when the signal frequency
 MAMDOUH et al.: EFFICIENT SUPPLY MODULATOR FOR WIDE-BAND EER PA 13

TABLE II TABLE III

P OWER B UDGET C OMPARISON W ITH S TATE - OF - THE -A RT

reported peak efficiency is tested. The HD is reported only

in [9] and [10], where the signal applied to the supply modu-
lator is defined by the frequency Ffund and swing App . It can
be noted that the proposed design provides good efficiency
Fig. 8. PSD using the proposed supply modulator. while achieving the highest signal BW with good linearity.

IV. C ONCLUSION
The architecture of an efficient supply modulator for wide-
band EER PAs has been proposed. Design equations and trade-
offs have been presented. The design is implemented using
0.13µm CMOS technology. Post-layout simulations using LTE
signals have been performed showing that the proposed sup-
ply modulator is a good candidate for modern communication
systems supporting wide-band signals.
Fig. 9. Layout of the proposed supply modulator.
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