COEN 3103 – Logic Circuits and Design

Lesson 6 - 7

by: Engr. Ricrey E. Marquez, PCpE

•Digital logic circuits is classified as
combinational or sequential circuits
•Digital logic gates constitute the most basic
building block of a combinational logic
circuits like arithmetic circuits
•At the end of this lesson, you will be able to:
1. identify the basic elements or parts of combinational
logic circuits (CLC),
2. familiar with the design procedures in designing
combinational logic circuits, and
3. design a logic diagram of some of the building
blocks of arithmetic circuit.
PART 1
• Combinational logic circuit (CLC) is a type of logic circuit that
consists of logic gates whose outputs at any time are determined
from only the present combination of inputs

• Combinational circuit performs an operation that can be specified

logically by a set of Boolean functions
• Sequential logic circuits (SLC) is logic circuit that employs
storage elements in addition to logic gates.
• Outputs of SLC are function of the inputs and the state of the
storage elements.
• CLC are circuit used in
combinatorial logic to carry
out operations such as:
• data manipulation and
selection,
• coding,
• decoding and
• error detection
• Input variable (n). These are
binary values comes from
external inputs such switches,
sensors, and other possible
input source.
• The n-input variables could have
2n possible combinations of
binary input values.
• Output variable (m).
Generated variables for each
possible combination of inputs.
• Each possible input,
combination, there is one and
only one possible output
combination. Also, each output
function is expressed in terms of
n-input variable.
• Combinational Logic Gates.
These are digital logic circuits
that accept signals from inputs
and generate signals to the
output.
• A combinational circuit can be
specified with a truth table that
lists the output values for each
combination of input variables
• A design of combinational circuits starts from the verbal outline of the
problem and ends in a logic circuit diagram or a set of Boolean
functions from which the logic diagram can be easily obtained
• Design procedure involves the following steps:
1. Understand the problem stated
2. State any relevant algorithms
3. Construct the truth tables
4. Obtain the output functions
5. Construct the logic diagrams
6. Check the results or functionality of the circuit
PART 2
• Arithmetic circuits are those combinational logic building
blocks that can be used to perform addition and subtraction
operations on binary numbers
• The addition and subtraction are the two most commonly used
arithmetic operations, as the other two, namely multiplication and
division, are respectively the processes of repeated addition and
repeated subtraction when dealing with binary arithmetic (Maini, A.,
2007).
• Adder circuits
• Basic building blocks of all arithmetic circuits.
• Add binary numbers and give out sum (S) and carry (C) as
output
• Three types of binary adders:
1. Half-adder,
2. Full-adder, and
3. n-bit parallel adder
• A half-adder (HA) circuit is an arithmetic circuit block
that can be used to add two bits.

a) Block diagram of HA, b) truth table of HA, c) map representation and simplified Boolean function of
each output
Logic diagram of half adder (HA) circuit
• A full adder circuit is an
arithmetic circuit block that can
be used to add three bits to
produce a SUM (S) and a
CARRY (Co) output
• FA circuit overcomes the limitation
of the half-adder, which can be
used to add two bits only
• Can be constructed by cascading
tow half adder circuits (FA = HA +
HA) a) Block diagram of FA, b) truth table of FA, c)
map representation and simplified Boolean
function of each output
• An n-bit parallel adder circuit is an adder circuit that can add two n-bit
binary numbers and it can be constructed by connecting nth full adders in
series.
• Each full adder represents a bit position i (from 0 to n-1).
• Each carry output (Co) from a full adder at position i is connected to the carry in (Cin)
of the full adder at higher position i +1.
• The output of a full adder at position i is given by the general algorithm:
• Example 2-1. Design a 4-bit parallel adder circuit.

Block diagram of 4-bit parallel adder circuit

• Recall: Binary addition principles
Count the number of bit 1's from the input
If total count of bit 1's is ODD then
S == 1
Else
S == 0
For every pair binary input corresponds to 1 carry output
• Since, there are available medium scale integrated IC for a 4-bit parallel
adder circuit such as 7483. Thus, we can implement a parallel circuit using
this IC, so as to minimize the size of circuit design as well as its complexity
• Alternative circuit design for Example 2-1 using 7483 IC
• Example 2-2. Design an
8-bit parallel adder circuit
using 7483.
• Example 2-2. Design an
8-bit parallel adder circuit
using 7483.

Logic diagram of 8-bit parallel adder using 7483 IC

• Example 2-3. Design a
6-bit parallel adder circuit
using 7483.

Logic diagram of 6-bit parallel adder using 7483 IC

• A subtractor circuits are arithmetic circuit that takes two binary
numbers as input and subtract one binary number input from the
other binary number input.
• Similar to adders, it gives out two outputs namely DIFFERENCE
(D) output and BORROW (B) output (carry-in the case of adder).
• Like adder circuits, there are also three types of subtractor:
1. half-subtractor (HS),
2. full-subtractor (FS), and
3. n-bit parallel subtractor.
• In addition, this circuit may be accomplished by taking
the complement of the subtrahend (a) and adding it to
minuend (b).
• subtraction of a – b can be done by taking the 2’s
complement of b and adding it to a such as a - b = a + (b)’
• The inverters are used to make 1’s complement of b
(connecting each bi to an inverter) and then add 1 to the
least significant bit (by setting carry C0 to 1) of binary adder.
• A half-subtractor is a combinational circuit that can be used to subtract
one binary digit from another to produce a DIFFERENCE (D) output and a
BORROW (B) output.

a) Block diagram of HS, b) truth table of HS, c) map representation and simplified Boolean function of
each output
Logic diagram of half-subtractor circuit
• A full-subtractor performs subtraction operation on two bits, a minuend and a
subtrahend, and also takes into consideration whether a ‘1’ has already been borrowed by
the previous adjacent lower minuend bit or not.
• Like in full-adder circuit, a full-subtractor circuit can also be constructed by cascading two half-
subtractor circuits (FS = HS + HS)
 • A full-subtractor performs subtraction operation on two bits, a minuend and a
subtrahend, and also takes into consideration whether a ‘1’ has already been borrowed by
the previous adjacent lower minuend bit or not.
• Like in full-adder circuit, a full-subtractor circuit can also be constructed by cascading two half-
subtractor circuits (FS = HS + HS)

a) Block diagram of FS, b) truth table of FS, c) map

representation and simplified Boolean function of each output
• Same procedure with
the full-adder circuit, we
need to manipulate
some terms of the
Boolean expression for
borrow output, so that it
will inherit the difference
and borrow outputs of
the half-subtractor
circuit.
• An n-bit parallel subtractor
circuit is a combinational logic
circuit that subtract two n-bit
binary numbers and can be built
by connecting nth full-subtractor
or nth full-adder with inverted
subtrahend (b) in series
• Similar to n-bit parallel adder
circuit that follows a regular
pattern, this circuit can also be
implemented with the general
algorithm as follows:
• Example 2-4. Design a 4-bit parallel subtractor circuit that subtract two 4-
bits binary numbers and gives an output of binary difference (D 4 to D1) and
borrow output (Bo) using logic gates.

Block diagram of 4-bit parallel subtractor circuit

• Solution.
• An n-bit parallel adder or subtractor circuit is a combinational logic
circuit that add or subtract two n-bit binary numbers and can be
constructed by connecting nth full adder and taking the XOR of subtrahend
(b) and Ci (carry input).
• A controlled inverter is needed when an adder is to be used as a
subtractor.

A controlled inverter using XOR gate

Operation of controlled input (M) with B outputs
• General algorithm of n-bit parallel adder or subtractor circuit:
• Example 2-5. Design a 2-bit parallel adder or subtractor circuit using logic
gates.
Logic diagram of 2-bit parallel adder or
subtractor circuit using logic gates
• Example 2-6. Repeat Example 2-5, but design using 7483, XOR, and AND
gates.

Logic diagram of 2-bit parallel adder or subtractor circuit using 7483, XOR, and AND gates.
• Example 2-7. Design 4-bit adder or subtractor circuit using 7483, 7486,
and 7408.

Logic diagram of 4-bit parallel adder or subtractor circuit using 7483, XOR, and AND gates.
 Results in binary and the expected results in BCD using a
• A BCD adder is used to perform the four-bit binary adder to perform the addition of two BCD
digits.
addition of BCD numbers. A BCD
digit can have any of the ten
possible four-bit binary
representations, that is, 0000, 0001,
…, 1001, the equivalent of decimal
numbers 0, 1, …, 9 respectively
(Maini, A. (2007).
• Table presented lists the possible
results in binary and the expected
results in BCD when we use a four-
bit binary adder to perform the
addition of two BCD digits.
• Using map method, the resulting the Boolean expression, we can apply the necessary
correction as: Co = K + Z3Z2 + Z3Z1

a) Map representation and simplified Boolean expression of C b) logic diagram of BCD corrector circuit
• Important notes in the design of single digit BCD adder
circuit:
• 1st 7483 connections:
o A’s inputs (A4 to A1) should be connected to BCD inputs (a4 to a1) respectively,
o B’s inputs (B4 to B1) should be connected to BCD inputs (b4 to b1) respectively,
o CI/C0 (carry-in) must be connected to carry input (cIN),
o CO/C4 (K) must be part of the BCD corrector circuits, and
o Binary sums (S4 to S1) outputs are inputs of the second 7483 A’s (A4 to A1) inputs.
o In addition, the output of BCD corrector circuit is also used as carry input for the
succeeding digit of BCD adder circuits.
• Important notes in the design of single digit BCD adder circuit:
(cont.)
• 2nd 7483 connections:
o A’s (A4 to A1) should be connected to the sum outputs of the 1st 7483 (S4 to S1), since the sum
of binary adder and BCD adder are the same as long as the sum is not greater than 10012 (9).
o B4 and B1 must be connected to Ground (0), and B3 and B2 are connected to BCD corrector
circuit output (C). In that case, if binary sum is greater than 9, B3 and B2 are set to 1. Thus, B’s
inputs will have an input value of 01102 (6), which will be added to the current binary sum.
o C0/CI (carry-in) is also connected to Ground (0),
o CO/C4 (Carry-out) is no connection, and
o The sum outputs (S4 to S1) outputs are the BCD sums (S4 to S1) outputs connected to the
output devices like LEDs or inputs of seven-segment decoder ICs (7447 or 7448).
• The design of a
single digit BCD
adder circuit. This
circuit uses two
7483 IC, 2-inputs
AND gates, and
2-inputs OR
gates.
Circuit design of a single digit BCD adder circuit
• Example 2-8.
Design a two-digit
BCD adder circuit

Circuit
design of a
two-digit
BCD adder
circuit
• Example 2-8.
Design a two-digit
BCD adder circuit

Circuit
design of a
two-digit
BCD adder
circuit
PART 3
• The arithmetic logic unit (ALU) is a digital building block
capable of performing both arithmetic as well as logic
operations.
• Arithmetic logic units that can perform a variety of
arithmetic operations such as addition, subtraction, etc., and
logic functions such as ANDing, ORing, EX-ORing, etc., on
two four-bit numbers are usually available in IC form (Maini,
A., 2007).
• Multiplication of binary numbers is usually implemented in
microprocessors and microcomputers by using repeated
addition and shift operations. Below are components of
typical multiplier circuit:
• shift registers - for the multiplicand and multiplier bits.
• accumulator register - for storing partial products.
• binary parallel adder – for finding sum of two binary
• clock pulse generator - for time various operations
• Example 2-9. Design a 2-bit multiplier circuit using logic
gates.

Block diagram and truth table of 2 x 2 multiplier circuit

Map representation, simplified Boolean functions and logic diagram of a 2 x 2 multiplier
circuit
• Binary multipliers are also available in IC
form, since multiplier circuit is difficult to
implement using logic gates.
• Some of the popular type numbers in the
TTL family include 74261 which is a 2 × 4
bit multiplier (a four-bit multiplicand
designated as B0, B1, B2, B3 and B4, and a
two-bit multiplier designated as (M0, M1
and M2).
• Another variant of multiplier IC are the
74284 and 74285. Both ICs are 4 × 4 bit
multipliers that can be used together to
perform high-speed multiplication of two Circuit design of 4 x 4 multiplier circuit using 74284 and 74285 ICs
four-bit numbers
• A magnitude comparator is a combinational circuit that compares two given numbers and
determines whether one is equal to, less than or greater than the other.

• The output is in the form of three binary variables representing the conditions a = b (EQ), a > b (GT)
and a < b (LT), if a and b are the two numbers being compared

a) Truth table, b) map representation and simplified Boolean functions, and c) logic diagram of 1 bit magnitude comparator
• Comparing two n-bit numbers has 22n entries in the truth table
and become too unwieldy if the n greater that two or more bits.
For example, if n = 4, this requires 22(4) = 128 possible
combinations of inputs.
• A magnitude comparator is another combinational circuit that
possesses a certain amount of regularity (repeated processes).
If a digital function possesses an inherent well-defined regularity,
it can usually be designed by means of an algorithmic procedure
if one found to exist, rather than using k-map method or other
simplification methods (Maini, A., 2007).
• Boolean expression
representing these
conditions are
given by the
general algorithm
equations:
• Example 2-10. Design a 4-bit magnitude comparator circuit

Logic diagram of 4-bit magnitude comparator circuit

• 7485 is a four-bit magnitude comparator of the TTL logic family.
IC 4585/4063B is a similar device in the CMOS family

Pin configuration of 7485/4063B IC (4-bit magnitude comparator)

• Example 2-11. Design a 4-bit magnitude comparator using 4063B IC.

Circuit design of 4-bit magnitude comparator circuit using 4063B (CMOS 4-bit
magnitude comparator IC)
Functional table of 7485/4063B IC
• In cascade arrangement, the A = B, A > B and A < B outputs of
a stage handling less significant bits are connected to
corresponding inputs of the next adjacent stage handling more
significant bits.
• The stage handling least significant bits must have a HIGH (1)
level at the A = B input.
• The other two cascading inputs (A > B and A < B) may be
connected to a LOW (0) level.
• Example 2-12. Design an 8-bit magnitude comparator circuit
using 7485 IC.

Circuit design of 8-bit magnitude comparator circuit using 7485 (TTL 4-bit
magnitude comparator IC)
• Table below lists Commonly used IC type numbers used for arithmetic operations

commonly used IC
type numbers used for
arithmetic operations.
Application relevant
information such as
pin connection
diagrams, truth tables,
or entire data sheet
can be found internet.