Experiment

(b)
To Model a PISO( parallel input serial output ) shift
register
Entities:

entity PISO is
Port ( clk,load : in STD_LOGIC;
pi : in std_logic_vector(3 downto 0);
so : out STD_LOGIC);
end PISO;
architecture Behavioral of PISO is
signal t : std_logic;
signal temp: std_logic_vector(3 downto 0);
begin
process (clk,pi,load)
begin
if (load='1') then
temp(3 downto 0) <= pi(3 downto 0);
elsif (CLK'event and CLK='1') then
t <= temp(3);
temp(3 downto 1) <= temp(2 downto 0);
temp(0) <= '0';
end if;
end process;
so <= t;
end Behavioral;
Test Bench:

ENTITY PISO_test_vhd IS
END PISO_test_vhd;
ARCHITECTURE behavior OF PISO_test_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PISO

PORT(
clk,load : IN std_logic;
pi : IN std_logic_vector(3 downto 0);
so : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL load : std_logic := '0';
SIGNAL pi : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL so : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PISO PORT MAP(
clk => clk,
load => load,
pi => pi,
so => so
);
clk_process: process
begin
clk<='0';
wait for 50 ns;
clk<='1';
wait for 50 ns;
end process;
tb : PROCESS
BEGIN
load <='1';
pi<="1001";
wait for 50 ns;
load<='0';

wait for 400 ns;

END PROCESS;
END;

Project Diagrams:

Waveforms: