Structural VHDL program for T-Flip-Flop.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity T_Flip_Flop_Stru is
Port ( T : in STD_LOGIC;
Clock : in STD_LOGIC;
Q : out STD_LOGIC;
not_Q : out STD_LOGIC);
end T_Flip_Flop_Stru;
architecture Structural of T_Flip_Flop_Stru is
component AND_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
clk : in STD_LOGIC;

C : out STD_LOGIC);
end component AND_GATE;
component NOR_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC;
clk : in STD_LOGIC);
end component NOR_GATE;
signal s1,s2,s3,s4 : STD_LOGIC;
begin
AND_GATE_01 : AND_GATE
Port map( A => s1,
B => T,
clk =>Clock ,
C => s3);
AND_GATE_02 : AND_GATE
Port map( A => T,
B => s2,
clk =>Clock ,
C => s4);

NOR_GATE_01 : NOR_GATE
Port map( A => s3,
B => s2,
clk => Clock ,
C => Q);
NOR_GATE_02 : NOR_GATE
Port map( A => s1,
B => s4,
clk => Clock ,
C => not_Q);
end Structural;

Behavioral VHDL program for T-Flip-Flop.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity T_Flip_Flop is
Port ( T : in STD_LOGIC;
Clock : in STD_LOGIC;
Q : out STD_LOGIC;
not_Q : out STD_LOGIC;
Reset : in STD_LOGIC);
end T_Flip_Flop;
architecture Behavioral of T_Flip_Flop is
begin
process (T,Clock,Reset)
begin
if Clock'event and Clock='1' then
if Reset = '1' then
Q <= '0';
not_Q <= '0';
elsif Reset = '0' then
Q <= T;
not_Q <= not T;
end if;
end if;
end process;
end Behavioral;

b)
T-Flip-Flop structural timing diagram

T-Flip-Flop behavioral timing diagram

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FSM is
Port ( C : in STD_LOGIC;
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
a : out STD_LOGIC;
b : out STD_LOGIC);
end FSM;
architecture Structural of FSM is
component T_Flip_Flop_Stru is
Port ( T : in STD_LOGIC;
Clock : in STD_LOGIC;
Q : out STD_LOGIC;
not_Q : out STD_LOGIC);
end component T_Flip_Flop_Stru;
component NOT_GATE is
Port ( A : in STD_LOGIC;
clk : in STD_LOGIC;
B : out STD_LOGIC);
end component NOT_GATE;
component OR_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
clk : in STD_LOGIC;
C : out STD_LOGIC);
end component OR_GATE;
component AND_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
clk : in STD_LOGIC;
C : out STD_LOGIC);
end component AND_GATE;
component AND_GTE_3PIN is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
clk : in STD_LOGIC;
D : out STD_LOGIC);
end component AND_GTE_3PIN;

signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11:STD_LOGIC;
begin
NOT_GATE_01 :NOT_GATE
Port map( A => C,
clk => Clock,
B => s1);
AND_GTE_3PIN_01 :AND_GTE_3PIN
Port map( A => C,
B => s3,
C => s5,
clk => Clock,
D => s6);
AND_GTE_3PIN_02 :AND_GTE_3PIN
Port map( A => s1,
B => s3,
C => s4,
clk => Clock,
D => s7);
AND_GATE_01 :AND_GATE
Port map( A => s3,
B => s5,
clk => Clock,
C => s8);
AND_GATE_02 :AND_GATE
Port map( A => C,
B => s5,
clk => Clock,
C => s9);
AND_GATE_03 :AND_GATE
Port map( A => s3,
B => s4,
clk => Clock,
C => a);
AND_GATE_04 :AND_GATE
Port map( A => s2,
B => s4,
clk => Clock,
C => b);
OR_GATE_01 :OR_GATE
Port map( A => s6,
B => s7,
clk => Clock,
C => s10);
OR_GATE_02 :OR_GATE
Port map( A => s8,
B => s9,

clk => Clock,

C => s11);
T_Flip_Flop_Stru_01 :T_Flip_Flop_Stru
Port map( T => s10,
Clock => Clock,
Q => s2,
not_Q => s3);
T_Flip_Flop_Stru_02 :T_Flip_Flop_Stru
Port map( T => s11,
Clock => Clock,
Q => s4,
not_Q => s5);
end Structural;

c)
entity TEST_BENCH_FSM is
end TEST_BENCH_FSM;
architecture Structural of TEST_BENCH_FSM is
component FSM
Port ( C : in STD_LOGIC;
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
a : out STD_LOGIC;
b : out STD_LOGIC);
end component FSM;
--Inputs
signal C : STD_LOGIC := '0';
signal Clock : STD_LOGIC := '0';
signal Reset : STD_LOGIC := '0';
--Outputs
signal a : STD_LOGIC;
signal b : STD_LOGIC;
--Clock period definition
constant Clock_period :time := 10 ns;
begin
FSM_01 :FSM
Port map( C => C,
Clock => Clock,
Reset => Reset,
a => a,
b => b);
Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;

Clock <= '1';

wait for Clock_period/2;
end process;
stimulus_process_01 : process
begin
wait for 25000ps;
C <= '1';
wait for 35000ps;

C <= '0';
end process;
stimulus_process_02 : process
begin
wait for 25000ps;
Reset <= '1';
wait for 5000ps;
Reset <= '0';
end process;
end Structural;

c)

entity FSM_tb is
Port ( C : in STD_LOGIC;
CLOCK : in STD_LOGIC;
CLEAR : in STD_LOGIC;
A : inout STD_LOGIC;
B : inout STD_LOGIC);
end FSM_tb;
architecture Structutal of FSM_tb is
component T_Flip_Flop_Stru is
Port ( T : in STD_LOGIC;
Clock : in STD_LOGIC;
Q : out STD_LOGIC;
not_Q : out STD_LOGIC);
end component T_Flip_Flop_Stru;
component AND_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
clk : in STD_LOGIC;
C : out STD_LOGIC);
end component AND_GATE;
signal s1,s2 :STD_LOGIC;
begin
T_Flip_Flop_Stru_01: T_Flip_Flop_Stru
Port map( T => C,
Clock => CLOCK ,
Q => B,
not_Q => s1);
T_Flip_Flop_Stru_02: T_Flip_Flop_Stru
Port map( T => s2,
Clock => CLOCK ,
Q => A);
AND_GATE_01: AND_GATE
Port map( A => C ,
B => s1,
clk => CLOCK ,
C => s2);