COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

CompEng 311 - Logic Circuits and

Design

Counter
Design, Register
Design and ALU
Function
Module 5

Amacdalino2020

AMACDALINO2020
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

Table of Contents
COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION ..................................................................... 1
Introduction ......................................................................................................................................... 1
Learning Outcomes ............................................................................................................................ 1
Learning Content................................................................................................................................ 1
Topic 1: COUNTERS ............................................................................................................................. 2
DEFINITION ....................................................................................................................................... 2
ASYNCHRONOUS (RIPPLE) COUNTER ............................................................................................ 2
i. Operation ............................................................................................................................ 2
ii. Truth Table............................................................................................................................ 4
SYNCHRONOUS COUNTER ............................................................................................................. 4
i. 2-bit Synchronous UP Counter ........................................................................................... 5
CLASSIFICATION OF COUNTERS ..................................................................................................... 6
Binary Up Counter........................................................................................................................... 6
Binary Down Counter ..................................................................................................................... 7
Bidirectional Counters (UP/DOWN Counters) .............................................................................. 7
BCD Counters .................................................................................................................................. 8
Ring Counter ................................................................................................................................... 8
Johnson Counter ............................................................................................................................ 9
Topic 2: Registers............................................................................................................................... 10
Definition ........................................................................................................................................ 10
Serial Input Serial Output (SISO) ................................................................................................... 11
i. Block Diagram ................................................................................................................... 11
ii. Operation .......................................................................................................................... 11
iii. Truth Table.......................................................................................................................... 12
iv. Waveforms......................................................................................................................... 12
Serial Input Parallel Output (SIPO) ............................................................................................... 13
i. Block Diagram ................................................................................................................... 13
Parallel Input Serial Output (PISO) ............................................................................................... 13
i. Load Mode ........................................................................................................................ 13
ii. Shift Mode .......................................................................................................................... 13
iii. Block Diagram ................................................................................................................... 14
Parallel Input Parallel Output (PIPO) ........................................................................................... 14
i. Block Diagram ................................................................................................................... 14
Bidirectional Shift Register ............................................................................................................ 15
i. Block Diagram ................................................................................................................... 15
ii. Operation .......................................................................................................................... 15
Universal Shift Register .................................................................................................................. 15

AMACDALINO2020 i
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

i. Block Diagram ................................................................................................................... 16

Topic 3: Arithmetic and Logic Unit (ALU) ........................................................................................ 16
Definition ........................................................................................................................................ 16
Teaching and Learning Activities.................................................................................................... 17
Recommended learning materials and resources for supplementary reading ........................ 18
Flexible Teaching Learning Modality (FTLM) adopted .................................................................. 18
Assessment Task ................................................................................................................................ 18

AMACDALINO2020 ii
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

Module 5

COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

Introduction

This module presents counters, registers and ALU. It discusses what counters are
including its classifications and other types, registers types and ALU functions.

Learning Outcomes
At the end of the lesson, students are expected to:
➢ Draw a timing diagram relating the input and output of such latches and flip-flops.
➢ Differentiate Asynchronous and Synchronous Counter.
➢ Relate Register and Register Transfer in the processes in the memory
➢ Explain the operation of shift registers, show how to build them using flip-flops, and
analyze their operation.
➢ Construct a timing diagram for a shift register. Explain the operation of binary counters,
show how to build them using flip-flops and gates, and analyze their operation.
➢ Explain the procedures used for deriving flip-flop input equations.
➢ Construct a timing diagram for a counter by tracing signals through the circuit.
➢ Design and Implement simple ALU

Learning Content
COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION
Topic 1: COUNTERS
o DEFINITION
o ASYNCHRONOUS (RIPPLE) COUNTER
i. Operation
ii. Truth Table
o SYNCHRONOUS COUNTER
i. 2-bit Synchronous UP Counter
o CLASSIFICATION OF COUNTERS
▪ Binary Up Counter
▪ Binary Down Counter
▪ Bidirectional Counters (UP/DOWN Counters)
▪ BCD Counters
▪ Ring Counter
▪ Johnson Counter
Topic 2: Registers
o Definition
o Serial Input Serial Output (SISO)
i. Block Diagram
ii. Operation
iii. Truth Table
iv. Waveforms
o Serial Input Parallel Output (SIPO)
i. Block Diagram
o Parallel Input Serial Output (PISO)
i. Load Mode
ii. Shift Mode
iii. Block Diagram
o Parallel Input Parallel Output (PIPO)
i. Block Diagram
o Bidirectional Shift Register
i. Block Diagram

AMACDALINO2020 1
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

ii. Operation
o Universal Shift Register
i. Block Diagram
Topic 3: Arithmetic and Logic Unit (ALU)
o Definition

Topic 1: COUNTERS

DEFINITION
• A counter is a sequential circuit that goes through a prescribed sequence of states
upon the application of input pulses. The input pulses (count pulses) of the counter is
clock pulses, or from some external source, and may occur at prescribed intervals of
time or at random.
• It is an equivalent of binary odometer. It counts the number of CLK pulses which arrive
at the CLK input.
• Counters can be classified into two broad categories according to the way they are
clocked:
1. Asynchronous (ripple) counters: the first FF is clocked by the external clock
pulse, and then each successive FF is clocked by the Q or Q’ output of the
previous FF.
2. Synchronous counters – all FFs are simultaneously triggered by the same clock.
• The counter follows the binary number sequence or other sequence of states. A
counter that follows the binary sequence is called a binary counter. An n-bit binary
counter consists of n flip-flops and can count in binary from 0 to 2n-1.

ASYNCHRONOUS (RIPPLE) COUNTER

• Is formed with a series of cascaded flip-flops. The flip-flops are connected as toggles
and the output of one stage feeds the clock input of the next stage.
• The logic diagram of a 2-bit ripple up counter is shown in Figure 1.A. The toggle (T) flip-
flop is being used. But we can use the JK flip-flop also with J and K connected
permanently to logic 1. External clock is applied to the clock input of flip-flop A and QA
clock output is applied to the clock input of the next flip-flop i.e. FF-B.

Figure 1.A. Logic diagram of a 2-bit ripple up counter

i. Operation
S.N. Condition Operation
1 Initially let both QBQA = 00 initially
the FFs be in the 1st clock pulse 2nd clock pulse 3rd clock pulse 4th clock pulse

reset state CLK

QA

QB

AMACDALINO2020 2
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

2 After 1st As soon as the first negative clock edge is applied, FF-A will toggle
negative clock and QA will be equal to 1.
edge 1st clock pulse 2nd clock pulse 3rd clock pulse 4th clock pulse

CLK
1st negative clock edge

QA
QA is toggled leading it to be equal to 1

QB

QA is connected to clock input of FF-B. Since QA has changed from

0 to 1, it is treated as the positive clock edge by FF-B. There is no
change in QB because FF-B is a negative edge triggered FF.
QBQA = 01 after the first clock pulse.
1st clock pulse 2nd clock pulse 3rd clock pulse 4th clock pulse

CLK
1st negative clock edge

QA
QA is toggled leading it to be equal to 1

QB
No change in QB

3 After 2nd On the arrival of second negative clock edge, FF-A toggles again
negative clock and QA = 0.
1st clock 3rd clock 4th clock
edge pulse
2nd clock pulse
pulse pulse

CLK
2nd negative clock edge

QA
QA is toggled leading it to be equal to 0.

QB

The change in QA acts as a negative clock edge for FF-B. So it will

also toggle, and QB will be 1.
QBQA = 10 after the second clock pulse.
1st clock 3rd clock 4th clock
2nd clock pulse
pulse pulse pulse

CLK
2nd negative clock edge

QA
QA is toggled leading it to be equal to 0.

QB
The toggling of QA triggered QB to
toggle.
4 After 3rd On the arrival of 3rd negative clock edge, FF-A toggles again and
negative clock QA become 1 from 0.
1st clock pulse 2nd clock pulse 3rd clock pulse 4th clock pulse
edge
CLK
3rd negative clock edge

QA
QA is toggled leading from 0 to 1.

QB

AMACDALINO2020 3
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

Since this is a positive going change, FF-B does not respond to it

and remains inactive. So QB does not change and continues to be
equal to 1.
QBQA = 11 after the third clock pulse.
1st clock pulse 2nd clock pulse 3rd clock pulse 4th clock pulse

CLK
3rd negative clock edge

QA
QA is toggled leading from 0 to 1.

QB
No change in QB. (positive edge)

5 After 4th On the arrival of 4th negative clock edge, FF-A toggles again and
negative clock QA becomes 1 from 0.
edge 1st clock pulse 2nd clock pulse 3rd clock pulse 4th clock pulse

CLK
4th negative clock edge

QA
QA is toggled leading to 1 from 0.

QB

This negative change in QA acts as clock pulse for FF-B. Hence it

toggles to change QB from 1 to 0.
QBQA = 00 after the fourth clock pulse.
1st clock 2nd clock 3rd clock
4th clock pulse
pulse pulse pulse

CLK
4th negative clock edge

QA
QA is toggled leading to 1 from 0.

QB
QB toggled since change in QA becomes its
negative clock edge.
Note: In this we can say that the negative-edge trigger is the state when an input/output
changes its value from high (1) to low (zero) and positive edge-trigger is a state when an
input/output changes its value from low (zero) to high (1).

ii. Truth Table

Counter Output
Clock State Number Decimal Counter Output
QB QA
Initially 0 0 - 0
1st 0 1 1 1
2nd 1 0 2 2
3rd 1 1 3 3
4th 0 0 4 0

SYNCHRONOUS COUNTER
• A state wherein the “clock” pulses are applied to all the flip-flops in a counter
simultaneously
• The clock inputs of all the flip-flops are connected with each other so that the clock
signal reaches them simultaneously.

AMACDALINO2020 4
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

i. 2-bit Synchronous UP Counter

o The JA and KA inputs of the FF-A are tied to logic 1. So FF-A will work as a toggle
flip-flop. The JB and KB inputs are connected to QA.

Logic Diagram

Operation
S.N. Condition Operation
1 Initially let both the QBQA = 00 initially
FFs be in the reset 1st clock pulse 2nd clock pulse 3rd clock pulse 4th clock pulse

state CLK

QA

QB
2 After 1st negative As soon as the first negative clock edge is applied, FF-A will
clock edge toggle and QA will change from 0 to 1.
1st clock pulse 2nd clock pulse 3rd clock pulse 4th clock pulse

CLK
1st negative clock edge

QA
QA is toggled leading it to 1

QB

But at the instant of application of negative clock edge, Q A,

JB=KB=0. Hence FF-B will not change its state.
QBQA = 01 after the first clock pulse.
1st clock pulse 2nd clock pulse 3rd clock pulse 4th clock pulse

CLK
1st negative clock edge

QA
QA is toggled leading it to 1

QB
No change in QB

3 After 2nd negative On the arrival of second negative clock edge, FF-A toggles
clock edge again and QA changes from 1 to 0.
1st clock 3rd clock 4th clock
2nd clock pulse
pulse pulse pulse

CLK
2nd negative clock edge

QA

AMACDALINO2020 5
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

QA is toggled leading it to be equal

to 0.

QB

But at this instant QA was 1. So JB=KB=1 and FF-B will toggle.

Hence QB changes from 0 to 1
QBQA = 10 after the second clock pulse.
1st clock 3rd clock 4th clock
2nd clock pulse
pulse pulse pulse

CLK
2nd negative clock edge

QA
QA is toggled leading it to be equal
to 0.

QB
The toggling of QA triggered QB to
toggle.

4 After 3rd negative On the application of the 3rd falling clock edge, FF-A will
clock edge toggle from 0 to 1 but there is no change of state for FF-B
QBQA = 11 after the third clock pulse.
1st clock 2nd clock 4th clock
3rd clock pulse
pulse pulse pulse

CLK
3rd negative clock edge

QA
QA is toggled leading from 0 to
1.

QB
No change in QB.

5 After 4th negative On the application of the next clock pulse, QA will change
clock edge from 1 to 0 as QB will also change from 1 to 0.

1st clock 2nd clock 3rd clock

4th clock pulse
pulse pulse pulse

CLK
4th negative clock edge

QA
QA is toggled leading to 1 from 0.

QB
QB toggled since change in QA becomes
its negative clock edge.

CLASSIFICATION OF COUNTERS
Depending on the way in which the counting progresses, the synchronous or asynchronous
counters are classified as follows:
• UP Counters – counts upward
• DOWN Counters – counts downward
• UP/DOWN Counters – counts up or down depending on value the control input

Binary Up Counter
The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA, but
the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also

AMACDALINO2020 6
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

supplied with signals from the input and output of the previous stage. These additional AND
gates generate the required logic for the JK inputs of the next stage.

Binary Down Counter

As well as counting “up” from zero and increasing or incrementing to some preset value, it is
sometimes necessary to count “down” from a predetermined value to zero allowing us to
produce an output that activates when the zero count or some other pre-set value is reached.

Bidirectional Counters (UP/DOWN Counters)

• are capable of counting in either the up direction or the down direction through any
given count sequence
• also known as Up/Down counters, are capable of counting in either direction through
any given count sequence and they can be reversed at any point within their count
sequence by using an additional control input as shown below.

AMACDALINO2020 7
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

• Generally, most bidirectional counter chips can be made to change their count
direction either up or down at any point within their counting sequence. This is
achieved by using an additional input pin which determines the direction of the count,
either Up or Down and the timing diagram gives an example of the counters operation
as this Up/Down input changes state.

BCD Counters
A 4-bit decade synchronous counter can also be built using synchronous binary counters to
produce a count sequence from 0 to 9. A standard binary counter can be converted to a
decade (decimal 10) counter with the aid of some additional logic to implement the desired
state sequence. After reaching the count of “1001”, the counter recycles back to “0000”. We
now have a decade or Modulo-10 counter.

The additional AND gates detect when the counting sequence reaches “1001”, (Binary 10)
and causes flip-flop FFD to toggle on the next clock pulse. Flip-flop FFA toggles on every clock
pulse. Thus, the count is reset and starts over again at “0000” producing a synchronous decade
counter.
We could quite easily re-arrange the additional AND gates in the above counter circuit to
produce other count numbers such as a Mod-12 counter which counts 12 states from ”0000″
to “1011” (0 to 11) and then repeats making them suitable for clocks, etc.
Ring Counter
A ring counter is a type of counter composed of a circular shift register. The output of the last
shift register is fed to the input of the first register.

AMACDALINO2020 8
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

Johnson Counter
Synchronous counter where the complement of the output of the last shift register is
connected to the input of the first register and circulates a stream of ones followed by zeros
around the ring as shown in the figure below.

S.NO SYNCHRONOUS COUNTER ASYNCHRONOUS COUNTER

1. In synchronous counter, all flip flops are In asynchronous counter, different flip flops
triggered with same clock simultaneously. are triggered with different clock, not
simultaneously.
2. Synchronous Counter is faster than Asynchronous Counter is slower than
asynchronous counter in operation. synchronous counter in operation.
3. Synchronous Counter does not produce any Asynchronous Counter produces decoding
decoding errors. error.

AMACDALINO2020 9
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

4. Synchronous Counter is also called Parallel Asynchronous Counter is also called Serial
Counter. Counter.
5. Synchronous Counter designing as well Asynchronous Counter designing as well as
implementation are complex due to implementation is very easy.
increasing the number of states.
6. Synchronous Counter will operate in any Asynchronous Counter will operate only in
desired count sequence. fixed count sequence (UP/DOWN).
7. Synchronous Counter examples are: Ring Asynchronous Counter examples
counter, Johnson counter. are: Ripple UP counter, Ripple DOWN
counter.
8. In synchronous counter, propagation delay is In asynchronous counter, there is high
less. propagation delay.
There is no connection between output of the Flip-flops are connected in such a way that
first flip-flop and clock of the next flip-flop. the output of first flip-flop drives the clock of
next flip-flop.
Flip-flops are clocked simultaneously Flip-flops are not clocked simultaneously.
Circuit becomes complicated as number of Circuit is simple for more number of states.
states increases.
Speed is high as clock is given at a same time Speed is slow as clock is propagated through
number of stages.

Topic 2: Registers
Definition
• A register is a memory device that can be used to store more than one bit of
information.
• A register is usually realized as several flip-flops with common control signals that control
the movement of data to and from the register.
o Common refers to the property that the control signals apply to all flip-flops in
the same way.
o A register is a generalization of a flip-flop. Where a flip-flop stores one bit, a
register stores several bits.
o The main operations on a register are the same as for any storage devices,
namely
▪ Load or Store: Put new data into the register.
▪ Read: Retrieve the data stored in the register (usually without changing
the stored data)
• Control Signals
o When they are asserted, they initiate an action in the register
o Asynchronous Control Signals cause the action to take place immediately.
o Synchronous Control Signals must be asserted during a clock assertion to have
an effect.
• Flip-flop is a 1-bit memory cell which can be used for storing the digital data. To
increase the storage capacity in terms of number of bits, we have to use a group of
flip-flops. Such a group of flip-flip-flop is known as a Register. The n-register will consist
of n number of flip-flop and it is capable of storing an n-bit word.
• The binary data in a register can be moved within the register from one flip-flop to
another. The registers that allow such data transfers are called as shift registers. There
are four mode of operations of a shift register.
o Serial Input Serial Output
o Serial Input Parallel Output
o Parallel Input Serial Output
o Parallel Input Parallel Output

AMACDALINO2020 10
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

Serial Input Serial Output (SISO)

Let all the flip-flop be initially in the reset condition i.e. Q 3 = Q2 = Q1 = Q0 = 0. If an entry of four-
bit binary number 1 1 1 1 is made into the register, this number should be applied to Din bit with
the LSB bit applied first. The D input of FF-3 (i.e. D3) is connected to serial data input Din output
of FF-3 (i.e. Q3) is connected to the input of the next flip-flop (i.e. D2) and so on.

i. Block Diagram

ii. Operation
1. Before application of clock signal, let Q 3Q2Q1Q0 = 0000 and apply LSB bit of the
number to be entered to Din. So, Din = D3 = 1. Apply the clock. On the first falling
edge of the clock, the FF-3 is set and stored word in the register is Q3Q2Q1Q0 = 1000.

2. Apply the next bit to Din. So, Din = 1. As soon as the next negative edge of the clock
hits, FF-2 will set and the stored word change to Q3Q2Q1Q0 = 1100.

3. Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the
third negative clock edge hits, FF-1 will set and output will be modified to Q3Q2Q1Q0
= 1110.

AMACDALINO2020 11
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

4. Similarly, with Din = 1 and with the fourth negative clock edge arriving, the stored
word in the register is Q3Q2Q1Q0 = 1111.

iii. Truth Table

iv. Waveforms

AMACDALINO2020 12
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

Serial Input Parallel Output (SIPO)

• In such types of operations, the data is entered serially and taken out in
parallel fashion.
• Data is loaded bit by bit. The outputs are disabled as long as the data is
loading.
• As soon as the data loading gets completed, all the flip-flops contain their
required data, the outputs are enabled so that all the loaded data is made
available over all the output lines at the same time.
• 4 clock cycles are required to load a four-bit word. Hence the speed of
operation SIPO mode is same as that of SISO mode.

i. Block Diagram

Parallel Input Serial Output (PISO)

• Data bits are entered in parallel fashion.

• The circuit shown below is a four-bit parallel input serial output register.
• Output of previous Flip Flop is connected to the input of the next one via a
combinational circuit.
• The binary input word B0, B1, B2, B3 is applied though the same combinational
circuit.
• There are two modes in which this circuit can work namely - shift mode or
load mode.

i. Load Mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become
active they will pass B1, B2, B3 bits to the corresponding flip-flops. On the low
going edge of clock, the binary input B0, B1, B2, B3will get loaded into the
corresponding flip-flops. Thus, parallel loading takes place.
ii. Shift Mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become
inactive. Hence parallel loading of the data becomes impossible. But the
AND gate 1,3 and 5 become active. Therefore the shifting of data from left
to right bit by bit on application of clock pulses. Thus, the parallel in serial
out operation takes place.

AMACDALINO2020 13
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

iii. Block Diagram

Parallel Input Parallel Output (PIPO)

In this mode, the 4-bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1,
D2, D3 respectively of the four flip-flops. As soon as a negative clock edge is
applied, the input binary bits will be loaded into the flip-flops simultaneously. The
loaded bits will appear simultaneously to the output side. Only clock pulse is
essential to load all the bits.

i. Block Diagram

AMACDALINO2020 14
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

Bidirectional Shift Register

• If a binary number is shifted left by one position then it is equivalent to multiplying the
original number by 2. Similarly, if a binary number is shifted right by one position then itis
is equivalent to dividing the original number by 2.
• Hence, if we want to use the shift register to multiply and divide the given binary
number, then we should be able to move the data in either left or right direction.
• Such a register is called bi-directional register. A four-bit bi-directional shift register is
shown in the block diagram
• There are two serial inputs namely the serial right shift data input DR, and the serial left
shift data input DL along with a mode select input (M).

i. Block Diagram

ii. Operation

S.N. Condition Operation

1 With M=1 – Shift
Right Operation
2 With M=0 – Shift
Left Operation
If M = 1, then the AND gates 1, 3, 5 and 7 are enabled whereas
the remaining AND gates 2,4, 6 and 8 will be disabled.
The data at DR is shifted to right bit by from FF-3 to FF-0 on the
application of clock pulses. Thus, with M = 1 we get the serial right
shift operation.
When the mode control M is connected to 0 then the AND gates
2, 4, 6 and 8 are enabled while 1, 3, 5, and 7 are disabled.
The data of DL are shifter left by bit from FF-0 to FF-3 on the
application of clock pulses. Thus, with M=0, we get the serial right
operation.

Universal Shift Register

A shift register which can shift the data in only one direction is called a uni-directional shift
register. A shift register which can shift data in both directions is called a bi-directional shift
register. Applying the same logic, a shift register which can shift the data in both directions as
well as load it parallelly, is known as a universal shift register. The Shift register is capable of
performing the following operations:

AMACDALINO2020 15
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

• Parallel Loading
• Left Shifting
• Right Shifting
The mode control input is connected to logic 1 for parallel loading operations whereas it is
connected to 0 for serial shifting. With mode control pin connecter to ground, the universal
shift register acts as a bi-directional register. For serial left operation, the input is applied to the
serial input which goes to AND gate-1 shown in block diagram. Whereas, for the right
operation, the serial input is applied to D input.

i. Block Diagram

Topic 3: Arithmetic and Logic Unit (ALU)

Definition
• A digital circuit used to perform arithmetic logic operations
• It represents the fundamental building click of the central processing unit (CPU) of a
computer.
• It is capable of performing logical operations (e.g. AND, OR, Ex-OR, Invert, etc.) in
addition to the arithmetic operations (e.g. Addition, Subtraction, etc.) The control unit
supplies the data required by the ALU from memory, or from input devices, and directs
the ALU to perform a specific operation based on the instruction fetched from the
memory. ALU is the “calculator” portion of the computer.

AMACDALINO2020 16
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

• An arithmetic logic unit (ALU) is a major component of the central processing unit of a
computer system. It does all processes related to arithmetic and logic operations that
need to be done on instruction words. In some microprocessor architectures, the ALU
is divided into the arithmetic unit (AU) and the logic unit (LU).

• An ALU can be designed by engineers to calculate many different operations. When

the operations become more and more complex, then the ALU will also become more
and more expensive and also takes up more space in the CPU and dissipates more
heat. That is why engineers make the ALU powerful enough to ensure that the CPU is
also powerful and fast, but not so complex as to become prohibitive in terms of cost
and other disadvantages.

• ALU is also known as an Integer Unit (IU). The arithmetic logic unit is that part of the CPU
that handles all the calculations the CPU may need. Most of these operations are
logical in nature. Depending on how the ALU is designed, it can make the CPU more
powerful, but it also consumes more energy and creates more heat. Therefore, there
must be a balance between how powerful and complex the ALU is and how expensive
the whole unit becomes. This is why faster CPUs are more expensive, consume more
power and dissipate more heat.

• Different operation as carried out by ALU can be categorized as follows –

o logical operations − These include operations like AND, OR, NOT, XOR, NOR,
NAND, etc.
o Bit-Shifting Operations − This pertains to shifting the positions of the bits by a
certain number of places either towards the right or left, which is considered a
multiplication or division operations.
o Arithmetic operations − This refers to bit addition and subtraction. Although
multiplication and division are sometimes used, these operations are more
expensive to make. Multiplication and subtraction can also be done by
repetitive additions and subtractions respectively.

Teaching and Learning Activities

Watch the following video lectures:
o Introduction to Sequential Circuits
▪ https://www.youtube.com/watch?v=AaN72s5WfOM&list=PLBlnK6fEyqR
jMH3mWf6kwqiTbT798eAOm&index=144
o Introduction to Counters:
▪ https://www.youtube.com/watch?v=iaIu5SYmWVM
o Types of Counters:
▪ https://www.youtube.com/watch?v=yqg1sqhZG3M
o Introduction to Registers:
▪ https://www.youtube.com/watch?v=-paFaxtTCkI

AMACDALINO2020 17
 COUNTER DESIGN, REGISTER DESIGN AND ALU FUNCTION

o ALU
▪ https://www.youtube.com/watch?v=U6GDGzEGRgc

Recommended learning materials and resources for supplementary reading

https://www.geeksforgeeks.org/differences-between-synchronous-and-asynchronous-
counter/
https://www.geeksforgeeks.org/ripple-counter-in-digital-logic/
https://www.tutorialspoint.com/arithmetic-logic-unit-alu

Flexible Teaching Learning Modality (FTLM) adopted

In this Module, the online and remote FTLM is adapted using the university’s Learning
Management System called SeDi. For the online modality, the Virtual Classroom of SeDi shall
be used for the purpose of delivering a lecture and allowing a synchronous discussion with the
students. For the remote modality, SeDI shall be used to upload the module and to allow
asynchronous discussion with the students. This will also be used as platform for the submission
of the requirements.

Assessment Task
Watch the videos listed at the Teaching and Learning Activities section of this module.
Provide an impression or understanding of each video in a separate answer sheet. (20 points
each video impression. Total of 100 points)

AMACDALINO2020 18