LATCHES AND FLIP-FLOPS: SR, D, JK, T

CompEng 311 - Logic Circuits and Design

Latches and
Flip-Flops:
SR, D, JK, T
Module 4

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Table of Contents
LATCHES AND FLIP-FLOPS: SR, D, JK, T ........................................................................................................ 1
Introduction .......................................................................................................................................... 1
Learning Outcomes ............................................................................................................................... 1
Learning Content .................................................................................................................................. 1
Topic 1: Latches .................................................................................................................................... 2
Definition .......................................................................................................................................... 2
SR Latch ............................................................................................................................................ 2
i. SR Latch using NAND Gate .................................................................................................... 2
ii. SR Latch using NOR Gate ....................................................................................................... 3
Gated S-R Latch ................................................................................................................................. 4
D Latch .............................................................................................................................................. 5
Topic 2: Edge-triggered Latches or Flip-flops ........................................................................................ 5
Definition .......................................................................................................................................... 5
SR Flip-Flop ....................................................................................................................................... 7
D Flip-flop ......................................................................................................................................... 7
JK Flip-flop......................................................................................................................................... 8
Toggle Flip-flop ................................................................................................................................. 8
Flip-Flop Conversion ....................................................................................................................... 10
Example: JK to D flip-flop conversion .......................................................................................... 10
Teaching and Learning Activities ......................................................................................................... 11
Recommended learning materials and resources for supplementary reading ................................... 11
Flexible Teaching Learning Modality (FTLM) adopted ........................................................................ 11
Assessment Task ................................................................................................................................. 11

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Module 4

LATCHES AND FLIP-FLOPS: SR, D, JK, T

Introduction

This module presents latches and flip-flops. It discusses what latches and flip-flops are
including their 4 basic types which are SR, D, JK and T. Operations, characteristic table, truth
table and excitation table are also presented including flip-flop conversion. At the end of the
lesson, assessment task will be given to check students’ understanding of the module.

Learning Outcomes
At the end of the lesson, students are expected to:
➢ Explain the operation of S-R and gated D latches.
➢ Explain the operation of D, D-CE, S-R, J-K, and T flip-flops.
➢ Analyze the operation of a flip-flop that is constructed of gates and latches

Learning Content
Topic 1: Latches
o Definition
o SR Latch
▪ SR Latch using NAND Gate
▪ SR Latch using NOR Gate
o Gated S-R Latch
o D Latch
Topic 2: Edge-triggered Latches or Flip-flops
o Definition
o SR Flip-Flop
o D Flip-flop
o JK Flip-flop
o Toggle Flip-flop
o Flip-Flop Conversion
▪ Example: JK to D flip-flop conversion

Latches and Flip-Flops

• the basic elements for storing information.
• One latch or flip-flop can store one bit of information.
• The main difference between latches and flip-flops is that
o For latches, their outputs are constantly affected by their inputs as long as the
enable signal is asserted. In other words, when they are enabled, their content
changes immediately when their inputs change.
o Flip-flops, on the other hand, have their content change only either at the rising
or falling edge of the enable signal. This enable signal is usually the controlling
clock signal. After the rising or falling edge of the clock, the flip-flop content
remains constant even if the input changes.
• There are basically four main types of latches and flip-flops: SR, D, JK, and T. The major
differences in these flip-flop types are the number of inputs they have and how they
change state. For each type, there are also different variations that enhance their
operations. In this chapter, we will look at the operations of the various latches and
flipflops.

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Latches
Building blocks of sequential
circuits and these can be built
from logic gates
Continuously checks its inputs and
changes its output
correspondingly
Based on the enable function
input
Level triggered, it means that the
output of the present state and
input of the next state depends on
the level that is binary input 1 or 0
Asynchronous
Flip-Flops
Building blocks of sequential
circuits but these can be built from
the latches
Continuously checks its inputs and
changes its output
correspondingly only at times
determined by clocking signal
It works on the basis of clock
pulses
Edge triggered, it means that the
output and the next state input
changes when there is a change
in clock pulse
Synchronous

Topic 1: Latches

Definition
• Operate on signal levels
• Level-sensitive devices
• the basic circuits from which all flip-flops are constructed
• Graphic Symbols for Latches

SR Latch
- can be considered as one of the most basic sequential logic circuit possible.
- This simple circuit is basically a one-bit memory bistable device that has two inputs,
one which will “SET” the device (meaning the output = “1”), and is labelled S and
another which will “RESET” the device (meaning the output = “0”), labelled R.
- has two types:
o SR Latch using NAND Gates
o SR Latch using NOR Gates

i. SR Latch using NAND Gate

• simplest way to make any basic single bit set-reset SR flip-flop is to connect together a
pair of cross-coupled 2-input NAND gates
• has two inputs, one which will “SET” the device (meaning the output = “1”), and is
labelled S and another which will “RESET” the device (meaning the output = “0”),
labelled R.
• the prime in S and R denotes that these inputs are active low. An “active-low” input is
one where that particular gate function is activated or invoked on a low logic state.

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•
S R Q Q’ Description

1 0 0 1 Set Q’ » 1

1 1 0 1 no change

0 1 1 0 Reset Q’ » 0

1 1 1 0 no change

0 0 1 1 Not used
* The condition of S = R = “0” causes both outputs Q and Q’ to be HIGH together at logic level
“1” when we would normally want Q’ to be the inverse of Q. The result is that the flip-flop loses
control of Q and Q’, and if the two inputs are now switched “HIGH” again after this condition
to logic “1”, the flip-flop becomes unstable and switches to an unknown data state.

Think and Learn ……

Suppose that Q=0 and Q’=1. What happens with the circuit if
S is set to 1 and R is set to 0?
What happens if S and R are both set to 1?
What happens if S is set to 0 and R is set to 1?
What happens if S and R are both set to 1?
What happens if S and R are both set to 0?

ii. SR Latch using NOR Gate

• simplest way to make any basic single bit set-reset SR flip-flop is to connect together a
pair of cross-coupled 2-input NOR gates
• consists of two inputs, one called the Set, S and the other called the Reset, R with two
corresponding outputs Q and its inverse or complement Q’ (not-Q)

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S R Q Q’ Description

0 1 0 1 No change

0 0 0 1 Memory

1 0 1 0 No change

0 0 1 0 Memory
1 1 0 0 Not used
0 0 0 1 Not used

Think and Learn ……

Suppose that Q=1 and Q’=0. What happens with the

circuit if S is set to 1 and R is set to 0?
What happens if S and R are both set to 0?
What happens if S is set to 0 and R is set to 1?
What happens if S and R are both set to 0?
What happens if S and R are both set to 1?

Gated S-R Latch

- a latch that changes state only when certain conditions are met, regardless of its S
and R input states.
- The conditional input is called the enable, and is symbolized by the letter E.

When E=0, the outputs of the two AND gates are forced to 0, regardless of the states of
either S or R. Consequently, the circuit behaves as though S and R were both 0, latching
the Q and not-Q outputs in their last states. Only when the enable input is activated (1)
will the latch respond to the S and R inputs.

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D Latch
- Since the enable input on a gated S-R latch provides a way to latch the Q and not-
Q outputs without regard to the status of S or R, we can eliminate one of those
inputs to create a latch circuit with no “illegal” input states. Such a circuit is called
a D latch, and its internal logic looks like this:

Note that the R input has been replaced with the complement (inversion) of the old S
input, and the S input has been renamed to D. As with the gated S-R latch, the D latch
will not respond to a signal input if the enable input is 0—it simply stays latched in its last
state. When the enable input is 1, however, the Q output follows the D input.

Since the R input of the S-R circuitry has been done away with, this latch has no “invalid”
or “illegal” state. Q and not-Q are always opposite of one another.

Topic 2: Edge-triggered Latches or Flip-flops

Definition
• the most important memory element technically named as bistable multivibrator
• made up of an assembly of logic gates
• The term “Flip-flop” relates to the actual operation of the device, as it can be “flipped”
into one logic Set state or “flopped” back into the opposing logic Reset state.

In many digital applications, it is desirable to limit the responsiveness of a latch circuit

to a very short period of time instead of the entire duration that the enabling input is activated.
One method of enabling a circuit is called edge triggering, where the circuit’s data inputs
have control only during the time that the enable input is transitioning from one state to
another. Let’s compare timing diagrams for a normal D latch versus one that is edge-triggered:

In the first timing diagram, the outputs respond to input D whenever the enable (E)
input is high, for however long it remains high. When the enable signal falls back to a low state,
the circuit remains latched. In the second timing diagram, we note a distinctly different
response in the circuit output(s): it only responds to the D input during that brief moment of

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time when the enable signal changes, or transitions, from low to high. This is known as positive
edge-triggering.
There is such a thing as negative edge triggering as well, and it produces the following
response to the same input signals:

Whenever we enable a multivibrator circuit on the transitional edge of a square-wave

enable signal, we call it a flip-flop instead of a latch. Consequently, an edge-triggered S-R
circuit is more properly known as an S-R flip-flop, and an edge-triggered D circuit as a D flip-
flop. The enable signal is renamed to be the clock signal. Also, we refer to the data inputs (S,
R, and D, respectively) of these flip-flops as synchronous inputs, because they have effect only
at the time of the clock pulse edge (transition), thereby synchronizing any output changes with
that clock pulse, rather than at the whim of the data inputs.

To further discuss, the D-latch with pulses in its control input is essentially a flip-flop that
is triggered every time the pulse goes to the logic 1 level. The state transions of the latches start
as soon as the clock pulse changes to the logic 1 level. The state of a latch appears at the
output while the pulse is still active.
The problem with the latch is that it responds to a change in the level of a clock pulse.
The key to the proper operation of a flip-flop is to trigger it only during a signal transition. A
clock pulse goes through two transitions from 0 to 1 and the return from 1 to 0.
The positive transition is defined as the positive-edge and the negative transition as the
negative-edge.

Clock response in Latch and Flip-Flop

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SR Flip-Flop
- a 2-input NAND gate in series with each input terminal of the SR latch
- has extra conditional input called an “Clock” input and is given the prefix of “clk”
- The problems with S-R latches using NOR and NAND gate is the invalid state. This
problem can be overcome by using a bistable SR flip-flop that can change outputs
when certain invalid states are met, regardless of the condition of either the Set or
the Reset inputs. For this, a clocked S-R flip flop is designed by adding two AND
gates to a basic NOR Gate flip flop. The circuit diagram is shown below while the
other details for this flip flop is shown at the Summary section.

SR Flip-flop circuit

D Flip-flop
- Is a slight modification of the above explained clocked SR flip-flop. From the figure
below you can see that the D input is connected to the S input and the
complement of the D input is connected to the R input. The D input is passed on to
the flip flop when the value of CP is ‘1’. When CP is HIGH, the flip flop moves to the
SET state. If it is ‘0’, the flip flop switches to the CLEAR state.

- Delay Flip-flop or D flip-flop is the most important of the Clocked Flip-flops as it

ensures that inputs S and R are never equal to one at the same time
- constructed from a gated SR flip-flop with an inverter added between the S and
the R inputs to allow for a single D (data) input.

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JK Flip-flop
- is a modification of the S-R flip-flop. The only difference is that the intermediate
state is more refined and precise than that of S-R flip-flop. The behavior of inputs J
and K is the same as the S and R inputs of the S-R flip-flop. The letter J stands for SET
and the letter K stands for CLEAR.

When both the inputs J and K have a HIGH state, the flip-flop switches to the
complement state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0,
it switches to Q=1.

CP

When both J and K inputs are 1, however, something unique happens. Because of the
selective inhibiting action of those 3-input AND gates, a “set” state inhibits input J so
that the flip-flop acts as if J=0 while K=1 when in fact both are 1. On the next clock
pulse, the outputs will switch (“toggle”) from set (Q=1 and not-Q=0) to reset (Q=0 and
not-Q=1). Conversely, a “reset” state inhibits input K so that the flip-flop acts as if J=1
and K=0 when in fact both are 1. The next clock pulse toggles the circuit again from
reset to set.

Toggle Flip-flop
- a method of avoiding the indeterminate state found in the working of RS flip-flop is
to provide only one input (T) such, flip-flop acts as a toggle switch. Toggle means
to change in the previous stage i.e. switch to opposite state.

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Summary of Flip Flops

Flip-flop Name Flip-flop Logic Symbol Truth Table Characteristic Table Characteristic Equation Excitation Table
SR Q S R Qnext S R Q(next) Qnext = S+R’Q Q Q(next) S R
0 0 0 0 0 0 Q SR = 0 0 0 0 X
0 1 1 0
0 0 1 0 0 1 0
1 0 0 1
0 1 0 1 1 0 1 1 1 X 0
0 1 1 x 1 1 ?
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 x

JK Q J K Qnext J K Q(next) Qnext = JQ' + K'Q Q Q(next) J K

0 0 0 0 0 0 Q 0 0 0 X
0 1 0 0 1 1 X
0 0 1 0
1 0 1 1 0 X 1
0 1 0 1 1 1 Q' 1 1 X 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

T Q T Qnext T Q(next) Qnext = TQ' + T'Q Q Q(next) T

0 0 0 0 Q 0 0 0
1 Q' 0 1 1
0 1 1
1 0 1
1 0 1 1 1 0
1 1 0

D Q D Qnext D Q(next) Qnext = D Q Q(next) D

0 0 0 0 0 0 0 0
1 1 0 1 1
0 1 1
1 0 0
1 0 0 1 1 1
1 1 1

Truth Table – shows how a logic circuit's output responds to various combinations of the inputs
Characteristic Table – defines the state of each flip-flop as a function of its inputs and previous state.
Excitation Table – lists the required inputs for a given change of state

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Flip-Flop Conversion
- flip-flops can be converted from one type to another.
- To successfully convert, follow the steps below:

Steps:
1. Identify available and required flip-flop.
2. Make characteristic table for required flip-flop.
3. Make excitation table for available flip-flop.
4. Write boolean expression for available flip-flop.
5. Draw the circuit.

Example: JK to D flip-flop conversion

1. Required FF = D, Available FF = JK
2. Characteristic table for required FF:

Qn D Qn+1
0 0 0
0 1 1
1 0 0
1 1 1

3. Excitation table for available FF:

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 x 0

Then combine:

Qn D Qn+1 J K
0 0 0 0 X
0 1 1 1 X
1 0 0 X 1
1 1 1 X 0

4. Boolean expression for available FF:

J=D K = D’

5. Draw the circuit.

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Teaching and Learning Activities

• Lecture and Discussion
• Self-directed Learning using Week 7-8 Module
• Watching pre-recorded video lectures
• Hands-on activities

Recommended learning materials and resources for supplementary reading

http://www.allaboutcircuits.com/textbook/digital/chpt-10/edge-triggered-latches-flip-flops/
http://www.electronics-tutorials.ws/sequential/seq_2.html
http://www.daenotes.com/electronics/digital-electronics/flip-flops-types-applications-
woking

Flexible Teaching Learning Modality (FTLM) adopted

In this Module, the online and remote FTLM is adapted using the university’s Learning
Management System called SeDi. For the online modality, the Virtual Classroom of SeDi shall
be used for the purpose of delivering a lecture and allowing a synchronous discussion with the
students. For the remote modality, SeDI shall be used to upload the module and to allow
asynchronous discussion with the students. This will also be used as platform for the submission
of the requirements.

Assessment Task

***To be uploaded separately.

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