A D flip-flop stands for data or delay flip-flop. The outputs of this flip-flop are equal to the inputs.

Gate Level Modeling

The logic diagram of a D Flip Flop:

From the above circuit, we can see that we need four NAND gates and one NOT gate to construct a D-flip flop
in gate-level modeling.

The module is declared listing the terminal ports in the logic circuit.
module d_ff_gate(q,qbar,d,clk);
...
endmodule

Note that outputs are declared first followed by inputs since built-in gates also follow the same pattern.
Thereafter, let’s declare the input and output ports.
input d,clk;
output q, qbar;

Clear Input in Flip flop

All hardware systems should have a pin to clear everything and have a fresh start. It applies to flip flops too.
Hence, we will include a clear pin that forces the flip flop to a state where Q = 0 and Q’ = 1 despite whatever
input we provide at the D input. This clear input becomes handy when we tie up multiple flip flops to build
counters, shift registers, etc.
Behavioral Modeling of D flip flop with Synchronous Clear
For synchronous clear, the output will reset at the triggered edge (positive edge in this case) of the clock after
the clear input is activated. Here’s the code:

module dff_behavioral(d,clk,clear,q,qbar);
input d, clk, clear;
output reg q, qbar;
always@(posedge clk)
begin
if(clear== 1)
q <= 0;
qbar <= 1;
else
q <= d;
qbar = !d;
end
endmodule

Behavioral Modeling of D flip flop with Asynchronous Clear

For asynchronous clear, the clear signal is independent of the clock. Here, as soon as clear input is activated,
the output reset. This can be achieved by adding a clear signal to the sensitivity list. Here’s the code:

module dff_behavioral(d,clk,clear,q,qbar);
input d, clk, clear;
output reg q, qbar;
always@(posedge clk or posedge clear)
begin
if(clear== 1)
q <= 0;
qbar <= 1;
else
q <= d;
qbar = !d;
end
endmodule

Structural Modeling
In the case of D-flip flop, we have a NOT and four NAND gates that build the circuit.
Hence, we have to structurize each gate with their respective module.

To start with code, we will first structurize the NAND gate.

We declare the module as nand_gate. The input and output ports are then declared.
module nand_gate(c,a,b);
input a,b;
output c;

Then, we use assign statement to write the logical expression for NAND.
assign c= ~(a & b);

The endmodule keyword is used for representing the end of the module.
Similarly, we do for NOT gate
module not_gate(f,e);
input e;
output f;

assign f = ~e;
endmodule

Note: All the variables for assigning inputs and outputs in one module are kept different from others. This
ensures mixing up of signals does not happen during a simulation.

Now, there is need to integrate these lower modules to form our D-flip flop. In order to do that, module
instantiation is used. First, start with the name of the lower hierarchy module (defined and declared above)
and write the name of the instance of your choice. The port-list will contain the output signals, followed by the
input ones.

For example,
nand_gate nand1(x,clk,d);

Here,
(1.) module-name :- nand_gate
(2.) instance name:- nand1
(3.) output port:- x (intermediate signal)
(4.) input ports:- d and clk

Do the same for the rest of the instances

not_gate not1(dbar,d);
nand_gate nand1(x,clk,d);
nand_gate nand2(y,clk,dbar);
nand_gate nand3(q,qbar,y);
nand_gate nand4(qbar,q,x);
endmodule

Hence, the final structure code will be:

module nand_gate(c,a,b);
input a,b;
output c;
assign c = ~(a&b);
endmodule

module not_gate(f,e);
input e;
output f;
assign f= ~e;
endmodule

module d_ff_struct(q,qbar,d,clk);
input d,clk;
output q, qbar;
not_gate not1(dbar,d);
nand_gate nand1(x,clk,d);
nand_gate nand2(y,clk,dbar);
nand_gate nand3(q,qbar,y);
nand_gate nand4(qbar,q,x);
endmodule

Testbench
//test bench for d flip flop
//1. Declare module and ports

module dff_test;
reg D, CLK,reset;
wire Q, QBAR;

//2. Instantiate the module we want to test. We have instantiated the

dff_behavior

dff_behavior dut(.q(Q), .qbar(QBAR), .clear(reset), .d(D), .clk(CLK));

// instantiation by port name.

//3. Monitor TB ports

$monitor("simtime = %g, CLK = %b, D = %b,reset = %b, Q = %b, QBAR = %b",
$time, CLK, D, reset, Q, QBAR);

//4. Apply test vectors

initial begin
clk=0;
forever #10 clk = ~clk;
end
initial begin
reset=1; D <= 0;
#100; reset=0; D <= 1;
#100; D <= 0;
#100; D <= 1;
end
endmodule
RTL Schematic
The RTL schematic of the design of the behavioral model of D flip flop without clear input will look like:

With synchronous clear input,

With asynchronous clear input,

Simulated Waveform
The functional correctness of described D flip-flop can be verified by simulation. The simulated waveform of D flip flop is given below:

Simulated waveform of D flip flop without clear

Simulated waveform of D flip flop with synchronous clear

In this waveform, you will see that the Q and Q’ will be reset state at the positive cycle after clear is activated.

Simulated waveform of D flip flop with asynchronous clear

In this waveform, we can see that the Q and Q’ will be in the reset state as soon as clear is activated.