SRM VALLIAMMAI ENGINEERING COLLEGE

SRM Nagar, Kattankulathur – 603 203

DEPARTMENT OF
INFORMATION TECHNOLOGY

QUESTION BANK
Academic Year 2019-2020

III SEMESTER
CS8351-DIGITAL PRINCIPLES AND SYSTEM DESIGN
Regulation – 2017
CHOICE BASED CREDIT SYSTEM

Prepared by

Dr. A. R. Revathi, Associate Professor/IT

Ms. S. Shenbagavadivu, Assistant Professor (Sr.G)/IT

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 SRM VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603 203.

DEPARTMENT OF INFORMATION TECHNOLOGY

QUESTION BANK
SUBJECT : DIGITAL PRINCIPLE AND SYSTEM DESIGN
SEM / YEAR : III SEMESTER/ SECOND YEAR

UNIT I - BOOLEAN ALGEBRA AND LOGIC GATES

Number Systems - Arithmetic Operations - Binary Codes- Boolean Algebra and Logic Gates - Theorems and Properties of
Boolean Algebra - Boolean Functions - Canonical and Standard Forms - Simplification of Boolean Functions using Karnaugh
Map - Logic Gates – NAND and NOR Implementations.

PART-A
Q.no Question BTL Competence
1 Find the octal equivalent of hexadecimal numbers of AB.CD (OR) DC.BA BTL5 Evaluating
2 Add, subtract and multiply the following numbers in binary (110010)2 and BTL2 Understanding
(11101)2.
3 State the principle of Duality. BTL2 Understanding
4 Implement AND gate using only NOR gates. (OR) Realize XOR gate using only BTL6 Creating
NAND gates.
5 Convert (0.6875)10 to binary (OR) Convert (126)10 to Octal (OR) Covert (1128)16 BTL3 Applying
to decimal
6 Prove the following using DeMorgan’s Theorem BTL2 Understanding
[(X + Y)'+(X + Y) '] '=X + Y.
7 Write short notes on weighted binary codes. (OR) State the classification of binary BTL2 Understanding
codes
8 Illustrate NOR Operation with a truth table BTL6 Creating
9 What is Excess-3 Code? BTL1 Remembering
10 Simplify Z = (AB +C) (B'D + C'E')+(AB+C)' (OR) F=x’y’+xy+x’y BTL4 Analyzing
11 Realize G = AB'C +DE+F' (OR) Represent a OR gate using NAND gate BTL4 Analyzing
12 Convert (1001010. 1101001)2 to base 16 & (231.07)8 to base 10 (OR) Represent BTL3 Applying
3856 in BCD and 2421 code.
13 Convert the (1011111011)2 into gray code. (OR) Convert (A3B)H into decimal BTL3 Applying
number.
14 Find the complement of the function F= X'YZ' + X'Y'Z. BTL1 Remembering
15 Define Self complementary Code? BTL1 Remembering
16 What are Universal Gates? Why are they named so? BTL1 Remembering
17 What bit must be complemented to change an ASCII letter from capital to lower BTL1 Remembering
case and vice versa?
18 Express the following Boolean expression in to minimum number of literals. BTL5 Evaluating
XYZ+X'Y+XYZ'.
19 What are the limitations of K-map? BTL1 Remembering
20 Analyse the following Boolean functions using three variable maps. F(X,Y,Z) = BTL4 Analyzing
∑(0,2,3,6,7).

PART-B
Q.no Question Mark BTL Competence
1 Simplify the following switching function using Quine Mc Cluskey method 13 BTL3 Applying
and realize expression using gates F(A,B,C,D) = ∑(0,5,7,8,9,10,11,14,15)
2 Simplify the following switching function using karnaugh map method and 13 BTL2 Understanding
realize expression using gates F(A,B,C,D) = ∑m(0,2,8,10,12,13,14,15) +

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 ∑d(5,7)
3 Simplify the function F(w,x,y,z)=∑m(2,3,12,13,14,15) using Tabulation 13 BTL4 Analyzing
method. Implement the simplified function using gates.
4(a) Demonstrate by means of truth tables the validity of the DeMorgan’s 04 BTL1 Remembering
theorem for three variables : (XYZ)’=X’+Y’+Z’ (OR) State and prove De
Morgan’s theorems for 2-variables
4(b) Simplify the following Boolean functions by means of a 4 variable map 05 BTL5 Evaluating
F(A,B,C,D)=∑m(0,2,4,5,8,10,14,15)
4(c) Implement the following Boolean function only with NAND gates, using a 04 BTL6 Creating
minimum number of gate inputs F(A,B,C,D)=AB+CD
5 Simplify the Boolean function in Sum of Products(SOP) and Product of 13 BTL4 Analyzing
Sum(POS) F(w,x,y,z)=∑m(0,1,2,5,8,9,10). (OR)
Simplify the following Boolean expression in Sum of Product & Product of
Sum using Karnaugh map : AC' + B'D + A'CD + ABCD.
6(a) Express the following function in sum of min-terms and product of max- 06 BTL2 Understanding
terms : F(X,Y,Z)=X+YZ.
6(b) Convert the following logic system in to NAND gates only. 07 BTL3 Applying

7 Write short notes on Demorgans theorem, Absorption law and consensus 13 BTL1 Remembering
law.
8 Minimize the following function using Karnaugh map F(A,B,C,D) = 13 BTL4 Analyzing
∑m(0,1,2,3,4,5,6,11,12,13)
9 Minimize the expression using K-map and Quine Mc-cluskey method Y= 13 BTL2 Understanding
A’BC’D + A’BC’D+ABC’D’+ABC’D’+AB’C’D+A’B’CD’
10(a) Convert the following numbers in to decimal: (11011.101)2, (5432)6 04 BTL5 Evaluating
10(b) Perform the following arithmetic operation using 2’s complement 03 BTL5 Evaluating
arithmetic: (11011100)2-(10011011)2
10(c) Express the following functions in sum of minterms and product of 06 BTL2 Understanding
maxterms : F(ABCD)=A’B+BD+AC’
11 Explain the rules for Binary Addition and Subtraction using 1's & 2’s 13 BTL5 Evaluating
complement. Give examples.
12 Explain about common postulates used to formulate various algebraic 13 BTL1 Remembering
structures.
13(a) Explain the procedure for obtaining NAND- NAND circuit for any AND- 06 BTL5 Evaluating
OR network with a suitable example. (OR) Implement the following
Boolean function with NAND-NAND logic F(A,B,C)= ∑M(0,1,3,5)
13(b) Implement Y= (A'B+AB') (C+D') using NOR gates. 07 BTL3 Applying
14(a) Explain the procedure for obtaining NOR- NOR circuit for any AND-OR 06 BTL5 Evaluating
network with a suitable example.
14(b) Simplify the given Boolean function in POS form using k-map and draw the 07 BTL4 Analyzing
logic diagram using NOR gates.
F(A,B,C,D) =ΠM(0,1,4,7,8,10,12,15)+d(2,6,11,14)

PART-C
Q.no Question Mark BTL Competence
1 Define prime implicate and essential prime implicate. 04 BTL1 Remembering

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 Minimize the expression using Quine Mc Cluskey method 11 BTL5 Evaluating
F=∑m(0,1,9,15,24,29,30) + ∑d(8,11,31)
2 Express the following function in a simplified manner using K map 15 BTL6 Creating
technique (i) G=πM(0,1,3,7,9,11).
(ii) f(W,X,Y,Z)=∑m(0,7,8,9,10,12) + ∑d(2,5,13).
(OR)
Reduce the expression using tabulation method F(X1,X2,X3,X4,X5) =
∑m(0,2,4,5,6,7,8,10,14,17,18,21,29,31) + ∑d(11,20,22)
3 Simplify the following function using five variable map: 15 BTL5 Evaluating
F(A,B,C,D,E)=A’B’CE’+B’C’D’E’+A’B’D’+B’C’D’+A’CD+A’BD
4 Simplify the following expression 15 BTL5 Evaluating
Y= m1+m3+m4+m7+m8+m9+m10+m11+m12+m14 using Quine Mc Cluskey
method & K map technique

UNIT II - COMBINATIONAL LOGIC

Combinational Circuits – Analysis and Design Procedures - Binary Adder-Subtractor - Decimal Adder - Binary Multiplier -
Magnitude Comparator - Decoders – Encoders – Multiplexers - Introduction to HDL – HDL Models of Combinational
circuits.

PART-A
Q.no Question BTL Competence
1 Write the truth table of 2 to 4 line decoder and draw its logic diagram (OR) BTL6 Creating
Implement (solve) the function G=∑m (0, 3) using a 2x4 decoder.
2 Draw (design) the circuit diagram for 2 to 1 line multiplexer. BTL3 Applying
3 Convert the binary code 111012 to its equivalent grey code. BTL5 Evaluating
4 What is priority encoder? BTL1 Remembering
5 Implement (solve) a full adder with 4x1 multiplexer. (OR) Draw 1:8 Demultiplexer BTL6 Creating
using two 1:4 Demultiplexers
6 Write the Data flow description of a 4 bit comparator. BTL2 Understanding
7 What is half adder?. Draw the truth table of half adder BTL1 Remembering
8 Write short notes on propagation delay BTL2 Understanding
9 Define combinational circuits BTL1 Remembering
10 Differentiate between Multiplexer and Demultiplexer. BTL4 Analyzing
11 State the differentiate between decoder and demultiplexer. BTL4 Analyzing
12 Obtain the truth table for BCD to Excess-3 code converter BTL1 Remembering
13 Draw the truth table and circuit diagram of 4 to 2 encoder. BTL3 Applying
14 Write any two advantages of HDL. BTL2 Understanding
15 Write the HDL data flow description of 4 bit adder BTL2 Understanding
16 Differentiate between encoder and decoder. BTL4 Analyzing
17 List out the application of multiplexer. BTL1 Remembering
18 Determine the HDL description for the following circuit BTL5 Evaluating

19 How a full adder is obtained from two half adders? BTL3 Applying
20 List the truth table of full subtractor. BTL1 Remembering

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 PART-B
Q.no Question Mark BTL Competence
1 Describe the process involved in converting 8421 code to Excess 3 code 13 BTL2 Understanding
with neat sketch. (OR) Design a code converter that converts a 8421 to BCD
Code (OR) Design a BCD to Excess 3 code converter and explain
2(a) Examine the following Boolean function using 8 to 1 Multiplexer. 06 BTL4 Analyzing
F(A,B,C,D)=A’BD’ + ACD + B'CD + A'C'D.
2(b) Discover the above function using 16 to 1 Multiplexer. 07 BTL4 Analyzing
3 Describe the procedure of converting 8421 to Gray code converter also 13 BTL2 Understanding
realize the converter using only NAND gates.
4 Design 2-bit magnitude comparator and write a verilog HDL code. 13 BTL6 Creating
5(a) Examine the following Boolean functions with a multiplexer. F(w,x,y,z) = 06 BTL4 Analyzing
∑m(2,3,5,6,11,14,15)
5(b) Construct a 5 to 32 line decoder using 3 to 8 line decoders and 2 to 4 line 07 BTL3 Applying
decoder.
(OR)
Design 32 to 1 multiplexer using four 8 to 1 multiplexer and 2 to 4 decoder
6(a) Explain the Analysis procedure. Analyze the following logic diagram. 06 BTL5 Evaluating

6(b) With neat diagram explain the 4 bit adder with Carry look ahead. 07 BTL5 Evaluating
7(a) Design of 4 bit binary adder – subtractor circuit 05 BTL6 Creating
7(b) Design a combinational circuit that accepts a 3 bit number and generates a 6 08 BTL6 Creating
bit binary number output equal to the square of the input number. Write a
high level behaviour VHDL description for the circuit.
8 Design the full adder with inputs x,y,z and two outputs S and C. The 13 BTL6 Creating
circuits perform x+y+z is the input carry, C is the output carry and S is the
Sum & realize it’s using only NOR gates
(OR)
Design Full subtractor and derive expression for difference and borrow.
Realize using gates.
9 Design a logic circuit that accepts a 4-bit gray code and converts it to 4-bit 13 BTL6 Creating
binary code
10(a) Design a 2 bit binary multiplier to multiply two binary numbers and produce 06 BTL1 Remembering
a 4-bit result.
10(b) Construct a 4-bit odd parity generator circuit using gates 07 BTL3 Applying
11 Recall the design procedure for a combinational circuit to perform BCD 13 BTL1 Remembering
addition.
12 (a) Explain the logic diagram of a 4 Input Priority Encoder (08) 13 BTL1 Remembering
(b) Design 8 to 3 priority encoder (05)
(OR)
Explain in detail about encoders and decoders
13(a) Explain the design procedure for combinational circuits with suitable 07 BTL5 Evaluating
examples
13(b) Construct 16X1 multiplexer with two 8X1 and 2X1 multiplexer. Use Block 06 BTL3 Applying
diagrams
14(a) Write the HDL gate level description of the priority encoder circuit. 07 BTL2 Understanding

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 14(b) Implement the following function using 8 to 1 multiplexer f(a,b,c,d)= 06 BTL1 Remembering
∑m(0,1,3,5,9,12,14,15)

PART-C
Q.no Question Mark BTL Competence
1 Declare a module that describe a circuit that is specified with the following 15 BTL4 Analyzing
two Boolean expressions:
E=A+BC+B’D
F=B’C+BC’D
2(a) How to design a 4 bit magnitude comparator with 3 outputs A>B,A=B,A<B 08 BTL5 Evaluating
2(b) Find the design procedure for a 4 –bit parallel binary adder / subtractor. 07 BTL5 Evaluating
3 Design a binary to gray code converter circuit & a BCD to 7- Segment code 15 BTL6 Creating
converter circuit
4 Find the design procedure for binary multiplier 15 BTL6 Creating

UNIT III - SYNCHRONOUS SEQUENTIAL LOGIC

Sequential Circuits - Storage Elements: Latches , Flip-Flops - Analysis of Clocked Sequential Circuits - State Reduction and
Assignment - Design Procedure - Registers and Counters - HDL Models of Sequential Circuits.

PART-A
Q.no Question BTL Competence
1 Summarize the characteristic table and equation of JK flip flop. (OR) State the BTL2 Understanding
excitation table of JK-flip flop
2 Write any two application of shift register. BTL2 Understanding
3 With reference to a JK flip flop what is racing? BTL1 Remembering
4 Identify how many JK- flip-flops are required to design a MOD 35 counter? BTL3 Applying
5 What are the significances of state assignment? (OR) State the rules for state BTL1 Remembering
assignment
6 How many states are there in a 3-bit ring counter? what are they? BTL5 Evaluating
7 Give block diagram of Master -Slave D Flip flop BTL1 Remembering
8 Draw the diagram of T- Flip flop and discuss its working. (OR) Draw the logic BTL3 Applying
diagram and write the function table of D Latch.
9 Classify the shift registers. (OR) What is shift register ? BTL4 Analyzing
10 Analyze how many flip-flops are required to design a synchronous MOD 60 counter? BTL4 Analyzing
11 Develop the HDL code to realize a D - flip flop BTL6 Creating
12 Define state table BTL1 Remembering
13 Realize a JK flip flop using D flip flop. BTL3 Applying
14 Write down the steps involved in the design of synchronous sequential circuits. BTL2 Understanding
15 Recall the Characteristics equation of JK-flip flop (OR) Characteristics equation of BTL1 Remembering
JK-flip flop SR flip flop
16 Explain the difference between the performance of asynchronous and synchronous BTL5 Evaluating
counter (OR) Write the difference between synchronous and asynchronous sequential
circuit
17 Differentiate between latch and flip flop. BTL4 Analyzing
18 Define Ripple counter ( OR) What is Ring counter? BTL1 Remembering
19 What is meant by edge triggered flip flops?.List any two mechanisms to achieve edge BTL2 Understanding
triggering of flip flop
20 Design a 4 bit binary synchronous counter with D flip flops. (OR) Draw the block BTL6 Creating
diagram of a 4 bit serial in serial out right shift register.
PART-B
Q.no Question Mark BTL Competence
1 Implement T flip-flop using D flip-flop and JK using D flip flop. 13 BTL5 Evaluating

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 2 Design a synchronous counter with the following sequence: 0,1,3,7,6,4 and 13 BTL6 Creating
repeats. Use JK Flip flop.
3 Design a MOD-10 Synchronous counter using JK flip-flop. Write execution 13 BTL6 Creating
table and state table. (OR) Design MOD 6 counter circuit.
4(a) How a race condition can be avoided in a flip-flop. 06 BTL1 Remembering
4(b) Realize the sequential circuit for the state diagram shown below. 07 BTL4 Analyzing

a/0

X=1 X=0,X=1

c/1 b/0
X=0

X=0,X=1

5a Analyse the difference between a state table, characteristic table and an 06 BTL4 Analyzing
excitation table. (OR)
Explain the operations of a 4 bit bidirectional shift register
5b Write the HDL code for up-down counter using behavioural model. 07 BTL3 Applying
6 Consider the design of a 4 bit BCD counter that counts in the following way: 13 BTL3 Applying
0000 , 0010 , 0011 , ………. , 1001 , and back to 0000.
(i) Draw the state diagram.(04)
(ii) List the next state table. (04)
(iii) Draw the logic diagram of the circuit.(05)
7 Design a sequence detector to detect the input sequence 101(overlapping ).Use 13 BTL6 Creating
JK Flip flops. (OR) Draw the block diagram of Johnson counter and explain.
8 With logic diagram explain the universal shift register as a storage device 13 BTL1 Remembering
(OR)
Explain the different types of shift registers with neat diagram.
9 Design the sequential circuit specified by the following state diagram using T 13 BTL6 Creating
flip flops

10(a) Write the design procedure for a 3-bit synchronous up counter using JK / T- 06 BTL1 Remembering
flip flop and draw the diagram. (OR)
Outline the procedure for analyzing asynchronous sequential circuit
10(b) Write the design procedure for 3 bit parallel- in serial-out shift register and 07 BTL1 Remembering
write the HDL code to realize it. (OR)
Write the VHDL code for a 4 bit binary up counter and explain
11 Design and implementation of SR Flip Flop using NOR gate 13 BTL2 Understanding
12 Illustrate a serial adder using a full adder and a flip flop (OR) 13 BTL5 Evaluating
Explain the operation of master slave flip flop and show how the race around

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 condition is eliminated in it.
13 Write the HDL description of T flip-flop , JK flip-flop ,SR flip flop and D flip- 13 BTL2 Understanding
flops.
14(a) Describe the operations of R-S flip-flop with a neat sketch 05 BTL5 Evaluating
14(b) Design a sequential circuit with two D flip flops A and B and one input When 08 BTL6 Creating
X=0 the state of the circuit remains the same. When X=1 the circuit goes
through the state transitions from 00 to 10 to 11 to 01, back to 00 and then
repeats. (8)

PART-C
Q.no Question Mark BTL Competence
1 Design a synchronous counter which counts in the sequence 15 BTL6 Creating
000,001,010,011,100,101,110,111,000 using D flip-flop.
(OR)
Design a decade counter using JKFlip Flops using IC74LS112D.
2 A sequential circuit with two D flip-flops A and B, one input x , and one output 15 BTL5 Evaluating
z is specified by the following next state and output equations: A(t+1) = A'+B,
B(t+1)=B'X, Z =A+B'
(i)Draw the logic diagram of the circuit. (05)
(ii)Derive the state table. (05)
(iii)Draw the state diagram of the circuit.(05)
(OR)
A sequential circuit with two D flip flops A and B two inputs X and Y and the
output Z is specified by the following input equations.: A(t+1)=X’Y+XA;
B(t+1)=X’B+XA; X=B
(i) Draw the logic diagram of the circuit. (08)
(ii) Derive the state table and state diagram and state whether it is a Mealy or a
Moore Machine (04 + 03)
3 Design sequence detector that detects a sequence of three or more consecutive 15 BTL6 Creating
1’s in a string of bits coming through an input line and produces an output
whenever this sequence is detected.
4 Analyze and design a sequential circuit with two T Flip flop A and B, one input 15 BTL6 Creating
x and one output z is specified by the following next state and output equation is
A(t+1)= BX’+B’X; B(t+1)=AB+BX+AX; Z=AX’+A’B’X
(i)Draw the logic diagram of the circuit. (ii) List the state table for the
sequential circuit (iii) Draw the Corresponding state diagram.

UNIT IV- ASYNCHRONOUS SEQUENTIAL LOGIC

Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and Flow Tables – Race-free State Assignment
– Hazards.
PART-A
Q.no Question BTL Competence
1 Give an example for race free state assignment BTL2 Understanding
2 Define hazards. What are the types of hazards? BTL1 Remembering
3 Define Merger graph. BTL1 Remembering
4 How the Moore circuit differ from Mealy circuit? BTL1 Remembering
5 Define flow table in asynchronous sequential circuits BTL1 Remembering
6 Compare asynchronous and synchronous sequential circuit. BTL3 Applying
7 What are race? (OR) Define primitive flow table BTL2 Understanding
8 Compare the critical race and non critical race BTL3 Applying
9 What is lockout? How it is avoided? BTL2 Understanding
10 Estimate the wave forms showing static 1 hazards (OR) Write short notes on Static BTL6 Creating

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 -1 hazards.
11 List the characteristics of fundamental mode circuit. BTL2 Understanding
12 When asynchronous sequential circuits are preferred in circuit design. BTL2 Understanding
13 Show the diagram for denounce circuit. BTL3 Applying
14 Distinguish between fundamental mode circuit and pulse mode circuit. BTL4 Analyzing
15 Point out the steps involved in the designing an asynchronous sequential circuits. BTL1 Remembering
16 How can we change the hazards into hazards free circuit? BTL5 Evaluating
17 Differentiate transition table and flow table. BTL4 Analyzing
18 Compare static and dynamic hazards. BTL4 Analyzing
19 What is meant by race free condition in sequential circuits? (OR) Is it essential to BTL5 Evaluating
have race free assignment? Justify.
20 Differentiate conventional flow table and primitive flow table. BTL4 Analyzing

PART-B
Q.no Question Mark BTL Competence
1 Explain the steps for the design of asynchronous sequential circuits with an 13 BTL5 Evaluating
example.
2 Construct the switching function F=∑m(1,3,5,7,8,9,14,15) by a static hazard 13 BTL3 Applying
free two level AND-OR gate network.
3 What are hazards and its types? How can you design a hazard free circuits, 13 BTL1 Remembering
explain with example.
4 Analyze the following clocked sequential circuit and obtain the state 13 BTL4 Analyzing
equation and state diagram.

5(a) Describe the race free state assignment procedure. 06 BTL1 Remembering
5(b) Reduce the number of state in the following state diagram. Tabulate the 07 BTL3 Applying
reduced state and draw the reduced diagram.
Present state Next state Output
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1

6 Explain the hazards in combinational circuit and sequential circuit and also 13 BTL2 Understanding
demonstrate a hazards and its removal with example.
7 Discuss about Pulse mode & Fundamental mode asynchronous sequential 13 BTL6 Creating

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 circuits
8 Discuss in detail the procedure for reducing the flow table with an example. 13 BTL6 Creating
9(a) Explain the two types of asynchronous sequential circuit with suitable 06 BTL2 Understanding
example.
9(b) What is flow table? Explain with suitable example. 07 BTL1 Remembering
10(a) What is the objective of state assignment in asynchronous circuit? Explain 06 BTL1 Remembering
how race to be avoided with an example.
10(b) Summarize about static, dynamic and essential hazards in asynchronous 07 BTL2 Understanding
sequential circuits
11 Consider the asynchronous sequential circuits which is driven by the pulses, 13 BTL4 Analyzing
as in the following figure. Analyse the circuit

12 Analyze the fundamental mode asynchronous sequential circuit given in the 13 BTL4 Analyzing
following figure.

13 Explain with a neat example for minimization of primitive flow table. 13 BTL4 Analyzing
14 Design a circuit with inputs A and B to give an output Z=1 when AB=11 13 BTL6 Creating
but only if A becomes 1before B, by drawing total state diagram, primitive
flow table and output map in which transient state is included.

PART-C
Q.no Question Mark BTL Competence
1 An asynchronous sequential circuit is described by the following excitation and 15 BTL5 Evaluating
output function. Y=X1X2+(X2+X3)Y and Z=Y
i. Draw the logic diagram of the circuit. (06)
ii. Derive the transition table and output map.(06)
iii. Describer the behaviour of the circuit.(03)
2 Design an asynchronous sequential circuit with inputs X1 and X2 and one 15 BTL6 Creating
output Z. Initially and at any time if both the inputs are 0, output is equal to
0.When X1 or X2 becomes 1, Z becomes 1. When Second input also becomes 1,
Z=0; The output stays at 0 until circuit goes back to initial state.

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 3 An asynchronous sequential circuit is described by the following excitation and 15 BTL5 Evaluating
output function. X = (Y1Z1'W2)X + (Y1'Z1W2') & S = X'
i. Draw the logic diagram of the circuit. (06)
ii. Derive the transition table and output map.(06)
iii. (iii) Describe the behavior of the circuit. (03)
4 Design an asynchronous sequential circuit with two input x and y and with one 15 BTL6 Creating
output z whenever y is 1, input x is transferred to z. When y is 0, the output
does not change for any change in x. Use SR latch for implementation of the
circuit.

UNIT V - MEMORY AND PROGRAMMABLE LOGIC

RAM – Memory Decoding – Error Detection and Correction - ROM - Programmable Logic Array – Programmable Array Logic –
Sequential Programmable Devices.

PART-A
Q.no Question BTL Competence
1 What is memory decoding? BTL1 Remembering
2 Define ASIC. BTL1 Remembering
3 Justify whether PAL is same as PLA. BTL5 Evaluating
4 What is volatile memory? Give example. BTL1 Remembering
5 Differentiate between EEPROM and PROM. BTL4 Analyzing
6 How to detect double error and correct single error? BTL1 Remembering
7 What is memory address register? BTL1 Remembering
8 What is PLA in digital circuit? BTL2 Understanding
9 A seven bit hamming code is received as 1111110. What is the correct code? BTL3 Applying
10 List the types of memories. BTL2 Understanding
11 Define combinational PLD. BTL1 Remembering
12 Differentiate a DRAM and SRAM. BTL5 Evaluating
13 Develop the maximum range of a memory that can be accessed using 10 address BTL3 Applying
lines.
14 Identify the comparison between EPROM and PLA BTL3 Applying
15 Differentiate error detection and correction technique. (OR) What are error BTL4 Analyzing
detecting code? Give examples.
16 Give the details about write and read operations in RAM. BTL2 Understanding
17 Design the logic diagram of a memory cell. BTL6 Creating
18 Write down the different types of PLDs. (OR) List the advantages of using BTL2 Understanding
sequential programmable devices.
19 Classify the types of RAM. BTL2 Understanding
20 Differentiate between PLA and ROM. BTL4 Analyzing

PART-B
Q.no Question Mark BT L Competence
1 Implement the following function using PLA A(X,Y,Z)=∑m(1,2,4,6), 13 BTL5 Evaluating
B(X,Y,Z)=∑m(0,1,6,7),
C(X,Y,Z)=∑m(2,6)
2 Explain in detail about the Programmable Logic Array & Programmable 13 BTL1 Remembering
array logic.
3 Design a BCD to Excess 3 code converter and implement using suitable 13 BTL6 Creating
PLA.
4 Recall the concept of working and application of semiconductor memories. 13 BTL1 Remembering
5(a) Write short notes on Address Multiplexing. 06 BTL2 Understanding
5(b) Briefly discuss the sequential programmable devices. 07 BTL2 Understanding

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 6(a) Implement the following Two Boolean function with a PLA 05 BTL5 Evaluating
F1=AB'+AC'+A'BC' F2=(AC+BC+AB)'
6(b) Give the Internal block diagram of 4 x 4 RAM. (OR) 08 BTL2 Understanding
Explain the logical construction of a 256*8 RAM using 64*8 RAM chips
7 Implement the following using PAL F1(A,B,C)= ∑(1,2,4,6); F2(A,B,C) 13 BTL5 Evaluating
=∑(0,1,6,7) ; F3(A,B,C)= ∑(1,2,3,5,7)
8 Design a combinational circuit using ROM that accepts a three bit binary 13 BTL6 Creating
number and outputs a binary number equal to the square of the input
number.
9 Draw a neat sketch showing implementation of Z1= ab’d’e + a’b’c’e + bc 13 BTL3 Applying
+ de, Z2= a’c’e, Z3=bc + de + c’d’e + db and Z4=a’c’e + ce using 5*8*4
PLA.
10(a) How to implement the two following Boolean functions using 8X2 PROM 06 BTL1 Remembering
10(b) Construct the following two Boolean functions using PLA with 3 inputs, 4 07 BTL3 Applying
Product terms, and 2 outputs. F1=∑m(3,5,6,7) and F2=∑m(1,2,3,4)
11 Implement the following using PAL 13 BTL5 Evaluating
W(A,B,C,D) = ∑(0,2,6,7,8,9,12,13);
X(A,B,C,D) =∑(0,2,6,7,8,9,12,13,14) ;
Y(A,B,C,D) = ∑(2,3,8,9,10,12,13);
Z(A,B,C,D)= ∑(1,3,4,6,9,12,14);
12 (a) List the features of PROM, PAL and PLA & Discuss the sequential 09 BTL1 Remembering
programmable devices
12 (b) Compare PROM, PLA, PAL 04 BTL4 Analyzing
13(a) Given the 8 bit data word 10011010 generates the 13 bit composite word for 04 BTL4 Analyzing
the Hamming code that corrects single errors and detect double errors.
13(b) With neat diagrams describe the working principle of Programmable Array 09 BTL4 Analyzing
Logic.
14 Discuss the various types of RAM, ROM and PLD with architecture. 13 BTL2 Understanding

PART-C
Q.no Question Mark BT L Competence
1(a) Design the following Boolean function using 8X2 PROM. 06 BTL6 Creating
F1=∑m(3,5,6,7) F2=∑m(1,2,3,4)
1(b) Implement the combinational circuit having the shown truth table , using 09 BTL6 Creating
PLA
A B C F1 F2
0 0 0 1 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 0 1
2 Design a 16 bit RAM array (4X4 RAM) and explain the operation. 15 BTL6 Creating
3 Explain about error detection and correction using 15 BTL5 Evaluating
Hamming codes.
4 The following message have been coded in the even parity hamming code and 15 BTL5 Evaluating
transmitted through a noisy channel. Decode the message assuming that at most a
single error occurred in each codeword.
i) 1001001 (04) ii) 0111001 (04)
iii) 1110110 (04) iv) 0011011 (03)

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