VTU - Practical Book - Part A - 04-08-2009

Implementation Design Ideas
for
CMOS VLSI Practicals
as per Syllabus of
VTU, Karnataka
Part - A
ASIC Digital Design
This page is intentionally left blank
VTU 2009 Part A
ASIC Digital Design
Table of Contents
Introduction to Xilinx ISE Software for Digital Logic Design ....................................... 4
Experiment 1: Logic Inverter .................................................................................... 11
Experiment 2: Transmission Gate ............................................................................ 14
Experiment 3: Digital Gates...................................................................................... 18
Experiment 4: Flip Flops........................................................................................... 22
Experiment 5: Adders............................................................................................... 27
Part A: Serial Adder ........................................................................................... 27
Part B: Parallel Adder ........................................................................................ 31
Experiment 6: Counters............................................................................................ 35
Part A: Synchronous Counter ............................................................................ 35
Note: To be performed by studentPart B: Asynchronous Counter ..................... 35
Part B: Asynchronous Counter .......................................................................... 36
Note: To be performed by studentExperiment 7: Successive Approximation
Register(SAR) .......................................................................................................... 36
Experiment 7: Successive Approximation Register(SAR) ........................................ 37
Reference Software:
Xilinx ISE webpack 10.1
VTU 2009 Part A
ASIC Digital Design
Introduction to Xilinx ISE Software for Digital Logic Design

Creating New Project
Step (1): Open software and click on NEW PROJECT from file menu
Step (2): Write project name and specify location for project.
VTU 2009 Part A
ASIC Digital Design
Step (3): Specify target device technology and select your desired device.
Step (4): Create NEW SOURCE file.
(Example shown is of D type Flip-Flop)
VTU 2009 Part A
ASIC Digital Design
Step (5): Specify the input & outputs in design

Step (6): Describe the code for the design
VTU 2009 Part A
ASIC Digital Design
Step (7): For TESTBENCH. Create NEW SOURCE FILE
Step (8): Select the source file for TESTBENCH
VTU 2009 Part A
ASIC Digital Design
Step (9): Set the timing parameter in test bench. Set values carefully.
Step (10): Click on input pins to generate desired input test pattern.
VTU 2009 Part A
ASIC Digital Design
Step (11): Goto SOURCE TAB in software, and select simulation mode.
Step (12): Not select the test bench file and run the simulation process
VTU 2009 Part A
ASIC Digital Design
Step (13): Verify the results
Zoom in results
Step (14): Run VIEW RTL NETLIST command to check RTL schematic results
VTU 2009 Part A
10
ASIC Digital Design
Experiment 1: Logic Inverter

Aim: To write a Verilog code for Inverter and Synthesize using Spartan-3 XC3S50 OR
XC3S400 device.
Logic symbol:
Verilog Code:
// Inverter Design
module Inverter(
input a,
output y
);
assign y = ~a;
endmodule
VTU 2009 Part A
11
ASIC Digital Design
RTL Schematic Generated after Synthesis:
Synthesis Results:
======================================================================
*
Final Report
*
======================================================================
Final Results
RTL Top Level Output File Name : Inverter.ngr
Top Level Output File Name
: Inverter
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:2
Cell Usage :
# BELS
:1
#
INV
:1
# IO Buffers
:2
#
IBUF
:1
#
OBUF
:1
======================================================================
VTU 2009 Part A
12
ASIC Digital Design
Timing Report:
Pad to Pad
---------------+---------------+---------+
Source Pad
|Destination Pad| Delay |
---------------+---------------+---------+
a
|y
|
6.289|
---------------+---------------+---------+
Simulation Result:
Post-layout or gate-level verification of design (Full view)
VTU 2009 Part A
13
ASIC Digital Design
Experiment 2: Transmission Gate

Aim: To write a Verilog code for Transmission gate and Synthesize using Spartan-3
XC3S50 OR XC3S400 device.
Specifications:
Design with Output enable, direction control and of 8bit size.
Logic symbol:
Verilog Code:
module t_gate(a,b,enable,dir);
input enable,dir;
inout [7:0] a,b;
wire [7:0] a , b;
//-------------Code Starts Here------// b --> a
assign a = (enable == 1'b0 && dir == 1'b1) ? b : 8'hzz;
// a --> b
assign b = (enable == 1'b0 && dir == 1'b0) ? a : 8'hzz;
endmodule
VTU 2009 Part A
14
ASIC Digital Design
Synthesis Results:
======================================================================
*
Final Report
*
======================================================================
Final Results
RTL Top Level Output File Name : t_gate.ngr
: t_gate
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 18
Cell Usage :
# BELS
:2
#
LUT2
:2
# IO Buffers
: 18
#
IBUF
:2
#
IOBUF
: 16
======================================================================
Device utilization summary:
Selected Device : 3s50tq144-4
Number of Slices:
Number of 4 input LUTs:
Number of IOs:
Number of bonded IOBs:
1 out of 768 0%
2 out of 1536 0%
18
18 out of 97 18%
VTU 2009 Part A
15
ASIC Digital Design
Timing Report:
Pad to Pad
---------------+---------------+---------+
Source Pad
---------------+---------------+---------+
a<0>
|b<0>
|
6.060|
a<1>
|b<1>
|
6.060|
a<2>
|b<2>
|
6.060|
a<3>
|b<3>
|
6.060|
a<4>
|b<4>
|
6.060|
a<5>
|b<5>
|
6.060|
a<6>
|b<6>
|
6.060|
a<7>
|b<7>
|
6.060|
b<0>
|a<0>
|
6.060|
b<1>
|a<1>
|
6.060|
b<2>
|a<2>
|
6.060|
b<3>
|a<3>
|
6.060|
b<4>
|a<4>
|
6.060|
b<5>
|a<5>
|
6.060|
b<6>
|a<6>
|
6.060|
b<7>
|a<7>
|
6.060|
dir
|a<0>
|
6.954|
dir
|a<1>
|
6.954|
dir
|a<2>
|
6.954|
dir
|a<3>
|
6.954|
dir
|a<4>
|
6.954|
dir
|a<5>
|
6.954|
dir
|a<6>
|
6.954|
dir
|a<7>
|
6.954|
dir
|b<0>
|
6.954|
dir
|b<1>
|
6.954|
dir
|b<2>
|
6.954|
dir
|b<3>
|
6.954|
dir
|b<4>
|
6.954|
dir
|b<5>
|
6.954|
dir
|b<6>
|
6.954|
dir
|b<7>
|
6.954|
enable
|a<0>
|
6.954|
enable
|a<1>
|
6.954|
enable
|a<2>
|
6.954|
enable
|a<3>
|
6.954|
enable
|a<4>
|
6.954|
enable
|a<5>
|
6.954|
enable
|a<6>
|
6.954|
enable
|a<7>
|
6.954|
enable
|b<0>
|
6.954|
enable
|b<1>
|
6.954|
enable
|b<2>
|
6.954|
enable
|b<3>
|
6.954|
enable
|b<4>
|
6.954|
enable
|b<5>
|
6.954|
enable
|b<6>
|
6.954|
enable
|b<7>
|
6.954|
---------------+---------------+---------+
VTU 2009 Part A
16
ASIC Digital Design
Simulation Result:
Power Consumption Report:

Power summary
|
I(mA)
|
P(mW)
|
---------------------------------------------------------------Total estimated power consumption
|
|
24 |
--Total Vccint
1.20V |
5 |
6 |
Total Vccaux
2.50V |
7 |
18 |
Total Vcco25
2.50V |
0 |
0 |
--IOs
|
0 |
0 |
Inputs
|
0 |
0 |
Logic
|
0 |
0 |
Signals
|
0 |
0 |
--Quiescent Vccint
1.20V |
5 |
6 |
Quiescent Vccaux
2.50V |
7 |
18 |
VTU 2009 Part A
17
ASIC Digital Design
Experiment 3: Digital Gates

Aim: To write a Verilog code for basic & universal gates and Synthesize using Spartan-3
Specifications:
Design a 2-bit XOR, NAND, and AND gate.
Logic symbol:
Verilog Code:
module gates(
input a,
input b,
output gate_NAND,
output gate_XOR,
output gate_AND
);
assign gate_XOR = a ^ b;
assign gate_AND = a & b;
assign gate_NAND = ~(a & b);
endmodule
VTU 2009 Part A
18
ASIC Digital Design
Synthesis Results:
======================================================================
*
Final Report
*
======================================================================
Final Results
RTL Top Level Output File Name : gates.ngr
: gates
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 5
Cell Usage :
# BELS
: 3
#
LUT2
: 3
# IO Buffers
: 5
#
IBUF
: 2
#
OBUF
: 3
======================================================================
Number of Slices:
Number of IOs:
VTU 2009 Part A
3
5
5
out of
out of
768
1536
0%
0%
out of
97
5%
19
ASIC Digital Design
Timing Report:
Pad to Pad
---------------+---------------+---------+
Source Pad
---------------+---------------+---------+
a
|gate_AND
|
7.720|
a
|gate_NAND
|
8.037|
a
|gate_XOR
|
7.520|
b
|gate_AND
|
7.528|
b
|gate_NAND
|
8.206|
b
|gate_XOR
|
7.249|
---------------+---------------+---------+
To see timing results open *.TWR file from your project folder.
For Eb. gates.twr or FF_All.twr
VTU 2009 Part A
20
ASIC Digital Design
Simulation Result:

Power summary
|
I(mA)
|
P(mW)
|
|
|
24 |
--Total Vccint
1.20V |
5 |
6 |
Total Vccaux
2.50V |
7 |
18 |
Total Vcco25
2.50V |
0 |
0 |
--Inputs
|
0 |
0 |
Logic
|
0 |
0 |
Outputs
|
Vcco25 |
0 |
0 |
Signals
|
0 |
0 |
--Quiescent Vccint
1.20V |
5 |
6 |
Quiescent Vccaux
2.50V |
7 |
18 |
VTU 2009 Part A
21
ASIC Digital Design
Experiment 4: Flip Flops

Aim: To write a Verilog code for RS, D, JK, MS & T flip flops and Synthesize using Spartan3 XC3S50 OR XC3S400 device.
Specifications:
Write code for RS, D, JK, MS & T flip flops.
Logic symbol:
Verilog Code:
module FF_All(
input clk,
// Inputs for Flip-Flops
input J,K,
input R,S,
input D,
input set, reset,
input T_En,
// Outputs for Flip-Flops
output Q_JK, Q_JK_bar, // JK
output Q_RS,Q_RS_bar,
output Q_D,Q_D_bar,
output Q_MS,Q_MS_bar,
output Q_T,Q_T_bar
);
// RS
// D
// MS
// T
// Internal Variables
reg q_jk_temp;
reg q_rs_temp,q_rs_bar_temp;
reg q_d_temp;
reg q_t_temp;
reg q_ms_temp;
// JK Flip-Flop description
always@(posedge clk)
begin
if (J==1'b0 && K==1'b1)
q_jk_temp = 1'b0;
else if(J==1'b1 && K==1'b0)
q_jk_temp = 1'b1;
else if(J==1'b1 && K==1'b1)
q_jk_temp = ~q_jk_temp;
end
// JK Outputs assignments
assign Q_JK = q_jk_temp;
assign Q_JK_bar = ~q_jk_temp;
VTU 2009 Part A
22
ASIC Digital Design
// RS Flip-Flop description
always@(R,S)
begin
q_rs_temp = ~(S && q_rs_bar_temp);
q_rs_bar_temp = ~(S && q_rs_temp);
end
assign Q_RS
= q_rs_temp;
assign Q_RS_bar
= q_rs_bar_temp;
// D Flip-Flop description
always@(posedge clk or posedge reset or posedge set)
begin
if (reset)
// Asynchronous reset & set logic
q_d_temp = 1'b0;
else if(set)
q_d_temp = 1'b1;
else
q_d_temp = D;
end
// D-FF Outputs assignments
assign Q_D = q_d_temp;
assign Q_D_bar = ~q_d_temp;
// D Flip-Flop description
always@(negedge clk or posedge reset or posedge set)
begin
if (reset)
// Asynchronous reset & set logic
q_ms_temp = 1'b0;
else if(set)
q_ms_temp = 1'b1;
else
q_ms_temp = q_d_temp;
// stores O/P coming from D flip-flop
end
// MS-FF Outputs assignments
assign Q_MS = q_ms_temp;
assign Q_MS_bar = ~q_ms_temp;
// T Flip-Flop description
always@(posedge clk)
begin
if (T_En)
q_t_temp = ~q_t_temp;
end
// T-FF Outputs assignments
assign Q_T = q_t_temp;
assign Q_T_bar = ~q_t_temp;
endmodule
VTU 2009 Part A
23
ASIC Digital Design
Synthesis Results:
======================================================================
*
Final Report
*
======================================================================
Final Results
Design Statistics
# IOs
: 19
Cell Usage :
# BELS
: 10
#
INV
:5
#
LUT2
:5
# FlipFlops/Latches
:5
#
FDCP
:2
#
FDCP_1
:1
#
FDE
:1
#
FDRSE
:1
# Clock Buffers
:1
#
BUFGP
:1
# IO Buffers
: 17
#
IBUF
:7
#
OBUF
: 10
======================================================================
Number of Slices:
Number of Slice Flip Flops:
Number of IOs:
IOB Flip Flops:
Number of GCLKs:
VTU 2009 Part A
4
10
19
18
1
1
out of
out of
out of
768
1536
1536
0%
0%
0%
out of
97
18%
out of
12%
24
ASIC Digital Design
Timing Report:
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
| Setup to | Hold to
|
| Clock |
Source
| clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
D
|
3.426(R)|
0.779(R)|clk_BUFGP
|
0.000|
J
|
2.893(R)|
-0.324(R)|clk_BUFGP
|
0.000|
K
|
2.724(R)|
-0.174(R)|clk_BUFGP
|
0.000|
T_En
|
1.216(R)|
0.161(R)|clk_BUFGP
|
0.000|
------------+------------+------------+------------------+--------+
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) |
| Clock |
Destination |
to PAD
|Internal Clock(s) | Phase |
------------+------------+------------------+--------+
Q_D
|
7.678(R)|clk_BUFGP
|
0.000|
Q_D_bar
|
8.166(R)|clk_BUFGP
|
0.000|
Q_JK
|
8.128(R)|clk_BUFGP
|
0.000|
Q_JK_bar
|
8.518(R)|clk_BUFGP
|
0.000|
Q_MS
|
8.831(F)|clk_BUFGP
|
0.000|
Q_MS_bar
|
9.155(F)|clk_BUFGP
|
0.000|
Q_T
|
9.525(R)|clk_BUFGP
|
0.000|
Q_T_bar
|
8.857(R)|clk_BUFGP
|
0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock
|Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk
|
1.713|
|
1.617|
|
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad
---------------+---------------+---------+
S
|Q_RS
|
7.945|
S
|Q_RS_bar
|
7.360|
---------------+---------------+---------+
VTU 2009 Part A
25
ASIC Digital Design
Simulation Result:

Power summary
|
I(mA)
|
P(mW)
|
|
Number of error messages: 0
Number of warning messages: 3
Number of info messages: 1
1.20V
Total Vccaux
Total Vcco25
2.50V
2.50V
--Clocks
Inputs
Logic
Outputs
Vcco25
Signals
--Quiescent Vccint
1.20V
Quiescent Vccaux
2.50V
|
|
|
5
7
0
|
|
|
6
18
0
|
|
|
|
|
|
|
|
|
0
0
0
|
|
|
0
0
0
|
|
|
0
0
|
|
0
0
|
|
|
|
5
7
|
|
6
18
|
|
VTU 2009 Part A
26
ASIC Digital Design
Experiment 5: Adders
Part A: Serial Adder
Aim: To write a Verilog code for serial adder and Synthesize using Spartan-3 XC3S50 OR
XC3S400 device.
Specifications:
Design a 4-bit serial adder. Addition will start with a control signal Enable, the 2 numbers
would come serially to the adder. Output has to be given on a o/p register.
Logic symbol:
Verilog Code:
module adder_serial(
input clk,rst,
input en,
// on Enable, addition will start
input a,
// 4-bit adder
input b,
output [3:0] result
);
reg [3:0] y;
reg carry;
always@(posedge rst or posedge clk)
begin
if (rst)
begin
y = 4'b0;
carry = 1'b0;
end
else if (en)
begin
y[3] = y[2];
y[2] = y[1];
y[1] = y[0];
{carry,y[0]} = a + b + carry;
end
end
assign result = y;
endmodule
VTU 2009 Part A
27
ASIC Digital Design
Synthesis Results:
======================================================================
*
Final Report
*
======================================================================
Design Statistics
# IOs
:9
Cell Usage :
# BELS
:2
#
LUT3
:2
# FlipFlops/Latches
:5
#
FDCE
:5
# Clock Buffers
:1
#
BUFGP
:1
# IO Buffers
:8
#
IBUF
:4
#
OBUF
:4
======================================================================
Number of Slices:
Number of IOs:
Number of GCLKs:
VTU 2009 Part A
5
2
9
9
1
out of
out of
out of
768
1536
1536
0%
0%
0%
out of
out of
97
8
9%
12%
28
ASIC Digital Design
Timing Report:
------------+------------+------------+------------------+--------+
|
| Clock |
Source
------------+------------+------------+------------------+--------+
a
|
0.514(R)|
0.703(R)|clk_BUFGP
|
0.000|
b
|
0.610(R)|
0.625(R)|clk_BUFGP
|
0.000|
en
|
0.868(R)|
0.461(R)|clk_BUFGP
|
0.000|
------------+------------+------------+------------------+--------+
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) |
| Clock |
Destination |
to PAD
------------+------------+------------------+--------+
result<0>
|
8.194(R)|clk_BUFGP
|
0.000|
result<1>
|
8.911(R)|clk_BUFGP
|
0.000|
result<2>
|
8.858(R)|clk_BUFGP
|
0.000|
result<3>
|
8.825(R)|clk_BUFGP
|
0.000|
------------+------------+------------------+--------+
---------------+---------+---------+---------+---------+
Source Clock
---------------+---------+---------+---------+---------+
clk
|
1.912|
|
|
|
---------------+---------+---------+---------+---------+
VTU 2009 Part A
29
ASIC Digital Design
Simulation Result:

Power summary
|
I(mA)
|
P(mW)
|
---------------------------------------------------------------Total estimated pow
Number of error messages: 0
Number of warning messages: 3
Number of info messages: 1
Total Vccint
1.20V |
Total Vccaux
2.50V
Total Vcco25
2.50V
--Clocks
Inputs
Logic
Outputs
Vcco25
Signals
--Quiescent Vccint
1.20V
Quiescent Vccaux
2.50V
|
|
7
0
|
|
6 |
18 |
0 |
|
|
|
|
|
|
0
0
0
|
|
|
0
0
0
|
|
|
0
0
|
|
0
0
|
|
|
|
5
7
|
|
6
18
|
|
VTU 2009 Part A
30
ASIC Digital Design
Part B: Parallel Adder

Aim: To write a Verilog code for parallel adder and Synthesize using Spartan-3 XC3S50 OR
XC3S400 device.
Specifications:
Design a 4-bit serial adder with Carry input.
Logic symbol:
A
4
B
4
Result
Cin
Verilog Code:
module Adder_Parallel(
input [3:0] a,b,
input cin,
output [4:0] y
);
assign y = a + b + cin;
endmodule
VTU 2009 Part A
31
ASIC Digital Design
Synthesis Results:
======================================================================
*
Final Report
*
======================================================================
Design Statistics
# IOs
: 14
Cell Usage :
# BELS
: 12
#
LUT2
:4
#
MUXCY
:4
#
XORCY
:4
# IO Buffers
: 14
#
IBUF
:9
#
OBUF
:5
======================================================================
Number of Slices:
Number of IOs:
4
14
14
VTU 2009 Part A
out of
out of
768
1536
0%
0%
out of
97
14%
32
ASIC Digital Design
Timing Report:
Pad to Pad
---------------+---------------+---------+
Source Pad
---------------+---------------+---------+
a<0>
|y<0>
|
8.906|
a<0>
|y<1>
|
9.638|
a<0>
|y<2>
|
9.500|
a<0>
|y<3>
|
9.503|
a<0>
|y<4>
|
8.449|
a<1>
|y<1>
|
9.301|
a<1>
|y<2>
|
9.607|
a<1>
|y<3>
|
9.610|
a<1>
|y<4>
|
8.556|
a<2>
|y<2>
|
8.642|
a<2>
|y<3>
|
9.265|
a<2>
|y<4>
|
8.436|
a<3>
|y<3>
|
9.158|
a<3>
|y<4>
|
8.773|
b<0>
|y<0>
|
8.386|
b<0>
|y<1>
|
9.118|
b<0>
|y<2>
|
8.980|
b<0>
|y<3>
|
8.983|
b<0>
|y<4>
|
7.929|
b<1>
|y<1>
|
8.705|
b<1>
|y<2>
|
9.011|
b<1>
|y<3>
|
9.014|
b<1>
|y<4>
|
7.960|
b<2>
|y<2>
|
8.028|
b<2>
|y<3>
|
8.651|
b<2>
|y<4>
|
7.822|
b<3>
|y<3>
|
8.430|
b<3>
|y<4>
|
8.045|
cin
|y<0>
|
9.874|
cin
|y<1>
|
9.986|
cin
|y<2>
|
9.848|
cin
|y<3>
|
9.851|
cin
|y<4>
|
8.797|
---------------+---------------+---------+
For eg. gates.twr or Adder_Parallel.twr
VTU 2009 Part A
33
ASIC Digital Design
Simulation Result:
Post-layout or gate-level verification of design (Zoom in view)

Power summary
|
I(mA)
|
P(mW)
|
|
|
24 |
--Total Vccint
1.20V |
5 |
6 |
Total Vccaux
2.50V |
7 |
18 |
Total Vcco25
2.50V |
0 |
0 |
--Inputs
|
0 |
0 |
Logic
|
0 |
0 |
Outputs
|
Vcco25 |
0 |
0 |
Signals
|
0 |
0 |
--Quiescent Vccint
1.20V |
5 |
6 |
Quiescent Vccaux
2.50V |
7 |
18 |
VTU 2009 Part A
34
ASIC Digital Design
Experiment 6: Counters
Part A: Synchronous Counter
Aim: To write a Verilog code for Synchronous Counter and Synthesize using Spartan-3
Specifications:
Design a 4-bit synchronous counter with asynchronous reset and enable.
Verilog Code:
// 4-bit Synchronous counter
module Syn_cntr_4_bit (
out ,
en ,
clk ,
rst
// Output of the counter

// Enable for the counter
// clock input
// reset input
);
//----------Output Ports-------------output [3:0] out;
//------------Input Ports-------------input en, clk, rst;
reg [3:0] out;
always @(posedge clk or posedge rst)
begin
if (rst) begin // active high reset
out <= 4'b0 ;
end
else if (en)
out <= out + 1;
end
endmodule
Note: To be performed by student
VTU 2009 Part A
35
ASIC Digital Design
Part B: Asynchronous Counter

Aim: To write a Verilog code for Asynchronous Counter and Synthesize using Spartan-3
Specifications:
Design a 4-bit asynchronous counter.
Verilog Code:
// Asynchronous 4-bit Counter
module Async_cntr_4bit(clk,q,rst);
input clk,rst;
output [3:0] q;
reg q0,q1,q2,q3;
// LSB bit
always@(posedge clk or posedge rst)
begin
if (rst)
q0 = 1'b0;
else
q0 = ~q0;
end
// O/P of LSB bit as clock to next F/F
always@(negedge q0 or posedge rst)
begin
if (rst)
q1 = 1'b0;
else
q1 = ~q1;
end
begin
if (rst)
q2 = 1'b0;
else
q2 = ~q2;
end
begin
if (rst)
q3 = 1'b0;
else
q3 = ~q3;
end
assign q = {q3,q2,q1,q0};
endmodule
Note: To be performed by student

VTU 2009 Part A
36
ASIC Digital Design
Experiment 7: Successive Approximation Register(SAR)

Aim: To write a Verilog code for SAR logic of ADC and Synthesize using Spartan-3 XC3S50
OR XC3S400 device.
Specifications:
Design a 4-bit SAR logic for 4-bit ADC, use start of conversion & end of conversion signals.
Algorithm for SAR counter:
Reset counter
i=N-1,ai=1
Update VDAC
Yes
No
Vin> VDAC
i=i-1; ai=1
ai=0
ai=1
Yes
No
i>=0?
End conversion
Verilog Code:
module SAR_Counter(
input clk,
input rst,
input comparator_in,
input SOC,
output EOC,
output [3:0] Q
);
reg[3:0] q_temp; // DAC o/p register
reg [2:0] q_cntr; // cycle counter
reg en,EOC_temp;
// Enable Control
begin
if (rst)
en = 1'b0;
else if (EOC_temp)
en = 1'b0;
else if (SOC)
en = 1'b1;
end
// End of conversion Control
begin
VTU 2009 Part A
37
ASIC Digital Design
if (rst)
EOC_temp = 1'b0;
else if (q_cntr==3'b111)
EOC_temp = 1'b1;
else
EOC_temp = 1'b0;
end
assign EOC = EOC_temp;
// Cycle Counter
begin
if (rst)
q_cntr = 3'b0;
else if (EOC_temp)
q_cntr = 3'b0;
else if (en)
q_cntr = q_cntr + 1;
end
assign Q = q_temp;
// SAR logic
begin
if (rst)
q_temp = 4'b1000;
else if (en)
begin
case (q_cntr)
3'b001 :
begin
if(comparator_in)
// Check MSB bit
q_temp[3] = q_temp[3];
else
q_temp[3] = 1'b0;
end
3'b010 : begin
q_temp[2] = 1'b1;
// Set 2nd MSB bit
end
3'b011 : begin
if(comparator_in)
// Check 2nd MSB bit
else
q_temp[2] = 1'b0;
end
3'b100 : begin
q_temp[1] = 1'b1;
// Set 3rd MSB bit
end
3'b101 : begin
if(comparator_in)
// Check 3rd MSB bit
else
q_temp[1] = 1'b0;
end
3'b110 : begin
q_temp[0] = 1'b1;
// Set LSB bit
end
VTU 2009 Part A
38
ASIC Digital Design
3'b111 : begin
if(comparator_in)
else
q_temp[0] = 1'b0;
end
default: begin
q_temp = q_temp;
end
endcase
end
else
q_temp = 4'b1000;
end
// Check LSB bit
endmodule
VTU 2009 Part A
39
ASIC Digital Design
Synthesis Results:
======================================================================
*
Final Report
*
======================================================================
Design Statistics
# IOs
:9
Cell Usage :
# BELS
: 16
#
INV
:2
#
LUT2
:3
#
LUT2_L
:1
#
LUT3
:2
#
LUT4
:5
#
LUT4_L
:3
# FlipFlops/Latches
:9
#
FDC
:4
#
FDCE
:4
#
FDPE
:1
# Clock Buffers
:1
#
BUFGP
:1
# IO Buffers
:8
#
IBUF
:3
#
OBUF
:5
======================================================================
Number of Slices:
7 out of
768
0%
9 out of
1536
0%
16 out of
1536
1%
Number of IOs:
9
9 out of
97
9%
Number of GCLKs:
1 out of
8
12%
VTU 2009 Part A
40
ASIC Digital Design
Timing Report:
-------------+------------+------------+------------------+--------+
|
| Clock |
Source
-------------+------------+------------+------------------+--------+
SOC
|
1.826(R)|
-0.326(R)|clk_BUFGP
|
0.000|
comparator_in|
2.218(R)|
0.413(R)|clk_BUFGP
|
0.000|
-------------+------------+------------+------------------+--------+
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) |
| Clock |
Destination |
to PAD
------------+------------+------------------+--------+
EOC
|
9.296(R)|clk_BUFGP
|
0.000|
Q<0>
|
8.613(R)|clk_BUFGP
|
0.000|
Q<1>
|
8.266(R)|clk_BUFGP
|
0.000|
Q<2>
|
8.174(R)|clk_BUFGP
|
0.000|
Q<3>
|
9.200(R)|clk_BUFGP
|
0.000|
------------+------------+------------------+--------+
---------------+---------+---------+---------+---------+
Source Clock
---------------+---------+---------+---------+---------+
clk
|
3.540|
|
|
|
---------------+---------+---------+---------+---------+
For eg. gates.twr or Adder_Parallel.twr
VTU 2009 Part A
41
ASIC Digital Design
Simulation Result:
Zoom in view

Power summary
|
I(mA)
|
P(mW)
|
|
|
24 |
--Total Vccint
1.20V |
5 |
6 |
Total Vccaux
2.50V |
7 |
18 |
Total Vcco25
2.50V |
0 |
0 |
--Clocks
|
0 |
0 |
Inputs
|
0 |
0 |
Logic
|
0 |
0 |
Outputs
|
Vcco25 |
0 |
0 |
Signals
|
0 |
0 |
--Quiescent Vccint
1.20V |
5 |
6 |
Quiescent Vccaux
2.50V |
7 |
18 |
VTU 2009 Part A
42

VTU - Practical Book - Part A - 04-08-2009

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Implementation Design Ideas

ASIC Digital Design

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VTU 2009 Part A

ASIC Digital Design

VTU 2009 Part A

ASIC Digital Design

Introduction to Xilinx ISE Software for Digital Logic Design

VTU 2009 Part A

ASIC Digital Design

Step (4): Create NEW SOURCE file.

(Example shown is of D type Flip-Flop)

VTU 2009 Part A

ASIC Digital Design

Step (5): Specify the input & outputs in design

Step (6): Describe the code for the design

(Example shown is of D type Flip-Flop)

VTU 2009 Part A

ASIC Digital Design

Step (7): For TESTBENCH. Create NEW SOURCE FILE

Step (8): Select the source file for TESTBENCH

VTU 2009 Part A

ASIC Digital Design

VTU 2009 Part A

ASIC Digital Design

VTU 2009 Part A

ASIC Digital Design

Step (13): Verify the results

VTU 2009 Part A

ASIC Digital Design

Experiment 1: Logic Inverter

VTU 2009 Part A

ASIC Digital Design

RTL Schematic Generated after Synthesis:

VTU 2009 Part A

ASIC Digital Design

Post-layout or gate-level verification of design (Full view)

VTU 2009 Part A

ASIC Digital Design

Experiment 2: Transmission Gate

VTU 2009 Part A

ASIC Digital Design

RTL Schematic Generated after Synthesis:

VTU 2009 Part A

ASIC Digital Design

VTU 2009 Part A

ASIC Digital Design

Post-layout or gate-level verification of design (Full view)

Post-layout or gate-level verification of design (Full view)

Power Consumption Report:

VTU 2009 Part A

ASIC Digital Design

Experiment 3: Digital Gates

VTU 2009 Part A

ASIC Digital Design

RTL Schematic Generated after Synthesis:

VTU 2009 Part A

ASIC Digital Design

VTU 2009 Part A

ASIC Digital Design

Post-layout or gate-level verification of design (Full view)

Post-layout or gate-level verification of design (Full view)

Power Consumption Report: