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-- CODIGO 1
---------------------------------------------------------------------------------------------------------------- ULA SIMPLES ---------------------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity ula_simples is
Generic (TAMANHO : integer :=4);
Port ( A : in STD_LOGIC_VECTOR (TAMANHO-1 downto 0);
B : in STD_LOGIC_VECTOR (TAMANHO-1 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
R : out STD_LOGIC_VECTOR (TAMANHO-1 downto 0));
end ula_simples;
architecture Comportamental of ula_simples is
begin
alu : process (op,A,B)
begin
case op is
when "00" =>
R <= A + B;
when "01" =>
R <= A - B;
when "10" =>
R <= A and B;
when "11" =>
R <= A or B;
when others => R <= "00";
end case;
end process;
end Comportamental;
----------------------------------------------------------------------------------- CODIGO 2
ENTITY quest1 IS
PORT (
X
: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Y, Z
: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
W,
: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END quest1;
ARCHITECTURE arch_q1 OF quest1 IS
BEGIN
process1: PROCESS (X,Y,Z,W)
BEGIN
CASE X IS
WHEN "000" =>
W <= Y OR Z;
WHEN "001" => W <= Y AND Z;
WHEN "010" => W <= Y XOR Z;
WHEN "011"=>
W <= NOT Y;
WHEN "100" =>
W <= Y + Z;
WHEN "101" => W <= Y - Z;
WHEN "110" => W <= Y * Z;
WHEN "111"=>
W <= X ROL Y;
WHEN OTHERS => W <= ZZZ
END CASE;
END PROCESS;
END arch_q1;

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----------------------------------------------------------------------------------- CODIGO 3
ENTITY Somador_completo_n_bits IS
GENERIC (TAMANHO : integer :=4);
Port (
A : in STD_LOGIC_VECTOR(TAMANHO-1 downto 0);
B : in STD_LOGIC_VECTOR(TAMANHO-1 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR(TAMANHO-1 downto 0);
Cout : out STD_LOGIC);
END Somador_completo_n_bits;
ARCHITECTURE Comport of Somador_completo_n_bits IS
signal connector : STD_LOGIC_VECTOR(TAMANHO downto 0);
begin
loop_for : FOR i in 0 to TAMANHO-1 generate
somador_n : entity work.Somador_completo
port map ( A => A(i),
B => B(i),
Cin => connector(i),
S => S(i),
Cout => connector(i+1) );
END GENERATE;
Cout <= connector(TAMANHO);
connector(0)<='0';
END Comport;
----------------------------------------------------------------------------------- CODIGO 4
ENTITY quest3 IS
PORT ( Clk, rst, clk_en
: IN STD_LOGIC;
A , B
: IN STD_LOGIC_VECTOR (1 DownTo 0);
S : OUT STD_LOGIC_VECTOR (1 DownTo 0));
END quest3;
ARCHITECTURE arch_q3 OF quest3 IS
SIGNAL contagem : integer;
SIGNAL contagem_STD : STD_LOGIC_VECTOR (1 DownTo 0);
BEGIN
process1: PROCESS (Clk,rst, contagem, clk_enable)
BEGIN
IF rst='0' then
contagem <= 1;
elsif clk_en ='0' then
IF Clk'EVENT AND Clk='0' THEN
contagem <= contagem + 1;
END IF;
else
contagem <= contagem;
END IF;
END PROCESS;
contagem_STD <= CONV_STD_LOGIC_VECTOR(contagem,2); - - converte para binrio
process2: PROCESS (contagem,A,B)
BEGIN
CASE contagem IS
WHEN "00" =>
S <= A and not b;
WHEN "01" =>
S <= not A and b;
WHEN "10" =>
S <= not A or b;
WHEN "11"=>
S <= A or not b;
END CASE;
END PROCESS;
END arch_q3;

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----------------------------------------------------------------------------------- CODIGO 5
ENTITY FSM1 IS
PORT ( Clk
: IN STD_LOGIC;
ent2bits : IN STD_LOGIC_VECTOR (1 DownTo 0);
saida
: OUT STD_LOGIC_VECTOR (1 DownTo 0));
END FSM1;
ARCHITECTURE arch_FSM1 OF FSM1 IS
TYPE TIPO_FSM IS (A, B, C, D);
SIGNAL estado : TIPO_FSM;
BEGIN
P1: PROCESS (Clk)
BEGIN
IF Clk'EVENT AND Clk='1' THEN
CASE estado IS
WHEN A =>
if (ent2bits="01") then
estado <= B;
else
estado <= A;
end if;
saida <= "01";
WHEN B =>
if (ent2bits="10") then
estado <= C;
else
estado <= B;
end if;
saida <= "10";
WHEN C =>
if (ent2bits="11") then
estado <= D;
else
estado <= B;
end if;
saida <= "11";
WHEN D =>
if (ent2bits="00") then
estado <= A;
else
estado <= C;
end if;
saida <= "00";
END CASE;
ELSE
estado <= estado;
END IF;
END PROCESS;
END arch_FSM1;

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----------------------------------------------------------------------------------- CODIGO 6
ARCHITECTURE behavior OF TestBench IS
constant clock_period : time := 10ms;
BEGIN
-- Clock process definitions
clock_process :process
begin
clock <= '1';
wait for clock_period/2;
clock <= '0';
wait for clock_period/2;
end process;
reset_stim_proc: process
begin
reset <= '0';
wait for 10 ms;
reset <= '1';
wait;
end process;
A_stim_proc: process
begin
A <= '1'; wait for 20 ms;
A <= '0'; wait for 30 ms;
A <= '0'; wait;
end process;
B_stim_proc: process
begin
B <= '0'; wait for 10 ms;
B <= '1'; wait for 30 ms;
B <= '0'; wait;
end process;
end behavior;

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----------------------------------------------------------------------------------- CODIGO 7 ------------------- TESTBECH DO SOMADOR DE N BITS ---------------------------------------------------------------------------------------------------LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
ENTITY TB_somador_nbits IS
generic (TAMANHO : integer :=8);
END TB_somador_nbits;
ARCHITECTURE behavior OF TB_somador_nbits IS
--Inputs
signal A : std_logic_vector(TAMANHO-1 downto 0) := (others => '0');
signal B : std_logic_vector(TAMANHO-1 downto 0) := (others => '0');
signal Cin : std_logic := '0';
--Outputs
signal S : std_logic_vector(TAMANHO-1 downto 0);
signal Cout : std_logic;
signal contagem : std_logic_vector((2*TAMANHO)-1 downto 0) := (others => '0');
constant period : time := 10ns;
BEGIN
uut: entity work.somadorN_bits
GENERIC MAP (N_BITS => TAMANHO)
PORT MAP (
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout
);
count_process :process
variable cont : integer range 0 to (2**(2*TAMANHO))-1 := 0;
begin
while cont < (2**(2*TAMANHO))-1 loop
contagem <= conv_std_logic_vector(cont, 2*TAMANHO);
wait for period;
cont := cont + 1;
end loop;
end process;
A <= contagem (TAMANHO -1 DOWNTO 0);
B <= contagem (2*TAMANHO -1 downto TAMANHO);
END;

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----------------------------------------------------------------------------------- CODIGO 8
Flip Flop Tipo D
ENTITY FF_D IS
PORT ( Clk, rst, clk_en, D
: IN STD_LOGIC;
Q : OUT STD_LOGIC);
END FF_D;
ARCHITECTURE behavior OF FF_D IS
process (Clk, rst, clk_en, D)
begin
if Clk'event and Clk='1' then
if rst='1' then
Q <= '0';
elsif clk_en ='1' then
Q <= D;
end if;
end if;
end process;
end behavior;
----------------------------------------------------------------------------------- CODIGO 9
Flip Flop Tipo JK
ENTITY FF_JK IS
PORT ( Clk, rst, clk_en, J,K : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END FF_JK;
ARCHITECTURE behavior OF FF_JK IS
signal q_ant;
BEGIN
process (Clk, rst, clk_en, J, K)
begin
if Clk'event and Clk='1' then
if rst='1' then
q_ant <= '0';
elsif clk_en ='1' then
if J = '0' the
if k = '0' then
q_ant <= q_ant;
else
q_ant <= '0';
end if;
else
if k = '0' then
q_ant <= '1';
else
q_ant <= not q_ant;
end if;
end if;
end if;
Q <= q_ant;
end process;
end behavior;

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----------------------------------------------------------------------------------- CODIGO 10
Multiplexador 4:1
ENTITY MUX4_1 IS
GENERIC (TAMANHO : integer :=4);
Port (
A, B, C, D : in STD_LOGIC_VECTOR(TAMANHO-1 downto 0);
Sel : in STD_LOGIC_VECTOR(1 downto 0);
O : out STD_LOGIC_VECTOR(TAMANHO-1 downto 0));
END MUX4_1;
ARCHITECTURE behavior OF MUX4_1 IS
BEGIN
process (Clk, rst, clk_en, J, K)
BEGIN
CASE sel IS
WHEN "00" =>
O <= A;
WHEN "01" =>
O <= B;
WHEN "10" =>
O <= C;
WHEN "11"=>
O <= D;
WHEN OTHERS => O <= (OTHERS => '0');
END CASE;
END PROCESS;
end behavior;
----------------------------------------------------------------------------------- CODIGO 11
Vetor de portas AND
ENTITY vetor_and IS
GENERIC (TAMANHO : integer :=4);
Port (
A, B : in STD_LOGIC_VECTOR(TAMANHO-1 downto 0);
O : out STD_LOGIC_VECTOR(TAMANHO-1 downto 0));
END vetor_and ;
ARCHITECTURE behavior OF vetor_and IS
BEGIN
O <= A and B;
END behavior;
----------------------------------------------------------------------------------- CODIGO 12
Vetor de portas OR
ENTITY vetor_or IS
GENERIC (TAMANHO : integer :=4);
Port (
A, B : in STD_LOGIC_VECTOR(TAMANHO-1 downto 0);
O : out STD_LOGIC_VECTOR(TAMANHO-1 downto 0));
END vetor_or;
ARCHITECTURE behavior OF vetor_or IS
BEGIN
O <= A OR B;
END behavior;

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