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  • Full Adder

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    Aastha Rattan
    26 views4 pages
    This document contains VHDL code to model a full adder using data flow and behavioral modeling. The code defines the full adder entity with inputs a, b, cin and outputs sum, carry. It then implements the full adder architecture using data flow modeling, assigning sum and carry based on logic expressions of the inputs. A testbench is created to simulate the full adder by changing the input values over time.

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    This document contains VHDL code to model a full adder using data flow and behavioral modeling. The code defines the full adder entity with inputs a, b, cin and outputs sum, carry. It then implements the full adder architecture using data flow modeling, assigning sum and carry based on logic expressions of the inputs. A testbench is created to simulate the full adder by changing the input values over time.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    26 views4 pages

    Full Adder

    Uploaded by

    Aastha Rattan
    This document contains VHDL code to model a full adder using data flow and behavioral modeling. The code defines the full adder entity with inputs a, b, cin and outputs sum, carry. It then implements the full adder architecture using data flow modeling, assigning sum and carry based on logic expressions of the inputs. A testbench is created to simulate the full adder by changing the input values over time.

    Copyright:

    Attribution Non-Commercial (BY-NC)
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    of 4

    EXPERIMENT 3 Aim: VHDL CODE FOR FULL ADDER USING DATA FLOW MODELLING

    library ieee; use ieee.std_logic_1164.all; Entity full is port(a,b,cin:in bit;sum ,carry:out bit); end full; architecture fulladd of full is begin sum <=a xor b xor cin; carry <= (a and b) or (b and cin) or(cin and a); end fulladd; entity testbench is end testbench; architecture test of testbench is component full is port(a,b,cin:in bit;sum ,carry:out bit); end component; signal a,b,cin,sum,carry : bit; begin process begin a<='0'; b<='0'; cin<='0'; wait for 50 ns; a<='0'; b<='0'; cin<='1'; wait for 50 ns; a<='0'; b<='1'; cin<='0'; wait for 50 ns; a<='0'; b<='1'; cin<='1'; wait for 50 ns; a<='1'; b<='0'; cin<='0'; wait for 50 ns; a<='1'; b<='0';

    cin<='1'; wait for 50 ns; a<='1'; b<='1'; cin<='0'; wait for 50 ns; a<='1'; b<='1'; cin<='1'; wait ; end process; X:full port map(a,b,cin,sum,carry); end test;

    OUTPUT OF VHDL CODE FOR FULL ADDER USING DATA FLOW MODELLING

    EXPERIMENT 3 Aim: VHDL CODE FOR FULL ADDER USING BEHAVIOURAL MODELLING
    library ieee; use ieee.std_logic_1164.all; Entity full1 is port(a,b,cin:in bit;sum ,carry:out bit); end full1; architecture fulladd1 of full1 is begin process(a,b,cin) begin sum <=a xor b xor cin; carry <= (a and b) or (b and cin) or(cin and a); end process; end fulladd1; entity testbench is end testbench; architecture test of testbench is component full1 is port(a,b,cin:in bit;sum ,carry:out bit); end component; signal a,b,cin,sum,carry : bit; begin process begin a<='0'; b<='0'; cin<='0'; wait for 50 ns; a<='0'; b<='0'; cin<='1'; wait for 50 ns; a<='0'; b<='1'; cin<='0'; wait for 50 ns; a<='0'; b<='1'; cin<='1'; wait for 50 ns; a<='1'; b<='0'; cin<='0'; wait for 50 ns; a<='1'; b<='0';

    cin<='1'; wait for 50 ns; a<='1'; b<='1'; cin<='0'; wait for 50 ns; a<='1'; b<='1'; cin<='1'; wait ; end process; X:full1 port map(a,b,cin,sum,carry); end test;

    OUTPUT OF VHDL CODE FOR FULL ADDER USING BEHAVIOURAL MODELLING

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