Name: Tolentino, Ken R.

Date:12-04-2021

Section: CpE-3105

Laboratory No. 4

CpE 415 – Introduction to HDL

First Semester, AY 2020-2021

Create a VHDL program of the circuit design inside a 3:8 Decoder using the basic logic
gates. Then test the VHDL design program and monitor the designs behavior through
its waveform output.
 CODES IN THE EDA PLAYGROUND (DESIGN & TESTBENCH)

Design Code:

library IEEE;

use IEEE.std_logic_1164.all;

entity Alejandro is

port(

a: in std_logic;

b: in std_logic;

c: in std_logic;

x0: out std_logic;

x1: out std_logic;

x2: out std_logic;

x3: out std_logic;

x4: out std_logic;

x5: out std_logic;

x6: out std_logic;

x7: out std_logic);

end Alejandro;

architecture logic of Alejandro is

begin

process(a, b, c) is

begin

x0 <= ((not a) and (not b) and (not c));

x1 <= ((not a) and (not b) and (c));

x2 <= ((not a) and (b) and (not c));

x3 <= ((not a) and (b) and (c));

x4 <= ((a) and (not b) and (not c));

x5 <= ((a) and (not b) and (c));

x6 <= ((a) and (b) and (not c));

x7 <= ((a) and (b) and (c));

end process;

end logic;

Testbench Code:

library IEEE;

use IEEE.std_logic_1164.all;

entity Tolentino is

end Tolentino;

architecture Ken of Tolentino is

component Alejandro is

port(

a: in std_logic;

b: in std_logic;

c: in std_logic;

x0: out std_logic;

x1: out std_logic;

x2: out std_logic;

x3: out std_logic;

x4: out std_logic;

x5: out std_logic;

x6: out std_logic;

x7: out std_logic);

end component;
signal a_in, b_in, c_in, x0_out, x1_out, x2_out, x3_out, x4_out, x5_out, x6_out, x7_out:
std_logic;

begin

DUT: Alejandro port map(a_in, b_in, c_in, x0_out, x1_out, x2_out, x3_out, x4_out, x5_out,
x6_out,

x7_out);

process

begin

a_in <= '0';

b_in <= '0';

c_in <= '0';

wait for 1 ns;

a_in <= '0';

b_in <= '0';

c_in <= '1';

wait for 1 ns;

a_in <= '0';

b_in <= '1';

c_in <= '0';

wait for 1 ns;

a_in <= '0';

b_in <= '1';

c_in <= '1';

wait for 1 ns;

a_in <= '1';

b_in <= '0';

c_in <= '0';

wait for 1 ns;

a_in <= '1';

b_in <= '0';

c_in <= '1';

wait for 1 ns;

a_in <= '1';

b_in <= '1';

c_in <= '0';

wait for 1 ns;

a_in <= '1';

b_in <= '1';

c_in <= '1';

wait for 1 ns;

assert false report "---Done---" severity note;

wait;

end process;

end Ken;
 SCREENSHOTS IN EDA PLAYGROUND (CODE & EP WAVE)

Code:

EP Wave:
 TRUTH TABLE OF THE EP WAVE

A B C x0 x1 x2 x3 x4 x5 x6 x7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1