UNIVERSITY OF THE EAST

College of Engineering
Computer Engineering Department

EXPERIMENT NO. 1
Introduction to Hardware Description Language (HDL)

Course Code: NCP 3201 Program:

Course Title: Introduction to HDL Date Performed: 08/23/2022
Date Submitted: 08/23/2022
Name: Dante, Christian Joie C Professor: Engr. Nelson Rodelas

Objective/s:
1. The activity's goal is to illustrate how to utilize EDA Playground to mimic VHDL
programs.

Learning Outcomes:
At the end of the experiment, the student should be able to:
1. Run VHDL codes to EDA Playground step by step to test the method.
2. Create the design and testbench codes.
3. Develop VHDL programs for OR logic gates.
4. Construct an EPWave of an OR logic gate.

Discussion:
 EDA Playground provides engineers with direct hands-on experience with
SystemVerilog, Verilog, VHDL, C++/SystemC, and other HDL simulations. You
only need a web browser. The objective is to expedite design/testbench
development learning through better code sharing and easier access to EDA
tools and libraries. (https://eda-playground.readthedocs.io/en/latest/intro.html)

Figure 1 EDA Playground Environment

  Select VHDL as the language to develop VHDL in the EDA playground, while you
can also execute other programs like Python. EDA playground allows you to
easily compare hardware design circuit codes such as VHDL when running it to
an ISE program.
Procedures:
1. Search the website www.edaplayground.com

Website: www.edaplayground.com

2. You must first log in with your Google or Facebook account.

Choose Google and Log in to your UE Account

3. The figure below shows an empty work area. The words "testbench" are on the
left, while "design" is on the right. Languages and Libraries are also visible on the
left side of the window. Choose VHDL for your Testbench + Design.
 Choose VHDL

4. In the picture below, where it says, "Add a title to help you discover your
playground," write "CodeSample1." Also, on the "Top entity" name on the left
side of the test bench window is the same name you placed on the title, if you
recall I typed "CodeSample1."

Write “CodeSample1” in the Top Entry textbox

Write “CodeSample1” as the title

5. Next to the title text field, click private (only you can see).
 Select “Private (only you can view)”

6. In Tools & Simulations, select “Aldec Riviera Pro 2022.04”

Select “Aldec Riviera Pro 2022.04”

7. Check the Open EPWave option after Run Options, as seen in the image below.
To check for mistakes, click the save button again below the testbench and
design window. After running, check the Open EPWave box. To check for
mistakes, click the save button again below the testbench and design window.
 Check “Open EPWave after run” Click “Save”

8. After saving CodeSample1, the "library ieee; and use ieee.std logic 1164.all;" will
appear in the testbench and design area. Copy and paste the following code into
the testbench section.
9. Copy and paste the given code below on the testbench area and save.

-- Testbench for OR gate

library IEEE;
use IEEE.std_logic_1164.all;

entity CodeSample1 is
-- empty
end CodeSample1;

architecture CodeSample1TB of CodeSample1 is

-- DUT component
component Designor_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end component;

signal a, b, q: std_logic;
begin
 -- Connect DUT
DUT: Designor_gate port map(a, b, q);
process
begin
a <= '0';
b <= '0';
wait for 1 ns;

a <= '0';
b <= '1';
wait for 1 ns;

a <= '1';
b <= '0';
wait for 1 ns;

a <= '1';
b <= '1';
wait for 1 ns;

-- Clear inputs
a <= '0';
b <= '0';

wait;
end process;
end CodeSample1TB;
10. Copy and paste the following code to the design area.

-- Simple OR gate design

library IEEE;
use IEEE.std_logic_1164.all;

entity Designor_gate is
port(
a: in std_logic;
b: in std_logic;
q: out std_logic);
end Designor_gate;

architecture DesignRTL of Designor_gate is

 begin
process(a, b) is
begin
q <= a or b;
end process;
end DesignRTL;

11. Save and Run the Program.

12. In the graphic below, you can see the EPwave, which stands for EDA Playground
waveform.
Take note of the following coding errors:
• One possible mistake is incorrect spacing.
• Always log out of your EDAPlayground account after completing a program.
• Always alter the top entity's and title's names because the top entity's and title's
names must be the same. Furthermore, testbench names like SampleCode1 must
be the same as the top entity name.
• The design's name must be the same as the design's name after beginning
architecture (for example, Design or_
• There must be no spaces in the design's name.
• You must input all the codes, or an error will occur.
Activity:
1. Create the VHDL Module of NOR, AND, XOR, and XNOR gates
2. Produce the EPWave of the NOR, AND, XOR, and XNOR gates on the space
provided.
3. Write the design code. (Separate page)
4. Screenshot of EPWave for NOR, AND, XOR, and XNOR gates. (Separate page)
Question:
1. What are your observations from using EDA Playground?
 Users can edit, simulate (and observe waveforms), synthesize, and share
their HDL code using the free web program EDA Playground. Its objective
is to hasten design and testbench development learning through more
convenient code exchange and more straightforward access to simulators
and libraries.
Results:
Change the Run Time in EPAWave. Write the results in the table below. (You may
change the time value (like 1ns)).
INVERTER in 10ns
Every 10 ns A B F
10ns 0 1 n/a
20ns 1 0 n/a
30ns 1 0 n/a
40ns 1 0 n/a
50ns 1 0 n/a
60ns 1 0 n/a

NOR in 10ns
Every 10 ns A B F
10ns 0 1 0
20ns 1 0 0
30ns 1 1 0
40ns 1 1 0
50ns 1 1 0
60ns 1 1 0

AND in 10ns
Every 10 ns A B F
10ns 0 1 0
20ns 1 0 0
30ns 1 1 1
40ns 1 1 1
50ns 1 1 1
60ns 1 1 1

XOR in 10ns
Every 10 ns A B F
10ns 0 1 1
20ns 1 0 1
30ns 1 1 0
40ns 1 1 0
50ns 1 1 0
60ns 1 1 0
 XNOR in 10ns
Every 10 ns A B F
10ns 0 1 1
20ns 1 0 1
30ns 1 1 0
40ns 1 1 0
50ns 1 1 0
60ns 1 1 0

Conclusion:
Tools like Hardware Description Languages (HDLs) are crucial for contemporary digital
designers. You will be able to specify digital systems considerably more quickly than if
you had to create the entire schematic after learning SystemVerilog or VHDL. Because
adjustments necessitate code changes rather than laborious schematic rewiring, the
debug cycle is frequently completed significantly more quickly. However, if you don't
have a strong understanding of the hardware your code implies, the debug cycle can be
substantially longer when utilizing HDLs.

SCREEN SHOTS: