Name: DANTE, CHRISTIAN JOIE C.

Experiment#: 3

NCP3201-3CPE-
Course Code: Activity Title: Conditional Statement and Signals in VHDL
1A

SCREENSHOTS:

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CODES:

// Code your testbench here

library IEEE; stim: process
use IEEE.std_logic_1164.all; begin

entity Experiment_3 is I <= "00";

end Experiment_3; wait for 100 ns;

architecture Experiment_3TB of Experiment_3 is I <= "01";

wait for 100 ns;
component DECODER_SOURCE
Port (
I: in std_logic_vector (1 downto 0); I <= "10";
Y: out std_logic_vector (3 downto 0)); wait for 100 ns;
end component;

signal I: std_logic_vector (1 downto 0); I <= "11";

signal Y: std_logic_vector (3 downto 0); wait for 100 ns;

begin wait;

UUT: DECODER_SOURCE port map( end process;

I => I, end Experiment_3TB;
Y => Y);

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// Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity DECODER_SOURCE is
Port (
I: in std_logic_vector (1 downto 0);
Y: out std_logic_vector (3 downto 0));

end DECODER_SOURCE;

architecture dataflow of DECODER_SOURCE is

begin

Y(0) <= not I(0) and not I(1);

Y(1) <= not I(0) and I(1);
Y(2) <= I(0) and not I(1);
Y(3) <= I(0) and I(1);

end dataflow;

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