Name: DANTE, CHRISTIAN JOIE C.

Experiment #: 5

Course Code: NCP3201-4CPE - 1B Activity Title: Multiplexer and Demultiplexer

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CODES:
TESTBENCH:
library ieee;
use ieee.std_logic_1164.all; DESIGN:
library IEEE;
entity mux_tb is use IEEE.STD_LOGIC_1164.ALL;
end entity; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
architecture tb of mux_tb is
component MUX_SOURCE is entity MUX_SOURCE is
Port ( S : in STD_LOGIC_VECTOR (1 downto 0); Port ( S : in STD_LOGIC_VECTOR (1 downto
I : in STD_LOGIC_VECTOR (3 downto 0); 0);
O : out STD_LOGIC); I : in STD_LOGIC_VECTOR (3 downto 0);
end component; O : out STD_LOGIC);

signal S : STD_LOGIC_VECTOR(1 downto 0); end MUX_SOURCE;

signal I : STD_LOGIC_VECTOR(3 downto 0);
signal O : STD_LOGIC; architecture Behavioral of MUX_SOURCE is

begin begin
uut : MUX_SOURCE port map(
S => S, process (S,I)
I => I,
O => O); begin

stim : process
begin if (S <= "00") then
O <= I(0);
I(0) <= '0'; elsif (S <= "01") then
I(1) <= '1'; O <= I(1);
I(2) <= '0'; elsif (S <= "10") then
I(3) <= '1'; O <= I(2);
else
S <= "00";wait for 10 ns; O <= I(3);
S <= "01";wait for 10 ns;
S <= "10";wait for 10 ns; end if;
S <= "11";wait for 10 ns; end process;
wait; end Behavioral;
end process;
end tb;

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