School of Engineering

Department of Computer and Communications Engineering

Spring 2018-2019
Final Exam
CENG355-Advanced Digital Logic Design
Instructors: Dr. Rawad Abou-Assi, Dr. Abdel Mehsen Ahmad, Dr. Ali Al Ghouwayel, Dr. Ali Ibrahim,
Dr. Ali Kalakech, Dr. Mostafa Rizk, Dr. Oussama Tahan

Test Examination, June 12th, 2019

Time 11:30 – 13:30

Student Name: ______________________ ID: ______________________Section: __________

Instructions:
• Closed book/notes
• Calculators are allowed
• Answer all questions
• Total pages: 10 Question sheets

Question Mark Weight

1 30
2 55
3 15
Total 100
 School of Engineering
Department of Computer and Communications Engineering

CENG355-Advanced Digital Logic Design

Final Exam
Spring 2018-2019
June 12th, 2019, 11:30-13:30

Student Name
Student ID

Problem Grade Weight

1 30
2 55
3 15
100

Instructions
10 Question sheets
Closed Book Examination.
Do not take the staple out. The exam booklet must remain intact
Calculators are allowed
The cheating penalty will be “F” in the exam
Answer all four questions
Question 1 : Combinational Circuits (30 points)

1. The below design shows an adder/subtractor circuit built using 2-way multiplexers, full adders and
NOT gates.

O3 O2 O1 O0

a. Complete the below behavior VHDL code of a 2-way multiplexer. You MUST use IF statement
within a process. (6 points)

ENTITY mux2to1 IS
PORT ( w: IN STD_LOGIC_VECTOR (0 TO 1);
s: IN STD_LOGIC;
f: OUT STD_LOGIC);
END mux2to1;

ARCHITECTURE Behavior of mux2to1 IS

BEGIN
PROCESS (_w,s___________) (2 pts)
BEGIN

IF s=’0’ THEN (1 pt)

f<=w(0); (1.5 pt)
ELSE
f<=w(1); (1.5 pt)
END IF;

END PROCESS;
END Behavior;

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b. Assume that you already have a pre-built VHDL entity named fulladd that has its ports indicated
below. Write the structural VHDL code of the adder/subtractor circuit using generate. (14 points)

ENTITY fulladd IS
PORT ( cin, x, y : IN STD_LOGIC ;
s, cout : OUT STD_LOGIC ) ;
END fulladd;

ENTITY addsub IS

PORT (x,y : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; (1 pt)

s: IN STD_LOGIC; (1 pt)
O : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); (1 pt)
cout: OUT STD_LOGIC) ; (1 pt)

END addsub;

ARCHITECTURE Structure OF addsub IS

Signal yprime, outputmux: STD_LOGIC_VECTOR (0 TO 3); (1 pt)
Signal c: STD_LOGIC_VECTOR (0 TO 4); (1 pt)
BEGIN
yprime <= NOT(y); (1 pt)
c(0) <= s; (1 pt)
cout <= c(4); (1 pt)
G1: FOR i IN 0 TO 3 GENERATE (1 pt)
Muxes: mux2to1 PORT MAP (y(i) & yprime(i), s, outputmux(i) ) ; (2 pt)
adders: fulladd PORT MAP (c(i), x(i), outputmux(i), O(i), c(i+1)) ; (2 pt)
END GENERATE ;
END Structure;

End Structure;
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 2. Write the behavioral VHDL code of a 4-bit Tristate buffer. The 4-bit Tristate buffer has a 4-bit input,
a 4-bit output and a 1-bit enable. You MUST use PROCESS with IF statement. (10 points)

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY tristate IS
PORT ( X : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; (1 pt)
E : IN STD_LOGIC ; (1 pt)
F : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; (1 pt)
END tristate ;
ARCHITECTURE Behavior OF tristate IS
BEGIN
PROCESS (X, E) (2 pt)
BEGIN
IF E = '1' THEN (1 pt)
F<= X; (2 pt)
ELSE
F <= "ZZZZ"; (2 pt)
END IF;
END PROCESS;
END Behavior ;

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Question 2: ALU, Storage Elements, Registers and Counters (55 points)

1. Consider the below timing diagram of a D Flip Flop and a Gated D-Latch. Find which Signal (Signal
x or Signal y) corresponds to which component (D Flip Flop or Gated D-Latch). Indicate if the gated
latch is enabled when Clock equals 0 or 1 and if the flipflop is rising-edge or falling-edge triggered.
Explain your answer. (6 points)

Signal x

Signal y

Signal x is for a rising-edge triggered D Flip Flop(1.5 pt for answer + 1.5 pt for explanation)
Signal y is for a gate-latch that is high-enabled (1.5 pt for answer + 1.5 pt for explanation)

2. Complete the behavioral VHDL code of an Arithmetic Logic Unit that has 4 inputs A, B, f and EN. A
and B are 16 bits each, f is 3 bits and EN is 1 bit. The ALU has one output S that has a size of 16 bits.
The below table shows the behavior of the Logic Unit. Note that any change on any input will affect
the output. (17 points)

EN f s
0 X s will keep its value
1 000 s=A-B
1 001 s=A+B
1 010 s= B rotated 3 times to the right
1 011 s= A divided by two while keeping the sign
1 100 s is cleared
1 101 s=A⊕B
1 110 All the bits of s are set to 1
Most significant byte of s equals most significant byte of A
1 111
Least significant byte of s equals least significant byte of B

4/11
ENTITY alu IS

PORT ( f: IN STD_LOGIC_VECTOR(2 DOWNTO 0) ; (1 pt)

EN: IN STD_LOGIC; (1 pt)
A, B : IN STD_LOGIC_VECTOR (15 DOWNTO 0) ; (2 pts)
S : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ) ; (1 pt)
END alu ;

ARCHITECTURE Behavior OF alu IS

BEGIN
PROCESS ( f, EN, A, B ) (2 pts)

BEGIN
If EN=’1’ (1 pt) THEN
CASE f IS
WHEN “000” =>
S <= A-B ; (1 pt)
WHEN “000” =>
S <= A+B ; (1 pt)
WHEN “000” =>
S <= B ROR3 ; (1 pt)
WHEN “000” =>
S <= A ASR 1 ; (1 pt)
WHEN “000” =>
S <= others => ’0’ ; (1 pt)
WHEN “000” =>
S <= A XOR B ; (1 pt)
WHEN “000” =>
S <= others => ’1’ ; (1 pt)
WHEN others =>
S <= A(15 DOWNTO 8) & B(7 DOWNTO 0); (2 pts)

END CASE ;
END IF;
END PROCESS ;
END Behavior ;

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3. Complete the behavioral VHDL code of a JK Flip Flop that is rising-edge triggered. Hint: a JK flip
flop has the following truth table where Q* is the next state/output. (8 points)

J K Q*
0 0 Q
0 1 0
1 0 1
1 1 Q’

ENTITY JKflipflop IS
PORT ( JK: IN STD_LOGIC_VECTOR (0 to 1);
CLK: IN STD_LOGIC; (1 pts)
Q,Qprime: BUFFER STD_LOGIC)); (1 pts)

END JKflipflop;

ARCHITECTURE Behavior OF JKflipflop IS

BEGIN
PROCESS ( CLK (1 pts) )
BEGIN
IF CLK’EVENT AND CLK=’1’ (1 pts) THEN
WITH JK SELECT
Q <= ‘0’ WHEN “01”; (0.5 pts)
‘1’ WHEN “10”; (0.5 pts)
NOT(Q) WHEN “11”; (0.5 pts)
Q WHEN OTHERS; (0.5 pts)
WITH JK SELECT
Qprime<= ‘1’ WHEN “01”; (0.5 pts)
‘0’ WHEN “10”; (0.5 pts)
NOT(Qprime) WHEN “11”; (0.5 pts)
Qprime WHEN OTHERS; (0.5 pts)

END IF ;
END PROCESS ;
END Behavior ;

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4. Complete the behavioral VHDL code of a T Flip Flop that is falling-edge triggered. Hint: a T flip flop
has the following truth table where Q* is the next state/output. (8 points)

T Q*
0 Q
1 Q’ CLK

ENTITY Tflipflop IS
PORT ( T: IN STD_LOGIC;
CLK: IN STD_LOGIC; (1 pts)
Q: BUFFER STD_LOGIC)); (1 pts)

END Tflipflop;

ARCHITECTURE Behavior OF Tflipflop IS

BEGIN
PROCESS ( CLK ) (1 pts)
BEGIN
IF CLK’EVENT AND CLK=’0’ (1 pts) THEN
IF T=’1’ (2 pts) THEN
Q <= NOT(Q); (1 pts)
Qprime <=NOT(Qprime); (1 pts)
END IF;
END IF ;
END PROCESS ;
END Behavior ;

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5. Write the VHDL code of a N-bit (generic) parallel load up-down counter with synchronous reset.
The counter has the following inputs and outputs: (16 points)
- Inputs:
o w has a size of N bits. Default of N is 32
o direction, clock, countload each has a size of 1 bit
- Outputs:
o F has a size of N bits

The counter works like follows:

- The counter is sensitive on the rising-edge of the clock
- When countload equals zero, the counter should be counting up or counting down depending
on the value of direction
- direction = 0 → count down, direction = 1 → count up
- When countload equals one, the counter should load a value on its output F coming from its
input w
- Reset is active-low and is responsible of resetting the counter. Resetting will force the output F
to zeros if the counter is counting up or to ones if the counter is counting down.

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ENTITY pludcounter IS
GENERIC (N: INTEGER := 32); (1 pts)
PORT ( w: IN STD_LOGIC_VECTOR (N-1 DOWNTO 0);
direction, clock, countload: IN STD_LOGIC; (3 pts)
F: BUFFER STD_LOGIC_VECTOR (N-1 DOWNTO 0)); (1 pts)
END pludcounter;

ARCHITECTURE Behavior OF pludcounter IS

BEGIN
PROCESS ( clock ) (1 pts)
BEGIN
IF CLK’EVENT AND CLK=’1’ (1 pts) THEN
IF RESET = ‘0’ (1 pts) THEN
IF direction = ‘0’ THEN (1 pts)
F <= (OTHERS =>’1’); (1 pts)
ELSE
F <= (OTHERS =>’0’); (1 pts)
ENDIF;
ELSE
IF countload=’1’ (1 pts) THEN
F<= w; (1 pts)
ELSIF direction =’0’ THEN (1 pts)
F<=F-1; (1 pts)
ELSE
F<=F+1; (1 pts)
ENDIF;
ENDIF;
END IF ;
END PROCESS ;
END Behavior ;

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Question 3: Hardware Design (15 points)

1. Consider the following System that consists of four 8-bit registers and a control unit.
The control unit has
- 1 Bit Function input that goes high for only one clock cycle whenever a specific operation should
be performed by the circuit
- Clock input
- Two output signals called Extern1 and Extern2 that control the Tristate buffers of Data1 and Data2
- Output signals called R0in, R1in, R2in and R3in that control the registers R0, R1, R2 and R3. When
Rxin = 1 then register Rx will read the data located on its input {x=0, 1, 2 or 3}.
Output signals R0out, R1out, R2out and R3out that control the Tristate buffers of Registers R0, R1,
R2 and R3

Data1 Data2
Extern1 Extern2

R3in

a) For the above design, we want to implement an operation in which R0 receives data from Data1
then R2 receives data from Data2. When this is done, the control circuit should copy the content
of R0 to R3 then copy the content of R2 to R1.
.
i. How many clock cycles are required to perform the above operation? Justify your answer.
Tell what happens on each clock. (5 points)
Cycle1: Copy data1 to R0
Cycle2: Copy data2 to R2
Cycle3: Copy R0 to R3
Cycle4: Copy R2 to R1

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 ii. At each clock cycle write down the value of the below control signals. Note the
below columns may or may not be all needed (6 points)

Clock Cycle Number 1 2 3 4 5 6 7 8

R0in 1
R1in 1
R2in 1
R3in
R0out 1
R1out
R2out 1
R3out 1
Extern1 1
Extern2 1
0.75 pts per correctly placed 1

b) Design the control unit circuit using Logic elements i.e. using D-Flip-flops. (4 points)

1 point per correctly placed and connected flipflop

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