Faculty of Media Engineering and Technology

Dept. of Computer Science and Engineering

Dr. Milad Ghantous

CSEN 605: Digital System Design

Winter 2020

Quiz 2

Name: …………………………………………………………………………………………………
Application ID: …………………………………………………………………….………………
Group: …………………………………………………………………………………………………

Grading scheme
Exercise 1 20 pts
Exercise 2 30 pts
Total 50 pts

Instructions:
 This is a closed book examination.
 Calculators are not allowed.
 Duration: 30 min. Kindly stop writing when told so.
 This booklet comprises XX pages including the cover page.

Good luck
Exercise 1- (20 pts)
A) Write the truth table of a 2-1 multiplexer (w0, w1 inputs and select line S, output f) and derive
its minimized SoP using a k-map or any other way you deem appropriate.
B) Complete the code in VHDL to implement this mux using the SoP found in part A.
Hints:
 Use W0 and W1 as inputs, S as select line, F as output.
 Call it mux2to1
 Also create a package for it call it mux2to1_Package

ENTITY mux2to1 IS
PORT ( W0, W1, S: IN STD_LOGIC;
F: OUT STD_LOGIC);
END mux2to1;

ARCHITECTURE behav OF mux2to1 IS

BEGIN

END behav;

PACKAGE mux2to1_package IS

END mux2to1_package;

2
Solution:
A)
s W0 W1 f
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

Sop: (using k-map) or any other way.

f= s’w0 + sw1

B) 10 pts
ENTITY mux2to1 IS
PORT ( W0, W1, S: IN STD_LOGIC;
F: OUT STD_LOGIC);
END mux2to1;

ARCHITECTURE behav OF mux2to1 IS

BEGIN
F <= (NOT S AND W0) OR (S AND W1);
END behav;

PACKAGE mux2to1_package IS
COMPONENT mux2to1
PORT(W0,W1,S: IN STD_LOGIC;
F: OUT STD_LOGIC);
END COMPONENT
END mux2to1_package

3
Exercise 2 (30 pts)
You are going to build a 2-bit register shown below using two 1-bit D-Flip flops
and two 2-1 multiplexers.

The register is used to hold a 2-bit number.

It has 4 inputs:
 Two D inputs, D1 and D0, representing the 2-bit number.
 A load signal called “load” used to select one of two modes for the
register: either hold the previous value in the flip flops, or load a new one
using the inputs D1 and D0
 A clock signal “clk”

It has 2 outputs: Q1 and Q0

Each D-flip flop has 2 inputs: D and clk, and 1 output Q.

A) Write the VHDL entity Reg2 of the above register.

4
 Solution:
Entity Reg2 is
Port (D1,D0,load,clk: IN std_logic;
Q1,Q0: OUT std_logic);
End reg2;

B) Write the architecture called Reg2_arch.

In this part, assume you have a package representing a 1-bit D-flip flop entity
called dff having ports (D, CLK, Q).
Also you will use the multiplexer package you created in exercise 1.
 Assume all libraries and packages are included at the beginning of the
code.
 Use the (x=>y) style in the port map.

Solution:

Architecture reg2_arch of reg2 is

Signal: f1, f0, i1, i0: std_logic;
Begin

Mux1: mux2to1 PORT MAP (W0=>i1, W1=>D1, S=>load, F=>f1);

FF1: dff PORT MAP (D=>f1, CLK=>clk, Q=>i1);

Mux0: mux2to1 PORT MAP (W0=>i0, W1=>D0, S=>load, F=>f0);

FF0: dff PORT MAP (D=>f0, CLK=>clk, Q=>i0);

Q1 <= i1;
Q0 <= i0;

END reg2_arch