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CH340g
• Input/out voltages
max3222
module mux32two
(input [31:0] i0,i1,
input sel,
output [31:0] out);
parameter BYTE_SIZE = 8,
BYTE_MASK = BYTE_SIZE - 1;
Next
State
Memory
Device Current
State Combinational
LOAD
Logic
Input Output
D
CLK
≥tCD
CLK
D
≥tSETUP ≥tHOLD
tPD: maximum propagation delay, CLK →Q
tCD: minimum contamination delay, CLK →Q
tSETUP: setup time
How long D must be stable before the rising edge of CLK
≥tCD
CLK
D
≥tSETUP ≥tHOLD
CLK
tSETUP = 20ns tPD-HL = 40ns
CLK
tCLK
tPD,reg1
CLK
tPD,logic
tCD,reg1
In
D Q Combinational D Q
Logic
clk2
δ>0
Vin Vout
CL
V DD V DD
V out V out
vin C
CL
CL
Ron
tp = ln (2) τ = 0.69 RC
6.111 Fall 2017 Lecture 4 18
RC Equation
Vs = 5 V
Vs = 5 V
Switch is closed t<0
R
Switch opens t>0
Vs = VR + VC
+
Vc Vs = iR R+ Vc iR = C dVc
- dt
dV
Vs = RC c + Vc
dt
t
⎛ − ⎞
t
Vc = Vs ⎜⎜1 − e ⎟⎟
RC
⎛ − ⎞ ⎝ ⎠
Vc = 5⎜⎜1 − e ⎟⎟
RC
⎝ ⎠
New
tCD,R = 1ns State
tPD,R = 3ns
tS,R = 2ns Current
tH,R = 2ns Combinational
State
Logic
Clock tCD,L = ?
tPD,L = 5ns
Input Output
Questions:
• Constraints on tCD for the logic? > 1 ns
Combinational Sequential
§ Assign any signal or variable from only one always block. Be wary of
race conditions: always blocks with same trigger execute concurrently…
6.111 Fall 2017 Lecture 4 23
Blocking vs. Nonblocking Assignments
• Verilog supports two types of assignments within always blocks,
with subtly different behaviors.
• Blocking assignment (=): evaluation and assignment are immediate
always @(*) begin
x = a | b; // 1. evaluate a|b, assign result to x
y = a ^ b ^ c; // 2. evaluate a^b^c, assign result to y
z = b & ~c; // 3. evaluate b&(~c), assign result to z
end
What we want:
Register Based
Digital Delay Line
endmodule endmodule
6.111 Fall 2017 Lecture 4 26
Use Nonblocking for Sequential Logic
always @(posedge clk) begin always @(posedge clk) begin
q1 <= in; q1 = in;
q2 <= q1; // uses old q1 q2 = q1; // uses new q1
out <= q2; // uses old q2 out = q2; // uses new q2
end end
“At each rising clock edge, q1, q2, “At each rising clock edge, q1 = in.
and out simultaneously receive the After that, q2 = q1.
old values of in, q1, and q2.” After that, out = q2.
Therefore out = in.”
• Equivalent Verilog
reg z ç same as è
always @ * example of assign z = x && y
z = x && y combinatorial // z not a “reg”
always block
////////////////////////////////// /////////////////////////////////
// Sequential always block with a // Single always block
// combinational always block //
initial begin
clk = 0; a = 0; b = 1; always @(posedge clk) a <= b;
D always @(posedge clk) b <= a;
#10 clk = 1;
#10 $display("a=%d b=%d\n",a,b);
$finish; always @(posedge clk) begin
end E a <= b;
endmodule b = a; // urk! Be consistent!
end
Rule: always change state using <= (e.g., inside always @(posedge clk)…)
6.111 Fall 2017 Lecture 4 32
Implementation for on/off button
button
light
For most of our lab designs we’ll use a 27MHz system clock (37ns
clock period).
* Actually, our FPGAs will reset all registers to 0 when the device is
programmed. But it’s nice to be able to press a reset button to return to a
known state rather than starting from scratch by reprogramming the
device.
D
Clock
Transition is missed Transition is caught Output is metastable
on first clock cycle, on first clock cycle. for an indeterminate
but caught on next amount of time.
clock cycle.
Q: Which cases are problematic?
6.111 Fall 2017 Lecture 4 37
Asynchronous Inputs in Sequential Systems
D Q Clock
Q1
D Q
Clock Clock
Complicated
D Q D Q D Q Sequential Logic
System
Clock
endmodule
endmodule
clr
enb clk