NHE2483 Digital Systems Integration

VHDL Coding
VHDL Structure – a VHDL programme has the three following
sections
Libraries
• Libraries
• Entity Entity
• Architecture
A A
P S SOUT OUT
B
B
G
X
COUT
COUT

CIN Cin
Architecture
1
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Basic VHDL Code Structure (1)

library IEEE;

ENTITY name1 IS
GENERIC (name; type, size/value);
PORT (define port name, type and size);

END name1;
 
ARCHITECTURE level of abstraction OF name1 IS

SIGNAL -- (define internal signal names, type and size, also a default start-up
value can
be specified)
BEGIN
-- Any functions/operations outside of the process will update as soon as signals
inside the Process change state/value
-- multiple Processes can be specified within one Entity.

2
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Basic VHDL Code Structure (2)

PROCESS (input list)
-- Sensitivity list – process will operate when there is activity (signal --
transition) on one of the specified signals
-- Used for combinational logic - will therefore be Synthesised to
-- combinational logic elements.

BEGIN
WAIT UNTIL (clk'EVENT AND clk = '1’); -- for sequential logic
-- Note if a sensitivity list isn’t specified then a WAIT UNTIL is required.
-- Use or sequential logic – as the Process will not operate Until the WAIT
-- requirements have been met – in this case positive edge triggered on -- ‘clk’
input.

-- Main body of code defining the operation of the circuitry

-- Operations – IF, While, FOR, CASE statements etc
– each will require an appropriate End statement)
END PROCESS;

END level of abstraction ; 3

Dr. P.J. Mather
NHE2483 Digital Systems Integration

Basic VHDL Code Structures Continued

Note:
The following VDHL code elements do not form a
single VHDL programme, (only to demonstrate
examples of possible code).
Please use in conjunction with the 3.VHDL lecture
notes
Libraries Section
Defines the libraries (IEEE
library IEEE; libraries) and Packages (in USE
WORK.convert_pack’). If a
use IEEE.std_logic_1164.all;
Package is specified the functions
use IEEE.STD_LOGIC_UNSIGNED.all; within the ‘package’ that are used
in the Architecture section
USE WORK.convert_pack.ALL;
NOTE - would be specified in an
ICT/exam question.
4
Dr. P.J. Mather
NHE2483 Digital Systems Integration

ENTITY Section

ENTITY Code1 IS
ENTITY name Code1
PORT Defined the (Ports) input and
outputs signals
(clk: IN BIT;
Inputs clk, res single bit
x : IN BIT_VECTOR(4 DOWNTO 0); x input : 5 bit vector
y input : 3 bit vector
y : IN BIT_VECTOR(2 DOWNTO 0);
z output: 8 bit vector
z : OUT BIT_VECTOR(7 DOWNTO 0));
END Code1;
clk clk
5 bit vector 8 bit vector

x x4-0 z7-0
3 bit vector z
y y2-0
5
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Generic Code
Generic code that can be modified to accommodate different sizes of input and
output vectors as well as Signal vectors

Set up the Generic parameters in the Entity section before the PORT definition.

ENTITY Code2 IS
GENERIC (n1: natural := 4 -- different values can be specified
n2: natural := 7);
PORT (clk : IN STD_LOGIC;
x : IN BIT_VECTOR(n1-1 DOWNTO 0);
y : OUT BIT_VECTOR(n2-1 DOWNTO 0); );
END Code2 ;
GENERIC – this enables parameters
(n1 and n2) to be set to a value. Can clk clk 7 bit vector
then be used to define the size of the
ENTITY input and outputs as well as y6-0
4 bit vector
the internal registers (signals). x x3-0 y
x input : 4 bit vector (n1 = 4)
y output : 7 bit vector (n2 = 7)
6
Dr. P.J. Mather
NHE2483 Digital Systems Integration

ARCHITECTURE Section (Signals 1)

ARCHITECTURE behavioural OF Code3 IS

Architecture Section (details the operation of the system)

‘behavioural’ is a name used to specify the code level of abstract.
Functional, Structural etc could also be used.
SIGNALS – Generally specified, after Architecture has been
specified - internal Signals (registers) – can be viewed in a waveform
simulation.
Variables don’t relate to hardware so can’t be viewed in the
Waveform Simulations

SIGNAL Reg1 : INTEGER := 0;

Reg1- Signal register is an Integer with the initial default value of 0

7
Dr. P.J. Mather
NHE2483 Digital Systems Integration

ARCHITECTURE Section (Signals 2)

SIGNAL control :STD_LOGIC_VECTOR(6 downto 0) := “1000000”;

Control- Signal register is a 7 bit vector with the initial default

value of ‘1000000’ where bit 6 is set to ‘1’, all the remaining bits are
set to ‘0’

SIGNAL Dx : STD_LOGIC_VECTOR (1 to 3) := (others => ‘0');

Dx- Signal register is a 3 bit vector with the initial default value of
‘000’ . As all the bits are to be the same (other => ‘0’) can be used

A default value isn’t necessarily set at this stage – a reset input can
be used to reset the internal signals to a known state.

8
Dr. P.J. Mather
NHE2483 Digital Systems Integration

ARCHITECTURE Section (Code outside of a Process)

Functions/operations outside of a Process will update as soon as

signals inside the Process, change state/value.

<= Left hand side is assigned the result

of the right hand side operation/function
BEGIN
x_int <= vec2int(x);

The vec2int function should be contained in the

Work.convert_pack - Converts from Vector to Integer
z <= int2vec(IntZ, 8);
The int2vec function should be contained in the
Work.convert_pack - Converts from Integer to Vector
9
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Code Outside of a Process

errorcode(2 downto 0) <= SIPO(6 downto 4);

Writing the 3 bits of the SIPO register into the ‘errorcode’ register.
Note : if the bit locations are not specified for ‘errorcode’ then the
full register is taken and will need to be 3 bits, else an error
message will be displayed when compiling the code.
errorcode <= SIPO(6 downto 4);

Process section
Multiple Processes can be specified within one Entity.

Note; all Processes start with BEGIN and require a ‘END Process’
10
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Process Section (cont)

PROCESS (a, b) -- sensitivity list

BEGIN
For each Process – the process will operate when there is activity
on the specified inputs or signals.
This means that the process is not clocked – Combinational logic

PROCESS
BEGIN
WAIT UNTIL (res = '1' OR (clk'EVENT AND clk = ‘0'));
Process – followed by a WAIT UNTIL statement.
This shows that the process will only operate on a negative ‘clk’
transition (EVENT means there is a transition and clk=‘0’ means
the final value is zero. Thus –ve edge transition on ‘clk’ or ‘res’=1.
This is effectively a synchronous (clocked) process. 11
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Code for Developing Circuit Structures :IF-ELSE Statements

IF res = '1' THEN Process(I)       

begin               
reg <= 0;
GS <= '1’; -- set default outputs A
ELSE <= "000";               
reg <= ******** ; IF I(7) = '1' then                       
A <= "111";  -- override default A 
END IF; ELSIF I(6) = '1' THEN                       
A <= "110";               
If res = 1 then the ELSIF I(5) = '1' THEN                        
A <= "101";                         
‘reg’ (register) is set
ELSE                       
to zero (cleared).
GS <= '0’; --override default GS
ELSE reg is set by
END IF;       
another function (just end Process;
given here as ******)               

12
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Code for Developing Circuit Structures - CASE Statement

CASE (errorcode) IS
WHEN "001" => dout <= (sipo(3 downto 0)) XOR ("1101");
WHEN "011" => dout <= (sipo(3 downto 0)) XOR ("1010");
WHEN "111" => dout <= (sipo(3 downto 0)) XOR ("0100 ");
WHEN "110" => dout <= (sipo(3 downto 0)) XOR ("1000");
WHEN OTHERS => dout <= sipo(3 downto 0);
END CASE;

WHEN the 3 bit errorcode equals one of the 4 codes

(001,011,111,110) the ‘dout’ is assigned the result of sipo(3 downto
0) XOR’d with the respective 4 bit values (1101 to 1000).
WHEN OTHERS section is always required as there needs to be an
assigned operation for all possible codes (even if all have been
accounted for in the CASE statement
13
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Code for Developing Circuit Structures (cont 1)

Accum <= y * (x + Accum);

Accum + x

X y

Accum is assigned the result of (Accum + x)*y

14
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Code for Developing Circuit Structures (cont 2)

Z <= x XOR Dx(2) XOR Dx(3);

z
Dx2
XOR
function Dx3

Z is assigned the result of x XOR Dx2 XOR Dx3

15
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Code for Developing Circuit Structures (cont 3)

LHS Control size of register not specified so full register is assumed

(6 downto 0)
control <= (control(0)) & (control(6 downto 1));
control
6 5 4 3 2 1 0

& = concatenation function enables different register bits to be

assigned to a register.
Number of bits on the right hand side (RHS) of <= needs to equal
the number of bits on the LHS.
Operation: control bit 6 is assigned control bit 0,
control (6 downto 1) is assigned to control (5 downto 0)
16
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Aspects of ‘good’ VHDL code design, comparing it to high-level

programming language design.
• Use existing general purpose code stored in library wherever
possible.
• Restrict the use of variables (limited visibility).
• Use SIGNALS which can be monitored during simulation and can
be synthesised to layout.
• VHDL code should be readable, easy to follow & the flow of data
should be apparent.
• Use simple Processes and Generic terms
• Software programs generally use large functions/procedures as
partitioning, however these do not lend themselves to be
synthesises to layout if used in VHDL code (not hardware
equivalent).
• A direct mapping from concurrent signal assignments to
hardware, easier to judge the size of a circuit if register sizes are
explicitly
Dr. P.J. Mather stated. 17