MPA-PLD Exam Topics 2021/22

1. Basic combinatorial functions (NOT, AND, NAND, OR, NOR, XOR, XNOR): truth table,
Boolean equation
Pagina 28 ( n am mai scris ca nu ii asa musai )
2. D-type registers: level sensitive (LATCH) and edge sensitive (Flip-Flop) – principle of
operation (waveforms), usage in FPGAs
LATCH =statically driven (level sensitive) register
When CLK is active (H level), value from D input is transferred to Q output.
When CLK is inactive (L level), output stays in the last known value (memory function).

FLIP FLOP = Dynamically (edge) driven register (edge sensitive FlipFlop)

When there is an active (rising) edge on CLK input, value from D input is transferred to Q
output.
Otherwise output stays in the last known value (memory function).

In FPGAs we ONLY use FLIP-FLOPS.

3. Binary <=> Hexadecimal <=> Decimal <=> BCD (number representation and conversion)
4. ASIC and ASSP: explain the meaning
ASIC = Application Specific Integrated Circuit
- both complex and simple, both analog and digital signals
- very long and expensive development
- very good power consumption
- very hard to modify
- not generally available
USED in : chipsets, control chips of SSD, chips for car industry, …

ASSP = Application Specific Standard Part

- both simple and complex function, same design procedure and production as for ASIC
- often very flexible
- often redundant (user do not need all the functionality)
- commercially available
USED in : standard interface chipsets ( USB, Ethernet ), ADC, DAC , memories

5. PROM (LUT) structure for combinatorial logic implementation – principle, usage

PROM or programmable ROM (programmable read-only memory) is a computer memory chip
that can be programmed once after it is created. Once the PROM is programmed, the
information written is permanent and cannot be erased or deleted

6. Basic FPGA structure: configurable logic cell (LUT + FF) and programmable interconnect
A FPGA = basic chip that could be shared among several different project
It is cheap, it has fast and cheap development and verification.
Structure : FPGA is made out of a lot of Look Up Tables and Flip Flops and are being connected
with interconnect.
FPGA is configurated using electronic switches which can be reprogrammed.
7. Implementation of a design into FPGA
a. Design capture using HDL and schematic
Digital Design Synthesis : Conversion of design description (textual, schematic...) to a circuit
composed of generic digital components (gates) including optimization (logic
minimization...)
Output of the synthesis tool is an RTL schematic (Register Transfer Logic)
b. Logic synthesis => RTL schematic (composed of generic logic cells)
Output of a synthesis tool: RTL schematic .

c. Mapping => Technology schematic (composed of LUTs and FPGA FFs)

MAP result : each LUT has already its own function.
MAP result: technology schematic

d. Place and Route

Partially random process with random initial conditions.
Can give different results for each run (difference in maximum design frequency, up to several
tens of %).
e. Static timing analysis
f. Generate configuration file

8. Basic structure of a VHDL code

a. Declaration of libraries and packages
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
b. Entity declaration
ENTITY ALU IS
PORT (A,B: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SUM: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END ALU;

Entity declaration describes its interface to the outside world. The PORT section defines inputs
and outputs of the block.

c. Architecture
ARCHITECTURE Behavioral OF ALU IS
BEGIN
SUM <= STD_LOGIC_VECTOR(UNSIGNED(A) + UNSIGNED(B));
END Behavioral;

Defines relations between entity inputs and outputs (contains the description of entity
functionality). It is always related to a particular Entity. Functionality of one Entity can be
described using several Architectures.
Several different types of description:

❑ Behavioral Algorithmic, high-level language constructs

❑ RTL Register Transfer Logic; using processes

❑ Structural Text equivalent of schema (netlist)

The best praxis is to combine all the description methods to get most EFFECTIVE and most
READABLE description of the required functionality
9. VHDL objects: PORT (IN, OUT), SIGNAL, VARIABLE, CONSTANT
Available modes of the PORT signals:
IN : it is not allowed to assign any value to this signal (port) within the entity (read only)
OUT : it is not allowed to read value of this signal (port) within the entity (write only, cannot be
used in conditions of conditional statements, cannot be used on the right side of
assignments)
SIGNAL : ( <= )
-basic VHDL object
- After synthesis the signal is represented by a physical wire (can be physically
located)
- Signals are declared within the entity as PORTs or inside the architecture as
internal SIGNALs, which are not visible from outside of the entity.

VARIABLE ( := )
-basic VHDL object
- Auxiliary variable for algorithmic description (iteration variable of loops...)
- has no physical equivalent
- Variables may be declared in declarative part of the architecture (shared
variables; rarely used) or in a declarative part of a process (non-shared variables)

CONSTANT ( := )
-basic VHDL object
- used to store fixed values
- can be assigned to both signals and variables
- Constants may be declared in declarative part of an architecture or a process
(similar to shared and non-shared variable)

declaration = declare a type of signal/variable/constant

definition = assign a value to variable/constant

10. STD_LOGIC and STD_LOGIC_VECTOR: values ('0', '1', 'Z',...)

'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-'); -- Don’t care

11. SIGNED and UNSIGNED data types (as described in IEEE.NUMERIC_STD package)
Data type for arithmetic functions.
The definition is identical to STD_LOGIC_VECTOR, but as it is a formally different type, it is
necessary to use conversion functions when dealing with these types.

12. VHDL: sequential and concurrent statements, PROCESS, sensitivity list of a PROCESS
Concurrent statements :

❑ Each concurrent statement represents part of a digital circuitry.

❑ The sequence of concurrent statements in the source code is not important.

❑ Used mostly for simple logic description.

❑ Each PROCESSS as a whole and each component instantiation is a concurrent statement on

its own.
PROCESS = one concurrent statement
Component instantiation = one concurrent statement
In concurrent statements, un semnal trebuie definit intr-o singura linie de cod .

Sequential statements :

❑ Used in processes, functions and procedures

❑ The order of the statements is important

❑ Can be used to describe both combinatorial and sequential logic

Commands within a process are interpreted sequentially (similar to microprocessor program),
the sequence of commands is important.
Each process as a whole represents one concurrent statement (a complex one).
There are two types of process:

❑ With a sensitivity list

❑ With a wait statement (use these only for simulation!)

In ce facem noi, noi folosim sensitivity list si logica Combinatorial.

Combinatorial : the sensitivity list contains all the signal from the right side of assignments and
from conditional statement arguments

From simulator point of view: a process is executed whenever any signal in the sensitivity
changes its value

13. Signal (delayed, scheduled) assignment "<=" and variable (immediate) assignment ":=":
the difference in usage and behavior within PROCESS. Principle of default assignment.
Delayed : In process for each signal only the last assignment found is considered (used), any
previous assignments are ignored. The assignment is actually made when the PROCESS is
finished (or stopped using a WAIT statement in simulation).

Default :
It is allowed to assign a value to a signal only in a single concurrent statement. As PROCESS is
one concurrent statement on its own, one signal can be assigned only in a single PROCESS!!!

<= is equal to delayed assignment. When we use this we are using SIGNALS and order of
assignments does NOT matter.
:= When we use this we are using VARIABLES and order of assignment matters.
Value of assigned signals are updated at the end of the process.

14. VHDL structural description: purpose, principle

- Often much easier to modify, possible automation
- Clear VHDL = design tool independent (portability)
- Usually less readable

BONUS - Simulation versus synthesis :

- Synthesizer is not interpreting the code exactly (as simulator does), it is trying to
recognize known structures
- For reliable design it is necessary to use standard design coding styles (especially
for synchronous sequence systems)

15. Combinatorial / sequential systems: difference, examples

Combinatiorial:
-Output signal values depend entirely on current values of input signals.
-For each combination of input values of logical ZEROs and ONEs there is an explicit (definit)
value of output value.

Sequential:
❑ Output signal values depend not only on current values of input signals but also on previous
values (history).

❑ Always contain memory elements (registers)

❑ Systems that combine registers and combinatorial logic are usually called sequential systems.

16. Synchronous / asynchronous systems: difference, which one to use in FPGA (and why)

Asynchronous:
-In case they contain a clock signal, it is not common for all its sequential components
(registers)
-They are able to respond immediately to an input stimulus
-They are usually less complex (in terms of utilized gates and registers) than equivalent
synchronous systems
-Very difficult to design and even more to verify
-Gradual signal propagation, risk of hazards

Synchronous:
-Can change its state only in certain moments defined by a single control (clock) signal
-Much easier design and verification
-Much more reliable, less dependent on external conditions

- Perfectly suitable for CAD tools (design automation)

- Today almost all digital systems are synchronous

- In FPGAs all the registers are edge sensitive D-type Flip-Flops
17. Counters: types, principle of implementation, advantages / disadvantages

Counters = Very simple Finite State Machines (FSMs)

❑ Binary
Incremented with each rising edge of a clock signal (CLK)
4b counter: 2^N = 16 states (0 to (2N – 1) = 15)

N bits ➔ N registers (flip-flops)

Cand ajunge la 111… se reseteaza la 0 (overflow)

❑ Decimal
Decima = binary counter with shortened cycle
Cycle shortening condition:
From state 9 jump to state 0
Unused states 10-15

❑ Gray
Only single bit changes when transitioning between adjacent states.
Numara: 0,1,3,2,6,7,5,4 etc adica numara astfel incat sa fie doar un bit schimbat intre valoarea
binara a state-urilor

Usage:
• FIFO addressing
• A/D converters
• Absolute position sensors

Ordinea numerelor nu este naturala dar se poate folosi un encoder care sa “traduca” ordinea
lor in ordine normala.

❑ Johnson
Very simple implementation

-High maximum clock frequency

- Disadvantage : The cycle length is only 2·N (compared to 2^N in case of binary or Gray
counter) ➔ large number of unused states

- Sometimes used as a decimal counter (with a decoder on its output) in DACs

❑LFSR
Liner Feedback Shift Register (feedback with at least 2 wires)

-Very simple implementation

-High maximum clock frequency

- The cycle length is (2^N)-1

-Generator of PRBS (Pseudo-Random Binary Sequence, also called M-sequence)

- If all bits are “1” => illegal state
- implementation : Fibonacci or Galois
XOR:

XNOR:

In acest tabel :

Astea sunt configuratiile RECOMANDATE. Putem lua feedback si de la alte TAPS, insa o
sa avem cicluri mai scurte ( deci nu (2^n)-1 ) si nu o sa fie asa de random .
Cand declaram semnalul, MSB e lugnimea registrului si LSB este bitul nr 1.

18. Inadvertent LATCH inference in VHDL

La flip flop trebuie tot timpul sa avem conditie the rising sau falling edge.
La latch nu avem conditia anterioara, avem conditie ca si clock sa fie activ .
Main problem of latch : formation of combinatorial loop .
La LATCH, cand avem combinatorial loop o sa primi warning in VIVADO, dar nu eroare,
programul va rula insa nu cum ar trebui.

Inadvertent ( din greseala ) latch se creeaza din greseala, atunci cand scriem cod gresit. Ca sa
corectam greseala, o sa encapsulam codul intr-un process sincron, senzitiv la rising edge, in
maniera asta convertim latch ul intr un flip flop.
Daca scriem conditii care nu sunt complete atunci putem crea un Inadvertent Latch.

INCOMPLET^
Ca sa corectam codul trebuie sa acoperim toate posibilitatile al conditional statement si/sau
adaugam un default assignment ( semnalul va avea valoare initiala si de ex. isi va schimba
valoarea doar in cazul in care vrem noi )
19. Generic structure of FSM: combinatorial / registred / state outputs, Moore / Mealy
FSM = Finite State Machine
= Simple system (program, automaton) which can be in exactly one of its statesat any
given time (finite number of states)
- The FSM performs transition – changes its state according to next state logicand input signals
- Based on the current state (and inputs) it generates output signals
- Finite State Machine can be considered to be generalized counter
- The other way around: counters are special case of finite state machines with dominant
counting regime (regular transition between neighboring states)
- State machines can be both synchronous and asynchronous
FPGA-Based FSM real use : video controller, Ethernet MAC, Encoder/Decoder …
- Program implementation of FSM running on a processor is called a software realization of a
FSM.
- The reaction of a software based FSM is usually slower compared to hardware based FSM
(implemented in FPGA or ASIC)

The state register stores information about current FSM state. Its minimum required size
(number of bits) is given N = log2 (M), where M is number of working (valid, intended) states of
the FSM.

MOORE FSM : FSM outputs depend solely on current state

MEALY FSM : FSM outputs depend both on current state and control inputs.

How to choose the FSM type ?

- When immediate (asynchronous) reaction of FSM outputs to an input is required, then
Mealy FSM must be used.
- Using state outputs enables Moore FSM implementation without output latency.
However, sometimes it is not efficient (too complex FSM).

Output of each block (entity) in a design should be registered ➔ try to use only
registered output FSM variants.
20. FSM state encoding (binary, Gray, one-hot...) benefits / drawbacks
After the synthesis the state signal is always represented by n-bit vector:

Minimum number of n bits, example :

FSM with 10 states (M=10) requires at least N=4 bit register (vector) for state register.

There are several different variants of state signal encoding. The difference is in

❑ Size (number of bits) required for state register

❑ Complexity of next-state logic and output logic blocks

❑ Maximum operating frequency (different combinatorial path delay)

❑ Different FPGA resource consumption and power consumption

❑ Number of hazards on output signals at transitions between states

❑ Auto – the synthesis will select "the best" encoding

❑ One-Hot – only one of N bits in a vector is in log. 1; suitable for medium FSMs in FPGAs, high
speed, low HW requirements

❑ Compact – optimum number of state registers used

❑ Sequential – simple calculation of the next state (without branching)

❑ Gray – suitable for large FSMs and for those with little branching

❑ Johnson – similar to Gray

❑ User – as specified in the HDL code

❑ Speed1 – properties not specified, usually large number of bits than number of
states, should result in high maximum operating frequency

❑ None – the synthesizer will not extract FSMs

21. FSM illegal states

Types : unused, unreachable, non-working
How can the FSM reach illegal state?

❑ Power supply problems: incorrect power ramp-up (non-monotonic) at startup, insufficient

power during normal operation (credit card cracking)

❑ Low quality of input signals: slow change ➔ metastability

❑ Timing violations: setup time (higher than allowed clock frequency), interface timing
violations

❑ Overheating

❑ Ionizing radiation

❑ Coding errors
How to solve Illegal States ?
“SAFE” property in synthesis tool, use an external timer ( Watchdog ) , let the user to reset the
logic

22. Timing of digital circuits: clock period, setup / hold time, clock to output, reset recovery
time... Static timing analysis of synchronous sequential systems, setup slack calculation
(timing margin)
Setup time si hold time : data trebuie sa fie stabila inainte(setup) si dupa(hold) momentul
citirii ( pe rising edge of flip flop ).

Atunci cand avem rising edge avem o mica intarziere pana se transmite de la data la output (
de la D la Q ) . Asta este Tcko. Intotdeauna > 0 .

Reset Recovery Time - noi trebuie sa avem un anumit timp intre rising edge al clockului si
semnalul de asynchronous reset
Static Timing Analysis – a process which calculates whether your design is able to meet your
timing specifications
-clock frequency is the most important
Timing margin = setup slack
Formula : Setup slack = Data required time – Data arrival time
If its positive is ok, if it’s negative it means that the logic of our system is too slow, design is
not optimal, to fix this we must reduce clock frequency or simplify our logic.
The maximum allowed frequency is determined by a path with the longest propagation delay
(worst case path). = the slowest combinatorial logic gives us the maximum frequency allowed
Hold slack = Data arrival time – Data required time

23. Principle of pipelining and register retiming (balancing)

Pipelining = trying to split the design in order to increase CPU frequency
= instead of performing one instruction in one clock cycle, the instruction is divided
to several discrete clock cycles and the instruction is executed in parts

- Improves speed of CPU (frequency increase).

 Split up complex task into several less complex, that are processed faster

Register retiming = Transfer part of a complicated logic function behind a register

Before

After

24. Metastability: cause, effects, treatment

Metastability = Temporal incorrect state of a digital output
-Usually disappears quickly (noise)
-It is a harmful event that should be eliminated!
Cause :
- caused by not respecting timing requirements (setup/hold time) of Flip-Flops
- caused by low-quality input signals (input level close to a 0/1 threshold)
SETUP / HOLD time violation

❑ Excessive clock frequency (overclocking)

❑ Asynchronous signal input (UART, buttons...)

❑ Asynchronous clock domain crossing

Improper usage of asynchronous set/reset

Effects :
-Random errors that are difficult to replicate
-Strongly depend on actual conditions: clock frequency, supply voltage, data value (0/1),
temperature, humidity, customer demonstration...
-Can affect only some components/devices (manufacturing process dependency)

Treatment :
We can only limit effects (probability) of metastability
The metastability is unavoidable.

❑ By increasing metastability settlement time we can reduce probability of further

metastability propagation.

Recommended method for asynchronous inputs : More registers in the chain ➔ lower
probability of metastability propagation ➔ longer Mean Time Between Failure (MTBF)
At least 2 registers are required, 3 or more registers are user in higher reliability
applications (beware of latency!).

25. What is a clock domain, clock domain crossing problems

Clock domain = A group of Flip-Flops (registers) sensitive to the same clock edge (usually rising
one) of the same clock signal.
( un grup de componente care au acelasi clock )
A minimal difference of clock signal propagation delay to individual Flip-Flops is expected
(minimal skew);
GOAL : minimize difference of clock signal propagation delay to individual Flip Flops

Clock domain crossing problems :

-The oscillators may have same nominal frequency but the actual frequency is always slightly
different.
-The difference is not stable over time – clock jitter / wander.
-When reading data on the receiver side some data words may be duplicated or skipped.

Solutions :
- Simple synchronizer – suitable for control signals or slow data
-Asynchronous FIFO buffer – with independent clocks at write and read side; suitable for high
speed data transfer
Both solutions can deal with data transfer in one direction only; for bidirectional transfer it is
necessary to double each structure.

26. Synchronous and asynchronous reset: principle and properties

What is the set / reset?

❑ By activation of a dedicated control signal it is possible to put agroup of registers into a

defined state simultaneously.
What is it good for ?
- Debugging ( put the system back into a known state )
- Hardware or software error – put the system back into an operational state
- After Power Up of a digital IC, reset brings it to default state of all registers
Synchronous reset :
The reset event occurs at the nearest active edge (usually the rising one) of the clock signal
Properties :
- Requires functional clock signal
 - It must be long enough so that at laest one active clock edge captures it

Asynchronous reset :
The reset event occurs immediately at the reset input activation
Properties :
- it is dangerous when released ( timing relation to the clock signal is not known )

Recommended reset method : asynchronous initialization, synchronous release (so called

asynchronous reset signal synchronization)

27. Clock management blocks: purpose, general capabilities

DCM- Digital Clock Manager - Clock signal conditioning (phase shifting, synthesis)
MMCM- Mixed Mode Clock Manager – can be used as a frequency synthesizer
CMT, PLL, DLL …
Purpose : blocks that can modify the base clock signal
General capabilities :
-deskewed clock ( with different duty cycle)
-clock doubler ( double frequency compared to the original one )
-clock divider ( divides the original frequency)
-frequency synthesizer ( phase shift compared to the original one )

28. Clock enabling: principle, purpose

Clock enabling - any lower frequency can be used (with a resolution of primary clock period).
All the Flip-Flops in the design (even those that should run on a slow clock) share a common
clock signal (usually of a relatively high frequency). Switching of the Flip-Flops can be
enabled/disabled (slow down) using a dedicated Clock Enable signal.
Benefits : less clock domains, less synchronizers
Purpose : to slow down the frequency of the flip flop

29. Basic FPGA logic cell (LUT + FF), size of LUT and its functions (logic, RAM/ROM, shift
register)
Logic cell - composed of combinatorial and sequential block
Combinatorial portion of the logic cell : MUX based / LUT based
MUX structure – better suited for data control and switching logic implementation
LUT structure – MUCH better for arithmetic function implementation and automatic synthesis
tools

Size of LUT : Number of memory cells = 2^inputs

More inputs results in larger address decoder resulting in slower propagation.
Large LUTs are inefficient for implementing simple logic functions .

LUT functions :
- Combinatorial function
- RAM
- Shift register
Each 4-input LUT is composed of 16 SRAM cells = 16 registers (flip-flops)

LUT AS RAM/ROM
- Small and fast memories
How to use distributed RAM?
- Inference
- Instantiation
- IP Core / Wizard
 - Special macros

LUT AS A SHIFT REGISTER

- Very efficient structure for delaying of data signals
- There must be no RESET, SET or LOAD function described in the code in order to be
correctly extracted (inferred). CLOCK ENABLE function is allowed. It is possible to use
address input ➔ shift register with dynamically adjustable length.

FLIP FLOPS
- Always a D-type register
- Can be set to Latch or Flip Flop
- Asynchronous not recommended for FPGA

BONUS : 1 Slice = n*LUT + m*FF

The CLOCK SIGNAL is common for the whole slice.

30. DSP in FPGA: DSP blocks in FPGA (features / capabilities)

Typical DSP blocks ( DSP = Digital Signal Processing )

❑ Modulators, demodulators

❑ Filters (FIR, CIC), correlators

❑ Complex multipliers, adders, dividers

❑ Transforms (FFT, IFFT, Cosine...)

❑ Digital Pre-Distortion (DPD)

❑ Direct Digital Synthesis (DDS)

Basic DSP operations

- Addition, Multiplication, Memories
- More complex operations, which are made from combining the ones above
31. Principle of resource sharing (required number of multipliers for FIR filter)
Resource sharing = Try to share resource-hungry components(like multipliers) to reduce HW
requirement
Required number of multipliers for FIR filter = Number of multiplications / Number of clock
cycles

32. FPGA IO cells features

I/O cells
• Interfacing of the FPGA core logic to the outside world
• The core uses low voltage levels (to improve performance and power consumption)
• The core logic is very sensitive (ESD...)
• I/O cells are ruggedized, equipped with many advanced features to enable fast and safe
interfacing

Requirements on an IO cell

❑ Support of multiple logic standards (different voltage levels)

❑ Support of differential pairs

❑ Parallel bus synchronization support

❑ Fast data transmission (over 1 Gbps)

❑ Integrated termination resistors

❑ ESD protection, pull-up / pull-down resistors

IO CELL BASIC STRUCTURE : input and output buffers, tri state output capability, programmable
input inverter and implementation of differential logic standards.

IO CELLS extra features : DDR interface, support for precise timing adjustment, serial
communication support,
BONUS :
❑ IO pins of an FPGA are grouped into so called BANKs

❑ Each BANK has its own power supply input

33. Differential pairs

Benefits:

❑ Much better noise immunity

❑ Enables use of smaller voltage swing

❑ Smaller EM emission

❑ Lower power consumption

Used in : LCD panels, ADC, DAC, SATA, USB, Ethernet, PCI-Express…

34. IP cores: soft and hard (principle, examples)

❑ IP = Intellectual Property; does not mean exactly what the "IP core" really is when
speaking about FPGAs, but the term is widely used.

Why to use IP cores ?

• Not to "reinvent the wheel", for standard systems there are often ready-to-use solutions
(free or payed)
• Immediately available; time = BIG money (time to market)
• Usually fully tested (guaranteed functionality), especially the payed ones
• Usually better optimized (performance, power, area), often even with respect to target FPGA
type
• Some Hard IP feature analog circuitry (cannot be implemented in FPGA logic cells)

• Hard IP – there is a dedicated area on the FPGA chip that is used for the IP functionality.
This dedicated chip area cannot be used for anything else.
• Soft IP – the required functionality is created using a general purpose FPGA logic (LUTs, Flip-
Flops, DSP blocks, BRAMs...). Some IP cores are in a form of an HDL code, however the more
complex ones are often payed and as such distributed as encrypted.

Hard IPs : better area efficiency, lower power consumption, higher performance
not available on every FPGA, less flexible

Soft IPs : independent of target FPGA, more flexible

larger chip area, higher power consumption, lower performance

Common hard IPs : RAM memories, clock managers, microprocessors, mixed signal blocks…
Common IPs : DSP blocks, Microprocessors, Audio and Video codecs, …

35. FPGA configuration cells technologies: types and properties

In each FPGA there are configuration cells that define function of each individual component
of the array.

❑ LUT setting (logical function), LUT function (combinatorial / RAM / Shift)

❑ Configuration of traces of the programmable interconnect

❑ IO cell setting (input/output, drive strength, impedance...)

❑ Hard IP setting

❑ ...
Configuration cell technology

❑ Mask-defined (ROM)
The basic chip (the logic) is manufactured and supplemented with one or more metal layers
that define the functionality (cell function and interconnect).
- Minimum chip area
- High performance, low power, instant functionality at power-on
- Fixed functionality, cannot be used for prototyping
- Great radiation hardness, but can be easily reverse-engineered (RTG)
Usage : structured ASIC

❑ One-time programmable (OTP): Fuse, Antifuse (PROM)

The FPGA is manufactured with unprogrammed cells (FUSE – conducting, ANTIFUSE – non-
conducting). Programming changes state of the cells (using high voltage/current)

- Relatively small chip area requirements: small cell but a large programming transistor is
required.

- For the same technology node occupies smaller space than EEPROM or SRAM ➔ shorter
tracks, faster switching, higher performance.
- Low power, functional immediately after power-up.

- Only one-time programmable (OTP) ➔ not suitable for prototyping.

- Perfect radiation hardness, suitable for space applications.
- Reverse engineering is difficult as the device function is burried deep inside the silicon (below
metallization layers)

Usage : older SPLD devices ( FUSE ) , now Microsemi FPGA ( Antifuse )

❑ EPROM
The configuration cell is a MOSFET transistor with a floating gate. To program a cell, a high
voltage is required to put a charge to the floating gate. The cell is erased using UV radiation.
- Relatively small chip area requirements: small cell but a large programming transistor is
required.

- For the same technology node occupies smaller space than SRAM ➔ shorter tracks, faster
switching, higher performance.
- Low power, functional immediately after power-up.

- At least one (usually more) technology nodes behind SRAM devices ➔ chip area, low power
and speed benefits are "lost".

- Can be used for prototyping (UV erasure takes about 10-60 minutes).

- Reverse engineering is difficult as the device function is buried deep inside the silicon (below
metallization layers).

- Somewhat lower radiation hardness.

Usage : older CPLD and SPLD, now obsolete

❑ EEPROM / FLASH
The cell is similar to EPROM, but the erasure can be done electrically using another electrode.
The FLASH is composed of EEPROM cells, which are grouped so that all the cells in a group are
erased simultaneously ➔ faster erasure process.

- FLASH: Relatively small chip area requirements: small cell but a large programming transistor
is required. EEPROM: much larger area required

- For the same technology node occupies smaller space than SRAM ➔ shorter tracks, faster
switching, higher performance.

- Low power, functional immediately after power-up.

- At least one (usually more) technology nodes behind SRAM devices ➔ chip area, low power
and speed benefits are "lost".

- Can be used for prototyping, but there is a limited number of write/erase cycles.

Usage: SPLD, CPLD and FPGA ("non-volatile FPGA")

❑ SRAM
Every cell is composed of 6 transistors, which are in a random state after power-up ➔ a
configuration is required at each power-up.

-Relatively high chip area requirements (6 transistors per cell)

- For the same technology node occupies more space than other cells ➔ longer tracks, slower
switching, inferior performance.
- Higher power consumption, after power-up a configuration is required(ranging from few
milliseconds to tens of seconds).

- Always at the edge of chip manufacturing technology (20/22 (14) nm SRAM x 65 nm Flash) ➔
drawback of performance, large area and power consumption is wiped out.

- Ideally suited for prototyping.

- Somewhat lower radiation hardness but there are space-ready hardened variants available.

- Reverse-engineering is possible (configuration is stored in an external non-volatile memory),

additional protection is needed (ciphering).

Usage: most of modern FPGAs, some CPLDs

Configuration cells occupy significant portion of the FPGA chip area (up to hundreds of Mb of
storage is required) ➔ their technology significantly affects properties of the whole FPGA

Important properties

❑ Ease of re-programmability (prototyping)

❑ Power-on functionality (start-up delay)

❑ Chip area of the cell

❑ Power consumption

❑ Ionizing radiation immunity

❑ Reverse engineering immunity

❑ Price
36. Static and dynamic power consumption of FPGA (dependencies)
Static supply current – dependency

- Supply voltage – dominantly core supply (usually 1.0 or 0.9V); lower voltage is typical for
newer and/or low-power FPGAs.
- A small change of the supply voltage within specified limits may change power consumption
significantly (like running core at 0.95V instead of 1.00V, when possible).

- Chip size – number of slices, IO cells...

- Logic technology – not only technology node (22 nm, 14 nm...) but also selected logic type
(low power / high performance)

- Configuration cell technology – SRAM / Flash / Antifuse

- Actual configuration – some unused portions of the chip can be left unpowered

Dynamic power consumption

-Usually higher than static power consumption (2-50x)

- Clock frequency of the logic

- Relative toggle rate of data signals (data signal dependency)

- Load capacitance (wiring, traces); strongly depends on the technology node (thinner traces
➔ smaller capacitance), PAR affects the power consumption slightly as well

- Voltage levels (voltage swing)

- Technology node – not only node but also selection of logic cells (low speed / high
performance)

Debouncing :
- Cand apesi un buton, semnalul oscileaza intre 0 si 1 timp de cateva ms ( aprox 20 ). Un
debouncer ( cod sau filtru trece jos ) : dupa primul rising/falling edge nu mai citim data
primita timp de cateva ms. pana ce consideram ca data s-a stabilizat.