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Tutorial 8
Michal Kubíček
Department of Radio Electronics, FEEC BUT Brno
Vytvořeno za podpory projektu OP VVV Moderní a otevřené studium techniky CZ.02.2.69/0.0/0.0/16_015/0002430.
Tutorial 8
FPGAs in detail
❑ Logic cells
❑ FPGA architecture
❑ Memories in FPGA
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Logic cells
LUT / MUX technology
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Logic cells
FPGA CPLD
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Logic cells
Inputs
Function
generator
Inputs
Function Flip-
generator Flop
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Logic cells
Logic cell
composed of combinatorial and sequential block
CPLD
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Logic cells
Logic cell
composed of combinatorial and sequential block
FPGA
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Logic cells
Logic cell
composed of combinatorial and sequential block
❑ FPGA architecture is Medium Grained, each cell
performs relatively simple logic function
❑ It leads to better area/utilization efficiency,
higher maximum frequency, but puts higher
requirements on programmable interconnect
❑ Granularity: CPLD is considered to be Coarse
Grained, while ASIC to be Fine Grained.
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Combinatorial function generator
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Logic cells
MAP process
RTL Schematic Technology Schematic
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Logic cells
MAP result each LUT has its content (defined logic function)
O = ((I0 * I1 * !I2 * !I3) + (!I0 * !I1 * I2 * I3) + (I0 * I1 * I2 * I3) + (!I0 * !I1 *
!I2 * !I3));
Logic cells
Function Flip-
generator Flop
Two variants:
• based on multiplexers (MUX based)
• based on look-up table (LUT based)
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Logic cells
"Y = 1 when C = 1 or when
A and B = 1"
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Logic cells
The LUT architecture dominates since early 90s, virtually no other FPGAs
are now available today (which doesn't mean that MUX based FPGAs will not
appear again sometime in a future).
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Logic cells
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Logic cells
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Logic cells
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Logic cells
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Logic cells
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Logic cells
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Logic cells
Real implementation:
one pseudo 6-input LUT is
composed of four 4-input
LUTs
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Logic cells
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Alternative use of a LUT
LUT = only a logic function generator?
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LUT: other functions
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LUT: other functions
LUT as a RAM/ROM
16 x 1b Data
Distributed RAM/ROM
Small and fast memories
16 x 1b
Data
16 x 1b
Address 16 x 1b
Address 16 x 1b
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LUT: other functions
LUT as a RAM/ROM
Distributed RAM/ROM
Modes (Virtex-5)
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LUT: other functions
LUT as a RAM/ROM
Distributed RAM/ROM
Modes (Virtex-5)
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How to use the distributed
RAM in your design?
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LUT: other functions
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LUT: other functions
Design – inference
Distributed RAM/ROM – using a VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---------------------------------------------------------
ENTITY RAM_64x8 IS
PORT (
clk : IN STD_LOGIC;
WR : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
D_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
D_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
D_out_reg : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END RAM_64x8;
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LUT: other functions
Design – inference
Distributed RAM/ROM – using a VHDL code
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LUT: other functions
Design – inference
Distributed RAM/ROM – using a VHDL code
-- data write
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LUT: other functions
Design – inference
Distributed RAM/ROM – using a VHDL code
-- asynchronous read
-- synchronous read
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LUT: other functions
Design – inference
Distributed RAM/ROM or Block RAM/ROM – using a VHDL code
-- distributed RAM
-- block RAM
attribute RAM_STYLE of ram_1: signal is "BLOCK";
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LUT: other functions
Design – instantiation
Distributed RAM/ROM – VHDL instantiation (Language templates)
RAM16X1D_1_inst : RAM16X1D
generic map (
INIT => X"0000")
port map (
DPO => DPO, -- Read-only 1-bit data output for DPRA
SPO => SPO, -- R/W 1-bit data output for A0-A3
A0 => A0, -- R/W address[0] input bit
A1 => A1, -- R/W address[1] input bit
A2 => A2, -- R/W address[2] input bit
A3 => A3, -- R/W ddress[3] input bit
D => D, -- Write 1-bit data input
DPRA0 => DPRA0, -- Read-only address[0] input bit
DPRA1 => DPRA1, -- Read-only address[1] input bit
DPRA2 => DPRA2, -- Read-only address[2] input bit
DPRA3 => DPRA3, -- Read-only address[3] input bit
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);
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LUT: other functions
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LUT: other functions
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LUT: other functions
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LUT = shift register
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LUT: other functions
MUX Q
D_in ...
D_out
clk
adr
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LUT: other functions
Artix-7 LUT:
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LUT: other functions
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LUT: other functions
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Sequential portion of a logic cell
Register (Flip Flop)
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Logic cell
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FPGA architecture
Grouping of basic cells
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FPGA architecture
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FPGA architecture
SLICE
The CLOCK SIGNAL is common for the
SLICE = 2 x LUT + 2 x Flip-Flop whole slice.
(Spartan-3)
The registers feature a CE (clock enable)
input, which is usually also common for the
whole slice.
The registers have a set/reset input. Only a
single variant of the set/reset function is
supported by the registers (either set or reset,
either synchronous or asynchronous). Any
additional set/reset function (if needed) must
be emulated using a general purpose logic
(LUTs).
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FPGA architecture
SLICE
A very important part of the logic cells is so called CARRY LOGIC, which is a dedicated high-
speed interconnect of neighboring slices. It is often used to implement arithmetic functions,
thus the name.
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FPGA architecture
SLICE
Modern FPGA SLICEs feature additional components that improve their utilization: a XOR gate
(the most demanding logic function), signal switches (to enable independent utilization of the
LUT and the register), switches for LUT function selection, etc.
Spartan-3: ½ SLICE
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FPGA architecture
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FPGA architecture
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Memories in FPGA
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Block RAM memories
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Block RAM memories
BRAM
Properties:
• True Dual Port
• Works at FPGA core clock frequency
• Synchronous, optional output registers
• Native support of ECC
Usage
• Fast memories (RAMs, CACHEs)
• Core of a FIFO memory
• Frame/packet buffers
• ROM memories
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Block RAM memories
BRAM 36 kb
Available modes:
1 x 36k 2 x 18k
• 32K x 1 • 16K x 1
• 16K x 2 • 8K x 2
• 8K x 4 • 4K x 4
• 4K x 9 • 2K x 9
• 2K x 18 • 1K x 18
• 1K x 36 • 512 x 36
• 512 x 72
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Block RAM memories
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Block RAM memories
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Block RAM memories
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Block RAM memories
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Block RAM memories
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Block RAM memories
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Block RAM memories
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RAM memories
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RAM memories
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RAM memories
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RAM memories
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Thank You for Your attention!