Advanced Digital Electronics Laboratory Exp.

10
Experiment 10
Signals and Variables:
Design Example Count Ones Circuit and Intensity Encoder
Learning Objectives:
1. Study the Signals, variables and Constants in VHDL language.
2. To design a VHDL code for a Count Ones circuit using Xilinx® ISE 9.2i, then simulation results
should be obtained.
3. To design a VHDL code for an Intensity Encoder using Xilinx® ISE 9.2i, then simulation results
should be obtained.
Equipment and Materials:
Full version of Xilinx ISE 9.2i software installed on your laboratory personal computer.
Introduction:
VHDL provides two objects for dealing with non-static data values: SIGNAL and VARIABLE.
It also provides means for establishing default (static) values: CONSTANT and GENERIC. SIGNAL.
CONSTANT and SIGNAL can be global (that is, seen by the whole code), and can be used in
either type of code, concurrent or sequential. A VARIABLE, on the other hand, is local, for it can
only be used inside a piece of sequential code (that is, in a PROCESS, FUNCTION, or PROCEDURE)
and its value can never be passed out directly. As will become apparent, the choice between a
SIGNAL or a VARIABLE is not always easy.
o CONSTANT serves to establish default values. Its syntax is:
CONSTANT name : type := value;
Examples:
CONSTANT set_bit : BIT := '1';
CONSTANT datamemory : memory := (('0','0','0','0'),
('0','0','0','1'),
('0','0','1','1'));
A CONSTANT can be declared in a PACKAGE, ENTITY, or ARCHITECTURE. When declared in
a package, it is truly global, for the package can be used by several entities. When declared in an
entity (after PORT), it is global to all architectures that follow that entity. Finally, when declared
in an architecture (in its declarative part), it is global only to that architecture’s code. The most
common places to find a CONSTANT declaration is in an ARCHITECTURE or in a PACKAGE.
o SIGNAL serves to pass values in and out the circuit, as well as between its internal
units. In other words, a signal represents circuit interconnects (wires).Its syntax is:
SIGNAL name : type [range] [:= initial_value];
Examples:
SIGNAL control: BIT := '0';
SIGNAL count: INTEGER RANGE 0 TO 100;
SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0);
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The declaration of a SIGNAL can be made in the same places as the declaration of a
CONSTANT (described above). A very important aspect of a SIGNAL, when used inside a section
of sequential code (PROCESS, for example), is that its update is not immediate. In other words, its
new value should not be expected to be ready before the conclusion of the corresponding
PROCESS, FUNCTION or PROCEDURE. Recall that the assignment operator for a SIGNAL is ‘‘<=’’
(Ex.: count<=35;). Also, the initial value in the syntax above is not synthesizable, being only
considered in simulations. Another aspect that might affect the result is when multiple
assignments are made to the same SIGNAL. The compiler might complain and quit synthesis, or
might infer the wrong circuit (by considering only the last assignment, for example).
o VARIABLE Contrary to CONSTANT and SIGNAL, a VARIABLE represents only local
information. It can only be used inside a PROCESS, FUNCTION, or PROCEDURE (that is,
in sequential code), and its value cannot be passed out directly. On the other hand, its
update is immediate, so the new value can be promptly used in the next line of code.
Its syntax:
VARIABLE name : type [range] [:= init_value];
Examples:
VARIABLE control: BIT := '0';
VARIABLE count: INTEGER RANGE 0 TO 100;
VARIABLE y: STD_LOGIC_VECTOR (7 DOWNTO 0) := "10001000";
Since a VARIABLE can only be used in sequential code, its declaration can only be done in
the declarative part of a PROCESS, FUNCTION, or PROCEDURE. Recall that the assignment
operator for a VARIABLE is ‘‘:=’’ (Ex.: count:=35;). Also, like in the case of a SIGNAL, the initial
value in the syntax above is not synthesizable, being only considered in simulations.
Procedures:
1. Write a VHDL code to design a circuit that counts the number of ‘1’s in a given binary vector
using only signals.
2. Implement your designs using Xilinx ISE 9.2i tools for Spartan 3E FPGA board. Obtain a timing
diagram after simulation to verify correct outputs.
3. Record your results (VHDL code, RTL, Timing diagram)use (0,5,10,15,20…) input vectors to test
the results.
4. Repeat steps 1,2 and 3 but an internal VARIABLE is to be used instead of a SIGNAL.
5. Design an encoder that receives as input din vector, and creates from it an output vector dout
whose bits are all ‘0’s, except the bit whose index corresponds to the number of ‘1’s in din.
6. Implement your designs using Xilinx ISE 9.2i tools for Spartan 3E FPGA board. Obtain a timing
diagram after simulation to verify correct outputs.
7. Record your results (VHDL code, RTL, Timing diagram).

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Report :
1.Comment on your results.
2.Compare between Signals and Variables by completing the following table:

3.Discover the error on following VHDL code then correct it. What is the function of it?

4.Discuss the number of flip-flops inferred from the code by the compiler for Q3.