Interrupts in microprocessors

INTERRUPTS • Interrupt = any (infrequent or exceptional) event that

causes a CPU to make a temporary transfer of control from
AND its current program to another program that services the
event.
EXCEPTIONS • The processor must interrupt its current task, execute the
Interrupt Service Routine (ISR) which relates specifically
to the event that launch the interrupt.
⇒Interrupts may be generated by a variety of sources
internal and external to the CPU.
⇒Interrupts are the primary means by which IO
devices obtain the services of the CPU.
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Interrupt classification Interrupt classification

1. Interrupt requests:

1. Interrupt requests: They are asynchronous with the interrupted program.

An input electrical signal asking for services
2. Exceptions:
Special events after decode or execution of an instruction
The interrupt requests are also called hardware
interrupts.
Can be generated by sources external to CPU:
⇒ peripheral asking services from CPU
⇒ special circuitry supervising the normal operation of
the hardware

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 Interrupt classification Response of the CPU
2. Exceptions:
The CPU responds to an interrupt request or at an exception
They are synchronous with the interrupted program in a similar way:
• Save the PC (Program Counter) contents (address of the next
Exceptions produces software traps, or software interrupts instruction) and supplementary information about current state (flags,
Generated by sources internal to CPU, i.e. unusual events registers, etc.)
produced in running a program: • Load PC with the beginning address of an Interrupt Service Routine
memory address violation (ISR) and start to execute it
illegal control instruction in a user program • Finish ISR and (usually) return to the interrupted program, to the point
in the current task from which it left.
arithmetic conditions (e.g. overflow, division by zero)
• The CPU responds to an interrupt request by a transfer of control to
page fault exceptions
another program in a manner similar to a subroutine call.

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Interrupt requests (HW int.) Problems to cope

• Recognized at the boundary of an instruction:
♣ Maskable interrupts (INTR), can be blocked ∋ Peripherals must send an electrical signal to the processor
♣ Non-maskable interrupts (NMI), always recognized ∋ Identification of interrupting device and arbitration.
• Schematic representation of maskable and non-maskable interrupts: ∋ CPU must find / compute the address of the required ISR. (PC is
Microprocessor
loaded - directly or indirectly - with this address)
OR
Non-maskable
interrupt (NMI)
∋ The processor must be able to ignore interrupt requests at times
when they would be inconvenient.
Interrupt AND ∋ CPU must have a “place” where to store information about
Request
interrupted program (status information), used when “RETURN
Maskable interrupt
(INTR) from interrupt”.
Enable
INTR
S ∋ Restoring state information and transfer of control back to the
CLOCK Q interrupted program.
Disable
INTR R
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 Maskable interrupts (INTR) Non-maskable interrupts (NMI)
• INTR input allows external devices to interrupt the executing program. • NMI input generally signals a catastrophic event such as:
• To ensure recognition, the INTR input must be held until the CPU – an imminent power loss
acknowledges the interrupt (interrupt acknowledge sequence). – a memory error
• INTR input is sampled at the beginning of every instruction. – a bus parity error
• In a microcomputer (like PCs): • NMI is asynchronous
– INTR signal is usually supplied by a Programmable Interrupt Controller • A NMI automatically causes the CPU to execute the
(PIC)
service routine
– The controller’s inputs are connected to devices that require interrupt
servicing.
– ISR corresponds to a pre-fixed location in the IDT
– PIC determines the priority of multiple requests. – The CPU will not service subsequent NMI requests until the
current one has been serviced.
• The service routine vector is the entry in a IDT (Interrupt Descriptor
Table) that points to a service routine for handling the interrupt.

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Vectored and Non-vectored Examples: Non-vectored interrupts

Interrupt Requests • A NMI automatically causes the 80386 microprocessor to execute the
• Non-vectored interrupts service routine that corresponds to location 2 in the IDT.
√ pre - fixed start address for ISRs • At the 8085A microprocessor RST and TRAP interrupts. Each non-
maskable interrupt corresponds to a processor input pin and each has a
√ non-vectored interrupts are useful for small systems where
pre-assigned jump address, as given in the following table.
there are few interrupt sources and the software structure is
straightforward.
Table: Jump addresses in the 8085A
• Vectored interrupts
√ requires that the interrupting device supply the CPU with the Interrupt Address
TRAP 24h
starting address or transfer vector of ISR RST 5.5 2Ch
√ useful for microprocessors that receive interrupt request RST 6.5 34h
RST 7.5 3Ch
from several devices via the same interrupt line

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 A vectored interrupt scheme A vectored interrupt scheme with IDT
Address (hex): Main memory

Activate CPU's interrupt 0000

request input Jump to
Program Counter (16 bits) address 01C0
vv=00

0000 0000 0000 vv00

0004
vv=01 Jump to
Priority encoder and address 1010
interrupt-vector generation vv=10
0008
Jump to
vv=11 address 0040
Signals an interrupt

000C
Jump to
address F000

0040
Start
Interrupt Interrupt IHR 2
Register Mask
Register

0 1 N-1 01C0
Start
IHR 0

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Interrupt Request Lines 13 MICROPROCESSORS 14

Examples of vectored interrupts Z80 int. request (mode 2)

INT
M1+
Vector MM
IORQ
• The 8086, Z8000, MC68000, and Z80 (in mode 2) all employ a 8
I/O
interrupt vector description table (IDT). During an interrupt Device Poiter to IDT
(LSB)
acknowledge cycle an 8-bit vector is supplied which is used to point to ARTI
an entry in the vector table. The entry is the start address of the ISR INT
(MSB)
8

and it is automatically loaded into the processor's program counter.

The vector table contents are loaded by software.
• For the MC68000 and 8086 the vector table is in a fixed position in the I

memory map. In the Z8000 and Z80, however, the position of the table ARTI:
Z 80
is relative to the contents of an internal register. ISR

• An 8-bit vector allows for 256 entries in the vector table. The 8086
predefines or reserves 32 of these and care must be taken to avoid
generating these vectors externally. For MC68000, Z8000 and Z80, the
full range is available for user definition.

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 PENTIUM Interrupt system
There are three categories of interrupts, which depend on the source:
• Software interrupts: initiated with an INT instruction. For example INT
10h issues the interrupt with the hex number 10h
• Hardware interrupts: NMI and INTR. In real mode, for vectored
interrupts Pointer = 4*Vector (vector=number of interrupt).
• Exceptions: originates in the processor itself, running instructions -
corresponds to that of a software interrupt: faults, traps and abort.
⇒ Fault: a fault issues an exception prior to completing the instruction
(segment not present, overflow, coprocessor error)
⇒ Trap: issues an exception after completing instruction execution, and
the instruction is not re-executed. (debugger breakpoints, single step)
⇒ Abort: serious failures after that the recovery of program execution is
not always possible. (hardware failures, invalid system tables, division
by 0, invalid opcode, bound exception
Timing
• The time that elapses before an interrupt request is serviced depends on
several factors. The following all can affect elapsed time:
If the interrupt is masked, an INTR request will not be recognized
until interrupts are re-enabled.
If a NMI interrupt is currently being serviced, an incoming NMI
interrupt request will not be recognized until IRET instruction.
Saving the Flags register and other registers requires time.
Time must be allowed for saving and restoring a task state in
interrupt servicing routine.
Instruction are usually non-interruptible.
Priorities (exceptions, software interrupts, NMI, INTR).

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STACK MEMORY Example of hardware stack

IN
• Special memory organization that operate on the principle
“Least In First Out” (LIFO).
• Temporarily storing memory, used by the interrupt system, the I2
subroutine call / return mechanism, rapid storing and loading
temporarily data, passing parameters to procedures, etc. I1
Y1 Y2 YN
• Stack memory implementations: ToS c01 c02 c0N
– Hardware stack (CPU internal registers): high speed, but P c11 c12 c1N
limited storing capacity U c21 c22 c2N P
S O
– Software stack (in main memory): high capacity but lower H c31 c32 c3N P
speed
cM1 cM2 cMN

R1 R2 RN

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 HARDWARE STACK HARDWARE STACK
(4 words depth, 8 bits/word) (4 words depth, 8 bits/word)
PUSH A a7 a6 a5 a4 a3 a2 a1 a0

TS TS

stack stack

BS BS

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HARDWARE STACK HARDWARE STACK

(4 words depth, 8 bits/word) (4 words depth, 8 bits/word)
PUSH B b7 b6 b5 b4 b3 b2 b1 b0

TS a7 a6 a5 a4 a3 a2 a1 a0 TS a7 a6 a5 a4 a3 a2 a1 a0

stack stack

BS BS

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 HARDWARE STACK HARDWARE STACK
(4 words depth, 8 bits/word) (4 words depth, 8 bits/word)
POP

TS a7
b a6
b a5
b a4
b a3
b a2
b a1
b a0
b TS b7 b6 b5 b4 b3 b2 b1 b0
a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0
stack stack

BS BS

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HARDWARE STACK HARDWARE STACK

(4 words depth, 8 bits/word) (4 words depth, 8 bits/word)
POP PUSH C c7 c6 c5 c4 c3 c2 c1 c0
b7 b6 b5 b4 b3 b2 b1 b0

TS b7
a b6
a b5
a b4
a b3
a b2
a b1
a b0
a TS a7 a6 a5 a4 a3 a2 a1 a0
a7 a6 a5 a4 a3 a2 a1 a0
stack stack

BS BS

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 HARDWARE STACK HARDWARE STACK
(4 words depth, 8 bits/word) (4 words depth, 8 bits/word)
PUSH D d7 d6 d5 d4 d3 d2 d1 d0

TS a
c7 a
c6 a
c5 a
c4 a
c3 a
c2 a
c1 a
c0 TS c7 c6 c5 c4 c3 c2 c1 c0
a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0
stack stack

BS BS

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HARDWARE STACK HARDWARE STACK

(4 words depth, 8 bits/word) (4 words depth, 8 bits/word)
PUSH E e7 e6 e5 e4 e3 e2 e1 e0

TS d
c7 d
c6 d
c5 d
c4 d
c3 d
c2 d
c1 d
c0 TS d7 d6 d5 d4 d3 d2 d1 d0
a
c7 a
c6 a
c5 a
c4 a
c3 a
c2 a
c1 a
c0 c7 c6 c5 c4 c3 c2 c1 c0
stack stack
a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0
BS BS

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 HARDWARE STACK HARDWARE STACK
(4 words depth, 8 bits/word) (4 words depth, 8 bits/word)
PUSH G g7 g6 g5 g4 g3 g2 g1 g0

TS d
e7 d
e6 d
e5 d
e4 d
e3 d
e2 d
e1 d
e0 TS e7 e6 e5 e4 e3 e2 e1 e0
d
c7 d
c6 d
c5 d
c4 d
c3 d
c2 d
c1 d
c0 d7 d6 d5 d4 d3 d2 d1 d0
stack stack
a
c7 a
c6 a
c5 a
c4 a
c3 a
c2 a
c1 a
c0 c7 c6 c5 c4 c3 c2 c1 c0
BS a7 a6 a5 a4 a3 a2 a1 a0 BS a7 a6 a5 a4 a3 a2 a1 a0

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HARDWARE STACK
(4 words depth, 8 bits/word)
Software (implemented) stack.
• Administration of stack is made by a special addressing register called
Stack Pointer (SP). SP register always contains the address of the
Top of the Stack (ToS).
TS e7
g e6
g e5
g e4
g e3
g e2
g e1
g e0
g
• Intel convention: stack memory grow towards lower addresses in MM
d7
e d6
e d5
e d4
e d3
e d2
e d1
e d0
e
stack • Filling in a data in stack memory (PUSH operation) means
d
c7 d
c6 d
c5 d
c4 d
c3 d
c2 d
c1 d
c0 decrementing the content of SP and then storing the data at the address
pointed by SP
BS a
c7 a
c6 a
c5 a
c4 a
c3 a
c2 a
c1 a
c0
• Pull out data from stack memory (POP operation) means reading data
a7 a6 a5 a4 a3 a2 a1 a0 addressed by SP and then updating the content of SP.
• The transfer with stack memory can be done in two ways:
automatic transfer.
stack transfer (special) instruction.
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 Example subroutine calls Subroutine calls-stack contents
MP P1 P2 time MP P1 P2

IN b: PUSH R1
Main IN
•
PUSH R2
PUSH R3 <t2>→ c: IN
IN b: PUSH R1 address memory •
•
<t1>→ IN
IN
IN

IN PUSH R2 t0 t1 t2 t3 t4 • •
IN . • •
• PUSH R3 <t2>→ c: IN <t0>→ .
CALL b
•
CALL c
. •

• <t1>→ IN IN <t4>→
a: IN <t3>→ d: IN
•
IN
RET

• IN SP x-7: dL •
.
.
•
•

• • • POP R3
• POP R2
x-6: dH
• •
POP R1
IN . RET

<t0>→ . • . • R3 END

CALL b CALL c SP SP x-5:

a: IN <t3>→ d: IN IN R2
x-4:
<t4>→ • RET
. • x-3: R1
• . •
• POP R3 x-2: aL
• POP R2
x-1: aH
POP R1
RET
SP SP x: ← initial ToS
END

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Example Example

• Describe the contents of Stack memory and Program

counter for the next program, that start on address 1
SP 2

PC= 1
call 6

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 Example Example

SP 11
SP 7 7 7
2 2 2 2 2

PC= 1 6 PC= 1 6 10
call 10 call 3

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Example Example
SP 4 SP 4 4
11 11 11 11 11
7 7 7 7 7 7 7
2 2 2 2 2 2 2 2 2

PC= 1 6 10 3 PC= 1 6 10 3 13
call 13 return

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 Example Example
4 4 4 4
SP 11 11 11 11 11 11 11 11
7 7 7 7 7 SP 7 7 7 7 7 7
2 2 2 2 2 2 2 2 2 2 2 2 2

PC= 1 6 10 3 13 4 PC= 1 6 10 3 13 4 11
return return

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Example Example
4 4 4 4
11 11 11 11 11 11 11 11
7 7 7 7 7 7 7 7 7 7 7 7
SP 2 2 2 2 2 2 2 2 SP 2 2 2 2 2 2 2 2

PC= 1 6 10 3 13 4 11 7 PC= 1 6 10 3 13 4 11 7 2
return halt

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 Why Register Windows ?
• The main idea behind the use of register windows is to minimize
memory accesses.
• Procedure call and return occurs quite often in high-level
programming languages
– When translated into machine language, a procedure call produces
a sequence of instructions that save register values, pass
Overlapped parameters needed for the procedure, and then calls a subroutine to
execute the body of the procedure
– After a procedure return, the program restores the old register

Register Windows values, passes results to the calling program, and returns from the
subroutine
• Saving and restoring registers and passing of parameters and
results involve time consuming operations
• In RISC, overlapped register windows are used to avoid the
need for saving and restoring register values
– each procedure is allocated its own bank of registers
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Why Register Windows ? EXAMPLE – OVERLAPPED

WINDOWS
• A procedure call will automatically switch the CPU to use
a different fixed-size window of registers. level i+1 level i
• In order to minimize the actual movement of parameters
among the calling and the called procedures, each set of Output Registers
registers is divided into three subsets:
– Input (Parameter) Registers, Local
– Local Registers, and Registers
Call procedure
– Output (Results) Registers.
• When a procedure call is made, a new overlapping window Input Registers Output Registers
will be created such that the output registers of the caller
are physically the same as the input registers of the called Local
procedure. Return Registers
• This overlap allows parameters to be passed among
procedure without actual movement of data. Input Registers

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 R15 Common
to D and A

The concept of the overlapped R10

R73
Local to D

register window R64

The R63

R58
R63

R58
Common
to C and D
EXAMPLE:
• The system has a total of 74 registers concept of PROC D R57
Local to C

• Registers R0 through R9 are global registers that hold

parameters shared by all procedures. the R48
R46 R46 Common
to B and C
R42 R42
• The other 64 registers are divided into four windows to overlapped PROC C R41
accommodate procedures A, B, C, and D Local to B

• Each register window consists of 10 local registers (local

variables) and two sets of 6 registers common to adjacent
register R32
R31 R31 Common
to A and B
windows
• The common overlapped registers permit parameters to be
window R9
R26
PROC B
R26
R25
Local to A

passed without the actual movement of data R16

R0
• Only one register window is activated at any given time R15 Common
to A and D
Global R10
53 registers 54
MICROPROCESSORS MICROPROCESSORS PROC A

R73

Circular Buffer of windows

R64

The R63

R58
R57 • Two pointers:
concept of – CWP - current window pointer - identifies the current
register window
the R48
R46
– SWP - saved window pointer
R42
overlapped Current
R41
Window overlapp
– The save operation (the called procedure is “saving”)
allocates a new register set by decrementing the CWP
register Register
Window
R32 – The restore operation de-allocates a register set by
R31
decrementing the CWP
window R26
R25

R16
R15
R10
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 Circular Buffer of windows
SWP Window 1

Input Local Input

P1 P1 P2

Call
procedure
Local Local
Window 4 P4 P2 Window 2
Return

Input Local Input

P4 P3 P3

CWP=1
MICROPROCESSORS Window 3 57