1

Top-level view of
Computer Function and
Interconnection
CHAPTER 02
 Contents
 Understand the basic elements of an instruction cycle and the
role of interrupts.
 Describe the concept of interconnection within a computer
system (buses)
 Explain the need for multiple buses arranged in a hierarchy.
 Assess the relative advantages of point-to-point
interconnection compared to bus interconnection.
 Present an overview of QPI, PCIe
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The Von Neumann Machine

Computer designs are based on concepts developed at the Institute for
Advanced Studies, Princeton. Such a design is referred to as the von
Neumann architecture and is based on three key concepts:

 Data and instructions are stored in a single read–write memory.

 The contents of this memory are addressable by location, without

regard to the type of data contained there.

 Execution occurs in a sequential fashion (unless explicitly modified)

from one instruction to the next
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• Instruction Cycle
Computer • Interrupts
Functions
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Instruction Cycle
INSTRUCTION FETCH & EXECUTE

 The basic function performed by a computer is execution of a program,

which consists of a set of instructions stored in memory.

 Program execution consists of repeating the process of instruction fetch

and instruction execution. The instruction execution may involve several
operations and depends on the nature of the instruction.

 The fetched instruction is loaded into a register in the instruction register

(IR).
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Instruction Cycle
Activities

1. Students read the example of a program execution of an

hypothetical machine (from p.70) to understand the processor’s
Instruction Fetch & Execute cycle.
 Watch video Fetch-decode-excecute cycle
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Instruction Cycle State Diagram

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Polling vs
Interrupt
 Interrupt vs Polling 12

Interrupt Polling
Basic Device notify CPU that it CPU constantly checks
needs CPU attention device status whether it
needs CPU's attention.
Mechanism An interrupt is a hardware Polling is a protocol
mechanism
Servicing Interrupt handler services CPU services the device.
the Device.
Indication Interrupt-request line Command-ready bit
indicates that device needs indicates the device
servicing. needs servicing.
Occurrence An interrupt can occur at CPU polls the devices at
any time. regular interval
Example Let the bell ring then open Constantly keep on
the door to check who has opening the door to
come. check whether anybody
has come.
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Interrupt
 An interrupt is a hardware mechanism that
enables CPU to detect that a device needs
its attention. Interrupt
handler
 The CPU has a wire interrupt-request
line (IRQ) which is checked by CPU after
execution of every single instruction. IRQ
 When CPU senses an interrupt signal on the
IRQ line, CPU stops its currently executing
task and respond to the interrupt send by
Iret
I/O device by passing the control to interrupt
handler. The interrupt handler then service
the device.
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Interrupts
 Way to improve processing efficiency.
 Classes of interrupts

Generated by some condition that occurs as a result of an

Program instruction execution, such as arithmetic overflow, division by zero,
(software) attempt to execute an illegal machine instruction, or reference
outside a user’s allowed memory space.

Timer Generated by a timer within the processor. This allows the

(Hardware) operating system to perform certain functions on a regular basis.

Generated by an I/O controller, to signal normal completion of an

I/O
operation, request service from the processor, or to signal a variety
(Hardware)
of error conditions.
Hardware
Generated by a failure such as power failure or memory parity
Failure
error.
(Hardware)
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Program flow with/without interrupts

Without interrupt With interrupt

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Transfer control via interrupt

 From the point of view of the user program, an interrupt is just an
interruption of the normal sequence of execution.

 When the interrupt processing is completed, execution resumes (Thus,

the user program does not have to contain any special code to
accommodate interrupts; the processor and the operating system
are responsible for suspending the user program and then resuming it
at the same point.
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Multiple Interrupts

Sequential interrupt processing Nested interrupt processing

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Interconnection
Structures
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Computer modules
 Computer is a network of basic modules.

 There must be paths for connecting the modules.

 The collection of paths connecting the various modules is called the

interconnection structure. The design of this structure will depend on
the exchanges that must be made among modules.

CPU

RAM ROM I/O

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Memory module
 A memory module will consist of N words of equal length.

 Each word is assigned a unique numerical address (0, 1, …, N - 1)

 A word of data can be read from or written into the memory.

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I/O module
 Functionally similar to memory.

 An I/O module may send interrupt signals to the processor.

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Processor
 The processor reads in instructions and data, writes out data after
processing, and uses control signals to control the overall operation
of the system.

 The processor also receives interrupt signals.

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Types of transfers
The interconnection structure must support the following types of
transfers

 Memory → processor: The processor reads/writes an instruction or a

unit of data from/to memory.

 I/O → processor: The processor reads/sends data from/to an I/O

device via an I/O module.

 I/O to or from memory: an I/O module is allowed to exchange data

directly with memory, without going through the processor, using
direct memory access.
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Bus interconnection
 A bus is a communication pathway connecting two or more devices.

 Key characteristic of a bus: a shared transmission medium. Multiple

devices connect to the bus, and a signal transmitted by any one device
is available for reception by all other devices attached to the bus. If two
devices transmit during the same time period, their signals will overlap
and become garbled. Thus, only one device at a time can successfully
transmit

 A bus consists of multiple lines. Each line is capable of transmitting signals

representing binary 1 and binary 0. Several lines of a bus can be used to
transmit binary digits simultaneously (in parallel). For example, an 8-bit unit
of data can be transmitted over eight bus lines.
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Bus structure
 Computer systems contain a number of different buses that provide
pathways between components.

 A bus that connects major computer components (processor,

memory, I/O) is called a system bus.

 The most common computer interconnection structures are based

on the use of one or more system buses
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Bus Structure
A system bus consists of from about fifty to hundreds of separate lines
and can be classified into three functional groups: data, address, and
control lines:

 Data bus: 32, 64, 128 lines (width → system performance)

 Address bus: 8, 16, 32 lines (width → max memory capacity)

 Control bus:
 Memory read/write
 I/O read/write
 Bus request/grant
 Interrupt request/ACK
 Clock
 Reset
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Multiple-Bus Hierachies
 A great number of devices connected to the bus will suffer system
performance (bottleneck).

Traditional bus architecture

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Multiple-Bus Hierachies

High-performance architecture
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Computer Buses

Bus speed = 66-800MHz

Core speed (FSB) = Bus x multiplier

66MHz

33,66MHz

8 MB/s then
33,66,100,133

High-performance architecture
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Bus Arbitration
 Because only one unit at a time can successfully transmit over the
bus, some method of arbitration is needed.

 Two types of arbitration: centralized and distributed.

 Centralized scheme: a bus controller or arbiter, is responsible for

allocating time on the bus.

 Distributed scheme: No central controller, each module contains

access control logic and the modules act together to share the bus.

 The device which initiates data transfer is called the master, while the
other device involves in the data exchange is called the slave.
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Bus Timing
 The way in which events are coordinated on the bus.

 Buses use either synchronous timing or asynchronous timing.

Synchronous bus operation
35
Asynchronous Bus Operation
36
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Point-to-Point Interconnect
 The electrical constraints encountered with increasing the frequency
of wide synchronous buses. At higher and higher data rates, it
becomes increasingly difficult to perform the synchronization and
arbitration functions in a timely fashion.

 Contemporary systems increasingly rely on point-to-point

interconnection rather than shared buses.

 Compared to the shared bus, the point-to-point interconnect has

lower latency, higher data rate, and better scalability.
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Significant characteristics
 Multiple direct connections: Multiple components within the system
enjoy direct pairwise connections to other components. This
eliminates the need for arbitration found in shared transmission
systems.

 Layered protocol architecture: As found in network environments,

such as TCP/IP-based data networks, these processor-level
interconnects use a layered protocol architecture, rather than the
simple use of control signals found in shared bus arrangements.

 Packetized data transfer: Data are not sent as a raw bit stream.
Rather, data are sent as a sequence of packets, each of which
includes control headers and error control codes.
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Intel’s QuickPath Interconnect

A B

C D
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QPI Protocol
 QPI is defined as a four-layer protocol architecture, encompassing
the 4 layers:
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QPI Layers
1. The Physical layer:

 The unit of transfer at

the Physical layer is 20 bits,
which is called
a Phit (physical unit)

 Each bit is transmitted on

a differential pair (lanes).

 20 lanes + clock line in each direction

 84 lines in total (both direction)

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QPI Layers
2. The Link layer:

 Performs two key functions: flow control and error control.

 Operate on the level of the flit (flow control unit). The basic unit of
transfer is the 80-bit flit, which has 64 bits for data, 8 bits for "link-layer
header", and 8 bits for error detection (four 20-bit transfers, two per
clock).

3. The Routing layer: determine the course that a packet will traverse
across the available system interconnect.

4. The Protocol layer: the packet is defined as the unit of transfer

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QPI transfer rate

 QPI operates at a clock rate of 2.4 GHz, 2.93 GHz, 3.2 GHz, 4.0 GHz or 4.8 GHz.

 At 3.2 GHz, the QPI transfers two data per clock cycle, making the bus to work
as if it was using a 6.4 GHz clock rate or 6.4 GT/s (giga transfers per second – a
unit of Intel).

 Since 16 bits are transmitted per time ➔ a maximum theoretical transfer rate
of 12.8 GB/s on each direction (6.4 GHz x 16 bits / 8) or 25.6GB/s for two
datapaths

QPI

20 bits 20 bits
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QPI transfer rate vs FSB

 At 3.2GHz, QPI transfer rate on each direction is 12.8 GB/s

 At 1600 MHz FSB (which actually 400MHz transferring 4 data per clock cycle )

 Transfer rate on a 64-bit wide fsb:

8 bytes/transfer x 400 MHz x 4 transfers/cycle = 12.8 GB/s
QPI FSB
Transfer rate: 12.8 GB/s (clock = Transfer rate: 12.8 GB/s
3.2Ghz) (clock = 400MHz)
On each direction For both read/write operations
Data & IO separate → less busy → Both Memory and IO requests →
more bandwidth less bandwidth
84 wires 150 wires
20 lines on each direction →
organized in four 5-bit lanes → fail-
safe default
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PCI Express (PCIe)

 PCI is a popular high-bandwidth, processor- independent bus that
can function as a peripheral bus.

 Compared with other common bus specifications, PCI delivers better

system performance for high-speed I/O subsystems (e.g., graphic
display adapters, network interface controllers, and disk controllers).

 PCI has not been able to keep pace with the data rate demands of
attached devices.

 PCIe is a point-to-point interconnect scheme (like QPI) intended to

replace bus-based schemes PCI.
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PCI Express Lanes

 Typical figures

Trans.
Ver Year Rate x1 x16
(GT/s) (GB/s (GB/s)
1 2003 2.5 0.25 4.00
2 2007 5 0.50 8.00
3 2010 8 0.96 15.75
4 2017 16 1.97 31.51
5 2019 32 3.94 63.02