CHAPTER Two

THE CENTRAL PROCESSING

UNIT (CPU)
1
part 1
 OUTLINE
 Instruction set characteristics & functions
 Interrupt
 Machine Instruction Characteristics
 Instruction Set Design
 Types of Operands
 Types of Operations
 Addressing Mode
 Instruction Format
 Instruction Cycle
 Processor Structure and Function
 Processor Organization
 Register Organization
 RISC & CISC
 Bus inter connection

2
 Chapter 2
 CPU
 Exchanges data with the memory and I/O.
 Uses the following registers to exchange data with the memory.
 Memory address register (MAR)

 Specifies the address of memory for

the next read or write
 Memory buffer register (MBR)
 Holds the data to be written into the memory

 Holds the data read from the memory

 Another important registers are the following:

 Program counter (PC)
 Holds the address of the instruction to be fetched

next. 3
 Instruction register (IR)

 Holds the fetched instruction

Chapter 2
 CPU
 Uses the following registers to exchange data with
I/O module
 I/O address register (I/OAR)
 Specifies a particular I/O device

 I/O buffer register (I/OBR)

 Holds the data to be exchanged between

an I/O module and CPU

 Much of the computer architecture/organization is hidden from a
high level language programmer.
 What is an instruction set?
 The collection of different instructions that are understood
by a CPU or that the CPU can execute.
4
INTRODUCTION…
 Instruction set is a boundary where
 Computer designer and computer programmer can view the
same machine.
 Computer program is a set of instruction that specific the
operations, operands and sequence by which processing has to
occur.
  It provides
From the functional
Designer’s Point ofrequirements
view for the CPU.
 It implementing the machine instruction set.

 From Assembly Language Programmer’s Point of view

 It enables to be aware of the register and memory
structure, types of data directly supported by the machine and
 the functioning of the ALU

5
 Chapter 2

 Basic Function
 Execution of a program
 Processing of Instruction consists of two
steps
 Fetch
 Execute

 Together called an Instruction cycle

6
INSTRUCTION CYCLE
 Two steps:
 Fetch
 Execute

7
 FETCH CYCLE
 Program Counter (PC) holds the address of
next instruction to be fetched.
 Processor fetches instruction from memory location
pointed by PC
 Increment PC

 Unless told otherwise

 Instruction loaded into Instruction Register (IR)

8
 EXECUTE CYCLE
 Processor interprets instruction and performs required
actions
 Processor-memory
 data transfer between CPU and main
memory
 Processor -I/O
 Data transfer between CPU and I/O
module
 Data processing
 Some arithmetic or logical operation on
data
 Control
Alteration of sequence of execution


 e.g. jump
 Execution of an instruction may involve a combination of 9
above actions
EXAMPLE OF PROGRAM EXECUTION

10
INTERRUPTS
 It’s a mechanism by which other modules (e.g. I/O)
may
interrupt normal processing of the processor.
 Interruption of the normal sequence of execution
 Provided to improve processing efficiency.
 Common classes of interrupts
 Program
 e.g. overflow, division by zero
 Timer
 Generated by internal processor timer
 Used in pre-emptive multi-tasking
 I/O
 from I/O controller
 Hardware failure
 e.g. power failure, memory parity error 11
INTERRUPT CYCLE
 Added to instruction cycle
 Processor checks for interrupt
 Indicated by an interrupt signal
 If no interrupt, fetch next instruction
 If interrupt pending:
 Suspend execution of current program
 Save context
 Set PC to starting address of interrupt handler
routine

 Process interrupt
 Restore context and continue interrupted
12
program
INSTRUCTION CYCLE WITH INTERRUPTS

13
TRANSFER OF CONTROL VIA INTERRUPTS

14
MULTIPLE INTERRUPTS
 Two approaches to deal with multiple interrupts
 Disable interrupts
 Processor will ignore further interrupts
whilst processing one interrupt
 Interrupts remain pending and are checked after first
interrupt has been processed
 Interrupts handled in sequence as they occur
 Define priorities
 Low priority interrupts can be interrupted by higher
priority interrupts
 When higher priority interrupt has been
processed, processor returns to previous interrupt 15
MULTIPLE INTERRUPTS – SEQUENTIAL
DISABLE INTERRUPTS

16
MULTIPLE INTERRUPTS – NESTED
PRIORITIZED INTERRUPTS

17
TIME SEQUENCE OF MULTIPLE INTERRUPTS

18
INTERCONNECTION STRUCTURES
 A computer consists of a set of components
 All the units must be connected
 The collection of paths connecting various units
 Interconnection structure
 Different type of connection for different type of
unit
 Memory
 Input / Output
 CPU
 There are a number of possible
interconnection
structures, the most common are: 19
 Single and multiple BUS structures
COMPUTER MODULES

20
MEMORY CONNECTION
 Receives and sends data
 Receives addresses (of locations)

 Receives control signals

 Read
 Write
 Timing

21
INPUT/OUTPUT CONNECTION
 Similar to memory from computer’s viewpoint
 Output
 Receive data from computer
 Send data to peripheral
 Input
 Receive data from peripheral
 Send data to computer

22
CPU CONNECTION
 Reads instruction and data
 Writes out data (after processing)

 Sends control signals to other units

 Receives (& acts on) interrupts

23
 BUS INTERCONNECTION
 What is a BUS ?
 A communication pathway connecting two or more
devices
 Consists of multiple lines, each line capable of transmitting
signals representing binary 1 or binary 0

 Multiple devices can be connected to the same bus

 A shared transmission medium
 A bus that connects major computer components
 System bus

24

34
 DATA BUS

 Carries data
 Remember that there is no difference between
“data” and “instruction” at this level
 Width is a key determinant of performance
 8, 16, 32, 64 bit

25
 ADDRESS BUS

 Identify the source or destination of data

 e.g. CPU needs to read an instruction (data) from a given
location in memory
 Bus width determines maximum memory capacity of
system
 e.g. 8080 has 16 bit address bus giving 64k address space

26
CONTROL BUS
 Control
and timing
information
 Memory read/write signal
 Interrupt request
 Clock signals

27
Operation of bus
 If one module wishes to send data to another,
it must
 Obtain the use of the bus
 Transfer data via the bus

 Ifone module wishes to request data from

another, it
must
 Obtain the use of the bus
 Transfer a request to the other module over the

appropriate control and address lines

 Wait for the second module to send the data 28
 Single Bus Problems
 If many number of devices are connected to a
single bus, performance will suffer:
Reason
 More devices, the greater the bus length, the
greater the propagation delay
 The bus becomes a bottleneck as the aggregate
data transfer approaches the capacity of bus
 Solutions
• Increasing the data rate that the bus can carry
• Using the wider bus

 Most systems use multiple buses to

overcome these problems 29
Multiple Buses
 A Traditional Bus
Architecture

30
Multiple Buses…
 A High-speed Bus
Architecture

31
ELEMENTS OF BUS DESIGN
 Basic design elements that serves to classify and
differentiate buses:
 Bus Types
o Dedicated, Multiplexed
 Method of Arbitration
 Centralized, Decentralized
 Timing
 Synchronous, Asynchronous
 Bus Width
 Address, Data

32
ELEMENTS OF BUS DESIGN…
 Bus Types
Dedicated Bus
 Functionally dedicated bus
 A bus line that is permanently assigned to one function

 E.g. separate data and address lines

 Physically dedicated bus
 Refers to use of multiple buses, each of which connects

only a subset of modules

 E.g. use of an I/O bus to interconnect all I/O modules
 Advantage
 High throughput --- less contention
 Disadvantage
 Increases size and cost of the system
33
 ELEMENTS OF BUS DESIGN…
 Bus Types...
Multiplexed Bus

 A bus that uses the same lines for multiple purposes at

different times, using time multiplexing

E.g. Address and data information may be transmitted over the
same set of lines using Address Valid control line
 Advantage
 Uses fewer lines, which saves space and usually cost
 Disadvantage
 More complex circuitry needed within each module
 Reduction in performance

• Certain events that share the same lines cannot takes

place in parallel
34
ELEMENTS OF BUS DESIGN…
 Method of Arbitration
 More than one module may need control of the bus
 BUT, only one module may control bus at one time
 Who should take control of bus ?
 A judge or arbiter is needed
 Two methods exist
 Centralized
 Decentralized

35
 ELEMENTS OF BUS DESIGN…
 Method of Arbitration...
 Centralized
 A single hardware device (bus controller/arbiter)
 It may be part of the processor or separate module
 Distributed
 There is no central controller
 Each module contains access control logic

 The module act together to share the bus

36
 ELEMENTS OF BUS DESIGN…
 Timing
 Buses use either synchronous timing or asynchronous
timing

 Synchronous timing
 Occurrence of events on the bus is determined by a clock
 Control bus includes clock line

 Which carries a regular sequence of alternating 1’s and 0’s

 A single 1-0 is referred to as a clock cycle

 All devices on the bus can read clock line

 All events start at the beginning of a clock cycle

 Usually a single cycle for an event

37
ELEMENTS OF BUS DESIGN…
 Timing...
 Synchronous timing
 A simplified diagram for synchronous read and write timing
diagram

38
ELEMENTS OF BUS DESIGN…
 Timing...
 Asynchronous timing
 The Occurrence of one event on the bus follows and depends
on the occurrence of a previous events
 A simplified diagram for asynchronous read timing diagram

39
ELEMENTS OF BUS DESIGN…
 Timing...
 Asynchronous timing
 A simplified diagram for write timing
asynchronous diagram

40
 Processor Structure and Function
The architectural design of the CPU is Reduced instruction set computing
(RISC) and Complex instruction set computing (CISC).

RISC is a computer that only uses simple commands that can be divided into
several instructions that achieve low-level operation within a single CLK cycle.

CISC is a computer where single instructions can perform numerous low-level

operations like a load from memory, an arithmetic operation, and a memory
store or are accomplished by multi-step processes or addressing modes in single
instructions.
RISC Vs CISC

41
 RISC Vs CISC
 It has no memory unit and uses a
separate hardware to implement
instructions.
 has a hard-wired unit of
programming.
 It is a complex compiler design.
 calculations are faster and more
precise.
 decoding of instructions is simple.
 Execution time is very less.
 It does not require external memory
for calculations.
 Pipelining is easy.
 Code expansion can be a problem.
 It has a memory unit to
implement complex.
 has a microprogramming unit
instructions.
 It is an easy compiler design.
 calculations are slow and
precise
 decoding of instructions is
complex
 Execution time is very high.
 It requires external memory
for calculations.
 Pipelining does not function.
 Code expansion is not a
problem.
42
 Applications of RISC and CISC

RISC is used in high-end applications like video processing,

telecommunications and image processing.

CISC is used in low-end applications such as security systems, home

automation, etc.

rt 1
pa
of
nd
E
43