Multistage Amplifiers 11-1 GAIN RELATIONS IN MULTISTAGE AMPLIFIERS In many applications, a single emplifier cannot furnish all the gain that is required to drive 1 particular kind of load. For example, a speaker represents a “‘heavy" load in an audio amplifier system, and several amplifier stages may be required to ‘boost’ a signal orig inating at a microphone or magnetic tape hedd to a level sufficient to provide a large amount of power to the speaker. We hear of preamplifiers, power amplifiers, and output ‘amplifiers, all of which constitue stages of amplification in such a system. Actually, each of these components may itself consist of a number of individual transistor amplifier stages. Amplifiers that create voltage, current, and/or power gain through the use of two or ‘more stages are called multistage amplifiers. ‘When the outpat of one amplifier stage is connected to the input of another, the amplifier stages are said to be in cascade. Figure 11.1 shows two stages connecte cascade. To illustrate how the overall voltage gnin of the combination is computed, let us assume that the input tothe first stage is 10 mV rms, and that the voltage gain ofeach stage isAy = Az = 20, as shown in the figure. The output of the fist stage is A,y,, = 20(10 mV ‘mns) = 200 mV sms. Thus, the input to the second stage is 200 mV rms. The output of the second stage is therefore Azv2 = 20(200 mY mms) = 4 V rms. Therefore, the overall voltage gain is Ya, Aims a va 10 mV rms Notice that Ay = AsA2 = (20)(20) = 400. Figure 11.2 shows an arbitrary number (n) of stages connected in cascade. Note that the output of each stage isthe input to‘the succeeding One Vai = vin. Yoo = vine etc.) We ‘will derive an expression for the overall voltage gain v, /v in termsof the individual stage gains Ay, Aa, .... Ay. We assume that each stage gain Ay, Aa... Ay is the value of the voltage gain between input and output of a stage with all other stages connected (more about that important assumption later). 400418 MULTISTAGE AMPLIFIERS yy = 10m ms toy = 8 = 200 RV Ems J Figure 11.2 n amplifier stages connected in cascade. The output voltage ‘of each stage is the input voltage to the next stage. By definition, Yor = Anvan any Also, 7 Vor = Aavn = Aa¥ot a2 Substinuting voy from (11.1) into (11.2) gives Yon = (ArAdva. a3) Similarly, Yes = Asvis = Asvor and, from (11.3), Yea = (AsA2ADWa Continuing in this manner, we eventually find ‘Therefore, Voal¥a = Anda «= AxAL an) ‘Equation 11.4 shows that the overall voltage gain of n cascaded stages is the product of the individual stage gains (not the wei) In general, any one or more of the stage gains can beGAIN RELATIONS IN MULTISTAGE AMPLIFIERS 419. negative, signifying, as usual, that the stage causes a 180° phase inversion. It follows from equation 11.4 that the cascaded amplifiers will cause the output ofthe last stage (Yon) to be out of phase with the input to the frst stage (vq) if there are an odd number of inverting stages, and will cause ¥,., 0 be in phase with vy if there are an even (or 7270) ‘number of inversions. ‘To find the overall voltage gain ofthe cascaded system in dB, we ignore the algebraic signs of each stage gain and compute src (2) = 20 logio Anna «+ Ard) = 20 logio Ay + 20 logAy-t +... + 20 logics + 20 logioAr = Ay (AB) + Ani (QB) +... + Az (4B) + A, (4B) (ALS) Equation 11.5 shows thatthe overall voltage gain in dB is the sum of the individual stage gains expressed in dB, Equations similar to (11.4) and (11.5) for overall current gain and overall power gain in terms of individual stage gains are casily derived. Our derivation of equation 11.4 did not include the effeet of source or load resistance ‘on the overall voltage gain. Source resistance rs causes the usual voltage division to take place at the input tothe first stage, and load resistance rz causes voltage division to occur between r, and the output resistance of the last stage. Under those circumstances, the overall voltage gain between load and signal source becomes: ze (eB alates : aa a) 6) Where rij = input resistance to first stage and 7a output resistance of last stage. [Example 11.1. Figure 11.3 shows a three-stage amplifier and the ac rms voltages at several points inthe amplifer. Note that vis the input voltage delivered by a signal source having zero resistance and that vs is the output voltage with no load connected. 1, Find the voltage gain of each stage and the overall voltage gain sv). 2, Repeat (1) in terms of dB. 3. Find the overall voltage gain vz/vs when the multistage amplifier is driven by a signal source having resistance 2000 02 and the load is 25 (2. Stage | has input resistance 1k and stage 3 has output resistance 50.0 4, What would be the gain vz/vs in dB for the con second stage were reduced by 6 dB? tions of (3) if the voltage gain of the Figure 11.3 (Example 11.1)420. MUCTISTAGE ANIPLIFIERS ‘5, What isthe power gin in dB under the conditions of (3) (meastired between the input vote tothe firtstage andthe load)? = Sige 6. What is tH overall Gurrent gain ii, under the conditions of (3)? Solution. — 3 i. Ar = G6 m¥y(900 wv) = 40 ‘Aa = (1.25 V)/36 mV) = 34.722 Ay = QL V)A1.25 V) = 16.8 vulvy = ApAads = (4034.722)(16.8) = 23,333 ‘Note that the produét of the voltage gains equals the overall voltage gain, which, in this example, can also be'calculated directly: vs/vi = (21 VY(900 nV) = 23,333. 2. Ax (4B) = 20 logyo40 = 32.04 eB : ‘Az (4B), 20 log (34.722) = 30.81 dB ‘As (GB) = 20 logig (16:8) = 24.51 dB vs/v; (BB) = Ay (6B) + Ax (AB) + As (4B) = 87.36 aB Againg2 note thats20 logio (¥s/vi) = 20 logio (21/900 x 10-] = 20 logio'(23,333) = 87: 3, From equation 11. me 4. ‘The (original) voltage Guin with load and source connected is 20 logo (2592.5) = <5" 68.274B"A 6B reduction in the gain of stage 2 therefore results in an overall gain of (68.27 dB) ~ (6 dB) = 62.27 dB. 5. When’a’signal-souree’ resistance of 2000 2 becomes = inserted in series with the input, ¥; i900 RY) = 300 BY ‘The input power is therefore (300.x 10-6 7 1000 = 90 pw ‘The voltage across the 25-0 load is then v= ntti drda( 8g) - = (0 nv 40984.722906.8)( ss) = 228 V ‘The output power developed across the load resistance is therefore v2 _ 2.33)? Ro = 0.217 WGAIN RELATIONS IN MULTISTAGE AMPLIFIERS 421 Finally, 0.217 ) pyar Po) Ap @B) = 10 reso?) =10 veep oo 6. Recall that Ap = A,A,. Using the results calculated in (5), the power gain between the ‘input to the first stage and the load is CeO ' Ap = PolP = sin = 241 X 10° ‘The voltage gain between the input to the first stage and the load is ‘Therefore, Ay 2 241 x10? ade = 2A L AeA H6 It's important to remember thatthe gain equations we have derived are based on the in-circuit values of Ay, da, ..., that is, on the stage gains that result when al other stages are connected. Thus, we have assumed that each value of stage gain takes into account the loading the stage causes on the previous stage and the loading presented to it by the next stage (except we assumed that A, did not include loading by rs and A, did not include loading by 71). If we know the open-circuit (unloaded) voltage gain of each stage and its input and output resistances, we can calculate the overall gain by taking into account the Joading effects of each stage on another, Theoretically, the load presented to a given stage may depend on all ofthe succeeding stages lying to its right, since the input resistance of any one stage depends on its output load resistance, which in turn i the input resistance to ‘the next stage, and so forth. In practice, we can usually ignore this cumulative loading effect of stages beyond the one immediately connected to 2 given stage, or assume thatthe input resistance that represents the load of one stage to a preceding one is given for the condition that all succeeding stages are connected. To illustrate the ideas we have just discussed, Figure 11.4 shows a three-stage ampli- fier for which the individual open-cireuit voltage gains A,y, Ava, and A,s are assumed to be = 31x10 Figure 11.4 A three-stage amplifier. Agy, Ava, and Aca are the open-circuit (unloaded) voltage gains of the respective stages.422 MULTISTAGE AMPLIFIERS ‘known, as well asthe input and cutput resistances of each stage. From the voltage division that occurs at each node in the system, it is apparent that the following relations hold: 1 Ges ol) Pues ole + a) ‘Combining these relations leads to at eteatalat) a” ‘As might be expected, equation 11.7 shows thatthe overall voltage gain of the multistage amplifier is the product of the open-circuit stage gains multiplied by the voltage-division ratios that account for the loading of each stage. Notice that a single voltage-division ratio accounts for the loading between any pair of stages. In other words, itis not correct to compute loading effects twice: once by regarding an input resistance as the load on a previous stage and again by regarding the output resistance of that previous stage as the source resistance for the next stage. [ Example 11.2. ‘The open-circuit (unloaded) voltage gains of three amplifier stages and their input and output resistances are shown in Table 11.1. Ifthe three stages are cascaded and the first is driven by a 10-mV-rms signal source having resistance 12 kA, what is the voltage across a 12-2 load connected at the outout of the third stage? Solution. 20 togioAni = 24 Togiode: = 1.2 Aor = antilog (1.2) = 15.85 Table 11.1 (Example 11.2) SE Sree eee eee ee eee eee eee Steer tee eee UNLOADED VOLTAGE, ipor oureut AMPLIFIER, GAIN RESISTANCE RESISTANCE ‘STAGE a) aD a2) 1 24 10 47 2 20 20 15 3 2 15 0.02 OeGAIN RELATIONS IN MULTISTAGE AMPLIFIERS 423, Similarly, Aca = antilog (1) = 10 4a = antilog (0.6) = 3.98 Then, from equation 11.7, ( 10 ko er srm) ¥s 20 Kn ) of 1.5 ko ) TRA + 2kH) TSO FSM, 29 0+ 12H, L Therefore, v, = 43.53vs = 43.53 (10 mV rms) = 0.4353 V mms. Frequency Response of Cascaded Stages In Chapter 10, we discussed the fact thatthe lower cutoff frequency of a single amplifier stage is influenced by as many as three different break frequencies, having values that depend on various RC components inthe circuit. IF the break frequencies were not close in value, we approximated the actual lower cutoff frequency of the amplifier by assoming it to equal the largest of those break frequencies. Similarly, we assumed the upper cutoff frequency to be the smallest of the break frequencies that affect the high-frequency response. The same reasoning applies to cascaded amplifier stages. If the lower cutoff frequencies of the individual stages are not close in value, the overall lower cutoff fre quency is approximately equal to the largest ofthe stage lower cutoff frequencies. Ifthe ‘upper cutoff frequencies of the individual stages are not close in value, the overall upper cutoff frequency is approximately equal tothe smallest ofthe stage upper cutoff frequen- cies. In practice, a multistage amplifier may have some lower break frequencies that are equal, of close in value, and others that are not. The same is true for upper break fre~ ‘quencies. In these situations, computation of the actual lower and upper cutoff frequencies of a multistage amplifier is a very complex problem. From a practical standpoint, the cutoff frequencies are best determined experimentally or by use of a computer program that computes the overall frequency response. (One of the BASIC programming exercises at the end of this chapter is an example.) For the special cases where all stages of a multistage amplifier have identical lower cutoff frequencies or identical upper cutoff frequencies, the overall cutoff frequencies can be calculated readily: x ea ) = 43.53 fi Suowan = Te ans) Lrroveran = NU" = 1 as Where freveatn = overall lower cutoff frequency of the multistage amplifier — Fetoveraty = Overall upper cutoff frequency of the multistage amplifier n= number of stages having identical lower cutoff frequencies and/or identical upper cutoff frequencies fi = lower cutoff frequency of each stage ‘fa = upper cutoff frequency of each stage424 MULTISTAGE AMPLIFIERS Table 11.2 The lower and upper cutoff frequencies of a multistage amplifier consisting of n stages, each having lower cutoff frequency f; and upper cutoff frequency fz Number of Stages Sitovereny Satoneraty i fi ft 2 1S5ft 0.64; 3 1.96f O.5If2 4 2.30f, 0.43f 5 2.591 0.39%f Table 11.2 shows values of froveaty and froveaty in terms of fi and fe, for n ranging from 1 to 5, Note that when n= 2, fiovent = 1-S5fi and faoveraty = 0.64f2, im agreement with our discussion in Chapter 10 forthe case of two identical break frequencies in a single stage. The table confirms what should be intuitively clear: the greater the number of identical stages, the larger the lower cutoff frequency and the smaller the upper cutoff frequency. In other words, cascading stages with identical frequency-response char- acteristics reduces the overall bandwidth of a multistage amplifier. When n stages having identical frequency response are cascaded, the overall frequency response falls off along asymptotes having slopes 20n dB/decade (6n dB/octave) at frequencies outside the mid- band range. The break frequencies are in all cases equal to the cutoff frequencies of a single stage. ["Bxample 11.3 A multistage audio amplifier is to be constructed using 4 identical stages. ‘What should be the lower and upper cutoff frequencies of each stage if the overall lower and upper cutoff frequencies are to be 20 Hz and 20 kHz, respectively? Solution. From table 11.2, with n = X 10°. Therefore, fi = 202.3 = 8.7 Hz and fy = 20 x 100.43 = 46.5 kHz. This example shows that ‘each stage must have a bandwidth of approximately 46 kHz 10 achieve an overall band- Lwidth of approximately 20 kHz. 11-2 METHODS OF COUPLING ‘The circuitry used to connect the output of one stage of a multistage amplifir to the input Of the next stage is called the coupling method. In previous chapters, we have discussed ‘only one such method: capacitor coupling, also called RC coupling because thé interstage circuitry is cquivalent to a high-pass RC network. In this chapter we will consider two additional coupling methods: direct coupling and transformer coupling. "Recall thai the primary reascit Tor employitig RC Coupling is to block the flow of de current, We have observed that it is often necessary to prevent the flow of de current between the input of an amplifier and its signal source, as well as between the amplificr’s ‘output and its load. Similarly, RC coupling is used to prevent do current from flowing between the output of one amplifier stage and the input of the next stage. The capacitor ‘connected in the path between amplifier stages makes it possible to have a de bias voltage at the output of one stage that is different from the de bias voltage atthe input to the next stage. This {dea is illustrated in Figure 11.5, which shows the ouput of 2 BJT amplifierMETHODS OF COUPLING 425 +Bv 1010 4 Figure 11.5 The capacitor used in the RC coupling method makes it possible to have different bias voltages on the amplifier stages. Note that the (electrolytic) capacitor has 6 V de across it and has its positive lead connected to the more positive bias (9 V). stage connected through a coupling capacitor to the input of another BIT amplifier stage. [Notice that the collector ofthe first stage is at +9 V and that the base ofthe second stage is at +3 Y, The de voltage across the capacitor is therefore 9 — 3 = 6 V, so the capacitor should have a de-working-voltage (DCWV) rating somewhat greater than 6 V. If the 10-nF coupling capacitor is ofthe electrolytic type, it must be connected with its positive ‘terminal to the more positive bias voltage: the 9-V collector voltage in this example. Of course, a coupling capacitor permits the flow of ac signal current between stages, provided the frequency is high enough to keep the capacitive reactance small. The dis- advantage of the RC coupling method is that it affects the low-frequency response of the amplifier; we must sometimes choose between an impractically large capacitor value and ‘an unreasonably large lower cutoff frequency. RC coupling is not used in integrated circuits because itis difficult and uneconomical to fabricate capacitors on a chip. ‘As the name implies, direct coupling isthe coupling method in which the output of one stage is electrically connected directly tothe input of the next stage. In other words, ‘both the de and ac voltages atthe ouput of one stage are identical to those atthe input ofthe next stage. The method is often referred to.as dc, which, inthe context of signal coupling, ‘means both direct coupling and direct current. Clearly, any change in the de voltage atthe ‘output of one stage produces an identical change in dc voltage at the input tothe next stage, 30 a ditect-couped amplifier behaves like a direct-current amplifier. Direct coupling is Used in differential and operational amplifies, which we will study extensively in Chapter 12, and in integrated circuits. We will investigate some examples of direct-coupled dis- crete amplifiers later in the present chapter. ‘Another method of coupling an ac signal from one stage t6 another while maintaining dc isolation between them is through the use ofa transformer. The primary winding ofthe transformer is in the output circuit of one stage and the secondary winding isin the input circuit of the following stage. In this way, the ac signal is passed from one stage to the next without the possibility of de current fowing between the two. The advantages of trans- former coupling include low de power dissipation and the capability for designing a tums ratio that results in maximum power transfer between stages. We will investigate how this is accomplished in an illustrative example using bipolar transistors. The disadvantages of transformer coupling include the bulk and cost of the transformers themselves and their generally poor frequency response characteristics. The transformer induétance and int426 MULTISTAGE AMPUFIERS, winding capacitance tend to reduce the usable bandwidth of these amplifiers. However, they are often used in narrowband applications, such as radio-frequency (ef) amplifi- ers. 11-3 RC-COUPLED BJT AMPLIFIERS [Example 11.4. Figure 11.6 shows two capacitor-coupled, common-emitter amplificr stages. Notice that the ac signal developed at the output of the fist stage (the collector ‘of Qi) is coupled through the 0.85 uF capacitor to the input of the second stage (the base ‘of Q2). Assuming that the transistors are identical and have B = 100, re = 1 MQ, and r= 25 0), find the small signal, midband (1) voltage gain vz/¥s and (2) current gain iyfis. ‘Solution, We will use the common-emitter, small-signal relations that are summarized jn equations 5.44. 1, ‘The input resistance to the frst stage is refstage 1) = Ralf Bre = (1 MO) | (2.5 kM) = 2.5 KO ‘The output resistance of stage 1 (at the collector of Qy) is rofstage 1) = Re1 Hl (re/B) = (3.3 kM) || (1 MOy/100] = 2.48 kO ‘The uncoaded voltage gain of stage 1 is therefore 8K 250 ‘The input resistance to the second stage is rig(stage 2) = Ri || Raf Bore Rea) = (100 kM) |] (10 KM) || 100 ((25 9) + (220 9)) = (9.09 KO) | (24.5 kM) = 6.63 kM ‘The output resistance of stage 2 (at the collector of Qa) is refstage 2) = Rex | ’e/B) = (2.2 KO) I (1 MM/100) = 1.8 KO ‘The unloaded voltage gain of stage 2 is therefore Ayg = —eolstage 2) 18K eRe tr, GD + BDH An = = 99.2 -1.35 +Rv Figure 11.6 (Example 11.4)RC-COUPLED BIT AMPLIFIERS 427 Figure 11.7 (Example 11.4) The two-stage amplifier of Figure 11.6 ‘The two-stage amplifier can now be represented as shown in Figure 11.7. No capac- itors are shown in this figure because we are assuming operation ia the midband frequency range. Using (the two-stage torm of) equation 11.7, we find % 2.540 a 6.63 KO a ¥6 la m+ O30 ml wal BD) + 68 wai) thee 50k. i las ey + ORR] * 365-85 ‘The positive result shows that vz is in phase with vs ‘Notice that an alternative approach to finding the overall voltage gain is to find the voltage gains Ai and Aa with loads connected. Taking this approach, we compute the ac load resistance 7, of each stage: , re(stage 1) = re{stage 1) fl rn(stage 2) = (2.48 KO) | 6.63 KO) = 1.8 kD re(stage 2) = rlstage 2) Re = (18 KM) f $0 KM) = 1.74 KO ‘The voltage gains with these loads connected are then Ko serena pgw ow EHO r+ Ra GSM) + G20) ‘The overall voltage gain is then 7% [eee |e “A lartira 1 Vs rin(stage 1) + rs LOSER + OM), Except for a small round-off error, this approach produces the same result as before. (“T2Y(-T.1) = 365.1 2. To determine the overall current gain, it is helpful to draw the small-signal equivalent circuit of each stage and then trace the flow of ae current through the amplifier. We will use the current-divider rule at each node to determine the jortion of signal current that428 MULTISTAGE AMPLIFIERS is oe fain woo} } <25K0 “o focmnfaove Figure 11.8 (Example 11.4) The small-signal equivalent circuit for the first stage of the amplifier in Figure 11.6. This circuit is used to compute the current igy in terms of is. Continues to flow towards the load. Figure 11.8 shows the small-signal equivalent of the first stage. Applying the curentdivider rule to the input side of tage 1 in Figure 11.8, we obtain IMQ aaway stam 09985 ‘This result shows that essentially all of the source current enters the base of Q; (0.0025is is shunted to ground through Rp). At the output side of stage 1, we have fer Blox = 100in1 = 100(0.9975is) = 99.75i5 To find the portion of Bi that flows into the base of Qs, we must consider all the parallel paths to ground in the interstage circuitry between Q; and Qo. Figure 11.9 ‘shows the equivalent circuit ofthe second stage and the output side of the first stage. ‘Note that r,(stage 1) is the parallel combination of rB and Rey, and this combination is in parallel with the bias resistors Ry and Rz at the input to the second stage. The total equivalent resistance ry shunting the input (base) of Qa is therefore sit = rofstage 1) || Ry || Re = (2.48 kQ) || (100 kA) || (10 kM) = 1.95 kA The current isa into the base of Qs is then found by the current-divider rule: eee ie FB zal a Ain 4 f= ka reGstage 1) =| Bre + Re) = a 2 7 f=) e=g Ra, i Bs MSO OY ome 250 ire 11.9 (Example 11.4) The small-signal equivalent circuit of the output side stage 1 joined to amplifier stage 2. This circuit is used to find iz in terms of is.RC-COUPLED BIT AMPUFIERS 429 Notice that a significant portion of signal current i lost inthe interstage circuitry due to the shunt paths to ground: less than ‘/o of ics reaches the base of Qa. Now, ‘ea = Bisa = 100(7.35is) = 735is ‘The parallel combination of r./8 and Rez shunts R, so one more application of the current-divider rule gives = [ eB) Ree 1 ee (40 KO) [| (2.2 kM) i i te li + (relB} I Rea | ~ | GM + (lO RM) | GIR [72% 18k 7 n = (Ak) = 25.Sdis ‘Therefore, the current gain from source to load is . = 25.54 is ‘This example demonstrates that the current gain of the two-stage BIT amplifier can be found using the relation Rey tu (stage 2) 5 (talc alee oe] 89 ‘where rint, Tana = resistance looking into the input (base) terminal of Qy and Qo, respectively, (nor the stage input resistance). ofstage 1) I Roa total equivalent resistance shunting the input of stage 1 and stage 2, respectively [Example 11.5. Figure 11.10 shows an amplitier consisting of a common-emitter stage driving an emitter-follower stage, ‘The transistors have the following parameter values Qi ra = 15.0, 8) = Qe rea = 25.8, By Row, Rea 80, re 100 Figure 11.10 (Example 11.5)Ne MULTISTAGE AMPLIFIERS Find (1) the midband voltage gain vz/¥s and (2) the approximate value of the lower cutoff frequency, Solution. 1. Noting that the 1.5 kQ emitter resistor in the first stage is bypassed by the 40-aF capacitor, the input resistance to the first stage is a(stage 1) = RVI RZ] Brrey = (150 kA) | (9 kM) ff (UBOKUS A) = 2.48 KD “The output resistance of the first stage, with rar = ©, is refstage 1) = rea [Ror ~ Ror = 47 edt ‘Therefore, the unloaded voltage guin of the first stage is Ra _ x47 KO Ta SD 10 K®Q) | (50.9) ~ 50., so the input resistance 313.3 An = “The ac load on the second stage is r to the second stage is ro(stage 2) = Ri || R2 Ul Baltes + 1) = (68 KA) I (47 KM) f 100125 9) + (60M) = Refezting to equations 5.71, the output resistance of the second stage is Rol 4) (0 EH where Rag = Ri R2 = (68 kM) | (47 kO) = 27.8 kM and rs = r-{stage 1) = 4.7 ko. Ths, 9 kA r{stage 2) = Re rofstage 2) = (10 xo)| [as M+ 81D) 1 67 = (10 kA) | (64.8 2) ~ 64.8.0 The unloaded voltage gain of stage 2 is, Re 10K 4a” eR, BO = cow 9% ‘The two-stage amplifier is equivalent to that shown in Figure 11.11. It is apparent from the figure that 248k is [is H+ O48 mi spa 500 ae GED + GOD. ‘We see that the load voltage is out of phase with the source voltage. As an exercise, repeat the computation using the loaded amplifier gains and verify thatthe overall gain js the same as that found above, x (0.998) [ 2, To find the lower cutoff frequency, we must find the break frequency due to each of the capacitors Cj, Cz, Cs, and Cy in Figure 11.10. From equation 10.16,RC-COUPLED BIT AMPLIFIERS 437 Figure 11.11 (Example 11.5) The equivalent circuit of the two-stage amplifier in Figure 11.10 1 a 1 Babradetage D+ racy — 24S X 10 + 106 X10 ~ From equation 10.42, AC) t IC) = Ree where Ce = C2 = 40 pF and = rsRe ae el (25+) = 5 x 1] SOLOS 19162 <1, 15] ~ 150 Tas, i 1 265.3 Hz fac) = ‘2m 15)(40 x Ki To find the break frequency due to C, we regard r,(stage 1) as source resistance and rig(stage 2) a8 load resistance. Therefore, FCS) = Faipsatage 1) + ralsiage DICs 1 i ca = RETR IOS 59 cIBKOA CIO ~ 35 HF 1 1 Fala DF RIG” ASF SX 10H ~ FB432 j MULTISTAGE AMPLIFIERS 14-46 (ox seat ras swanrdecade 7 1 1 L eo anvdecxce ! 1 1 i 1 eegueney 0) ing 5 OS freee Figure 11.12 (Example 11.3) A sketch of the Bode plot for the gain of the multistage amplifier in Figure 11.10. Note that the asymptotes fall off by an additional 20 d8/decade below each break frequency. ‘The lower cutoff frequency is the largest ofthe calculated break frequencies, which inthis example is cue to the emiter-bypass capacitor in stage 1. Thus, fi ~ fi(C2) = 265.3 He. "An equivalent way of viewing these results is to regard the lower cutoff frequency of stage 1 to be 265.3 Hizand that of stage 2 to be 69.3 Hz. The overall cutoff frequency is then the larger of these two. Figure 11-12 shows a sketch ofthe asymptotic Bode plot ofthe gain magnitude. [Note thatthe gain falls off at a rte that increases by an adaitional 20 dB/decade below cach break frequency found in the example. ‘To find the upper cutoff frequency of a multistage amplifier, we simply apply the ‘general equations devetoped in Chapter 10 (equations 10.30 and 10.31) to each stage. For example, the upper cutoff frequency due to shunt capacitance in the interstage coupling circuitry between stages | and 2 is See ee ee Taresiage D Vratstage MIG where C is the sum of all the interstage shunt capacitances: Cy = Cow(stage 1) + C,(stage 2). Remember to include Miller-effect capacitance, if any, in the quantity Crlstage 2). fC) ay DIRECT-COUPLED BJT AMPLIFIERS In Chapter 6 we discussed the curient-mirroriag ‘méthvafor eliminating coupling capac- itors in integrated circuits. Figure 11.13 shows an example of direct-coupled amplifier ‘stages using conventional bias methods. Notice that the output ofthe first stage (collector ‘of Qi) is connected directly to the input of the second stage (base of Q,). We wil fist analyze the dc bias of the circuit and then consider its ac performance, Notice that the current in cy is the sum of fey and Iga. To simplify the analysis, we will make the reasonable assumption that [gis negligibly small in comparison to fcvariations in B, the base voltage der: (Re Ver — Veo ati2 IE this assumption is not valid in a particular case, then equation 5.95 can be used to determine Vos. Assuming silicon transistors, Vex = Vor = 0.7 (13) ‘Then fey ~ fe; = Vex/Rex. Under our assumption that {go 1s negligible in comparison to Tor, the current in Rey i8 Ley + Jaa ~ der, $0 the quiescent collector-to-ground voltage is Ver = Yoo ~ terRer diag) ‘The quiescent value of Vex is Vert = Ver ~ Ver ans) Notice that Ver = Vaz, 50 Vex = Ver ~ 0.7 ale ‘Then Icz ~ fer = Vea/Rez and the quiescent éollector voliages of stage 2 are Ver = Veo ~ leaRea ana? oe Vers = Veo = Vex—— (L.18) We see that the do analysis is quite straightforward, being nothing more then the appi- cation of bias principles we have already studied. The important point to note is that Ve; = Voz. The ac gain analysis is similarly straightforward ‘The voltage gain ofthe first stage is hoy m tAtage 0H ra(tage 2) 7a * Rex434 MULTISTAGE AMPLIFIERS vice rfstage 1) ~ Rey and r(stage 2) = Balraa + Re). The voltage gin f the second stage is rAstage 2) Tat Rea ra Rea : Finally, the overall gain is the product ofthe stage gains: Artoveraty = Aviva «at.2y If a load resistance R, is ditect-coupled between the output (collector of Qz) and ‘ground, then the ac load resistance on the second stage is 7; = Rca |R and equation 11.20 becomes Anam «1.20 = Real Re a Tat Re [tis important to realize that direct-coupling an output load resistance changes the de value (of Vea and Vega: To demonstrate this fact, let us regard the transistor as a constant-current source, as shown in Figure 11.14(b). We can then apply the superposition principle to find the de voltage Vj, (= Vc) due to each source, in the circuit, as shown in Figures 11.14(c) ‘and (@). Combining the contributions of each source leads to Re | 1 ‘Rei | (11.22) +H : (2) Output sage with dre. () The de equivalent, connecied 88 Ry ire of tel Fe Be Be Mar Re we : ve rf trea) © rll Fr r+ Fe} (© The de voliage sero 1) The de voltage due Yee seroae Ry du 10 fc —By superposition, a tp ee & fe fe . cn (< + aie = “Ge + x - & + 7) ae Figure 11.14 Computing the dc voltage across a direct-connected load Ry, using the principle of superposition.DIRECT-COUPLED arr AMPLIFIERS 435 R, Me Vom & 7 x) Wee ~ teRe) a1.23), Equation 11.23 simply shows that the collector voltage equals’ its unloaded valve (Wee ~ IcRc) divided down by the voltage divider formed by Rr, and Re. Since Vce = Vo ~ Ves its clear that too small a value of Ry can reduce Voto the point that Ver approaches 0, severely limiting the voltage swing. [Example 11.6. The silicon transistors in Figure 11.15 have the following parameters: Qs: Br = 100, rr = 6.0, ry = Ge Ba = 60, ra = 100, ra ~ 1. Find the quiescent values of Vce1, lca, Er Vex, and Veen. 2, Find the voltage gain v./vin. 3, Repeat (1) and (2) if a 10-kO load is direct-coupled between the collector of Qs and ground. Solution. 1, The de input resistance looking directly into the base of Qy is approximately Rat ~ Bikey = 100 (75) = 7.5K ‘Since this resistance is not large compared tothe 11 KO resistor in the voltage-divider network across the base, we must take into account the loading effect it causes on the voltage divider. Therefore, from equation 5.95, - Geeks.) _ (11 KO) 1.07.5 ] eH Ve \R Ral Ra) ~ [Woo + aM TSH] OY) = 12V ‘Then Ver = Var ~ 0.7 = 1.02 ~ 0.7 = 0.32 V Tey ~ dex = Vey/Res = (0.32 VCS Q) = 4.26 mA Figure 11.15 (Example 11.6)436 MULTISTAGE AMPLIIERS, Neglecting the current fp, the collector-to-ground voltage, Vr, is therefore Ver * Veo = tere, = 24 ~ (4.26 mA) (4.7 kM) = 3.95 V ‘Thus, iM oS? Veg = Ver = Vai = 3.95 ~0.32 = 3.63 V since Vey = Von, we have Vea * Ver ~ 0.7 = 3.95 - 0.7 = 3.25 V ‘Therefore, 7 fa Ins = $B 325M = 3.25mA Since there is no Joad resistor connected to Qa, Ir = Ica = 3.25 mA, i: fcx/B2 = (3.25 mAY'6O = 0.054 mA, which is indeed negligibly mall in comparison to Jey = 4.26 mA. ‘The de collectorto-around voltage, Vez, and the dc collector-to-emitter voltage, Veen are Vea = Veo ~ leaRez = 24'— G.25 mA)3.3 kM) = Vera = Veo — Vex = 13.3 ~ 3.25 = 10.05 V 3.3V Ay, ~ ~Revi BalRen + ra). G7 KO) || 601(1 kD) +10) _ _ 53g i Ra + re (7150+ 6M) : wg ERG 33K Aa Rot ra” TRO) + OD Avonraty = Andra = (-538X-3.3) = 1715 3.3 3. The quiescent value of Vez is unaffected by a load resistor connector tothe vollector of Qo. 80 Vee, = 3.63 V, a8 in (1). Similarly, fc isthe same as in (1): 3.25 mA. From equation 11.23, eee 10ko = ae Va= Yoo (omtStom Gs ale .25 mAyG.3 kN] = 10 V | Therefore, Vora = Vea — Vex = 10 ~ 3.25 = 6.75 Y. Now, s0 Ir = Tea +f, = 3.25 mA) + (1 mA) = 4.25 mA, ~The voltage gain of stage 1 i still ~53:8: The-volage gain of stage 2 is now Roa LR _ =G-3 KM) (10 KD) _ _, gg Ratta (dk) +000) ‘Therefore, the. overall voltage gain with the 10 kO Toad connected is Avoreaiy = LL (-53.8(-2.48) = 133.4. Aa~DIRECT-COUPLED B/T AMPLIFIERS — 437 Figure 11.16 Direct-coupling using complementary transistors. Note that the PNP transistor is biased by connecting the positive supply voltage to the emitter ‘ side, (All voltages shown are de values with respect to ground.) Recall thatthe collector voltage of an NPN transistor must always be more positive than its base voltage. When transistors are direct-connected, the collector voltage of one stage equals the base voltage of the next stage. Therefore, the collector voltage of any NPN ‘stage must be greater than the collector voltage of a preceding NPN stage. As the number of direct-connected transistors increases, the collector voltages become progressively larger. In practice, relatively few direct-coupled stages can be cascaded before the col- lector voltage must be made impractically large, exceeding the power supply voltage, To ‘overcome this problem, alternating transistor types (NPN, PNP) can be used in direct- coupled cascades. In this application, the transistors are said to be complementary, and Figure 11.16 shows a two-stage example. The arrangement works well because the base of PNP transistor must be more positive than its collector—just the opposite to the condi- tion for an NPN transistor. Of particular interest in Figure 11.16 is the biasing ofthe PNP transistor. Note that the positive supply voltage is connected to the emitter side of the transistor and the collector side is grounded, Assuming a silicon transistor, the emiter-to-ground voltage of the PNP transistor is about 0.7 V more positive than its base-to-ground voltage (For forward bias of the base-emitter junction), Thus, Vez = 19.4 + 0,7 = 20.1 V. The voltage drop across the emitter resistor is therefore Veo ~ Vex = 24 - 20.1 = 3.9V and io Teg = (3.9 VI( KD) = 3.9 mA ™ Iea Clearly, Ver = leaRea = (3.9 mA)(2.7 kK) = 10.5 V The Darlington Pair - 7 ‘When the collectors of two BJT are ted together and the emitter of one is direct-coupled to the base of the other, as shown in Figure 11.17, we obtain an important and highly useful configuration called a Darlington pair. This combination is used in amplifier cir- cuits as if it were a single transistor having the base, collector, and: emitter terminals labeled B, C, and E in the figure, We will analyze the Darlington peit to discover the438 MULTISTAGE AMPLIFIERS Figure 11.17 The Darlington pair is used as a single transistor having the ‘> collector, base avd emt terminals ined , B, and E. effective beta (Bor) of the single transistor it represents, as well as some ofits small-signal characteristics. ‘Let Bi and 2 be the de P-values of Qs and Qa, respectively. Then, by definition, Toy = Biloi and Tey = (Bi + Ds But fer = Ina, 80 ea = Balen = BBs + Wan Now, To = lex + Tea = Balas + Bali + Dla = (BiB2 + (Bi + Bada fs, we have Ic = [BiB + (Bi + Balls, oF Bor = dolls = BiB2 + Bi + Bz (1.24) ‘Equation 11.24 shows thatthe effective B of the Darlington par is the product plus the sum ‘of the B's of the individual transistors. It is usually true that BiB2 >> Bi + Ba, 0 Bor = 8182 + Bi + Ba ~ Biba (11.25) Darlington pairs are often fabricated on a single chip to achieve matched Qi and Q2 characteristics. When B = Ba = B, we have an effective B of Bor = B* + 28 ~ B (11.26) For example, if 1 = 82 = 100, then Bpp = 10,000 + 200 ~ 10,000. We see that the Darlington pair can be regarded as a “'super-" transistor, and therefore enjoys all the ‘advantages that high-B transistors have. For example, the de resistance looking into the base-(of Qu) is the very large value Pope, where Reis the resistance between the emitter (of Qa) and ground. ‘While the foregoing analysis was performed for de currents and de B-values, an ‘dgotical small-signal analysis shows thatthe small-signal value of Bis the product plus the sum ofthe small-signal values of f and Bz. Hereafter we will make the usual assump- tion that the dc and small-signal values of B are approximately equal and will not distin- ‘uish between the two. Since IpDIRECT-COUPLED 8)T AMPLIFIERS 439° ‘We wish now to determine the effective small-signal input resistance from B to E, ‘igor, and the emitter resistance, rypp,, of the composite transistor. Recall the general relationship (equation 5.22) rem Fe~ SO at room temperature (27 Since dea * Ira, we have (1.28) ‘Referring to Figure 11.17, note that fo = de + lca * Ica since lez >> Ie1. Thus, (11.28) ‘may also be written tea 0.028 (11.29), Te Recall that the ac resistance looking into the base of Qa is Fon tse * Baker (1.30) Now ra x 228 sy tes ‘Since fez ~ Balm = Bole, we have lea kn ~ 1.32) ty ~ 1.32) ‘Substituting (11.32) into (11.31) gives ra ™ Ba (228) = Bra (11.33) ‘The total effective resistance looking into the base of Q, (across the composite BE terminals), i., the effective small-signal input resistance of the Darlington pair, is Teco) = Bulret + Yin cbana) * By (Fer + Bata) 1.34) ‘Substituting from equation 11.33, we have roan) ~ Bu\Bara + Bata) = Bibra a13s) Since Boe ~ BiB2, the effective emiter resistance, repr is rep = Tit02) « BrBarea He toe) mA we AP = On 1.36 [Example 11.7. A Darlington pair is biased so thatthe total collector current is 2 mA. 10 and B2 = 100, find the room-temperature values of (1) Be, (2) racopy, and (3) 1. Bor = Bifs + Bi + Br = (110)(100) + 110 + 100 = 11,210440 MULTISTAGE AMPLIFIERS 2, From equation 11.29, 0.026 ra gs 3a From equation 11.35, rior) ™ 2(110)(100)13 = 286 k2, 3. From equation 11.36, rape) ~ 2(13) = 26 9. ‘This cxample shows that the Darlington pair can be used to obtain a significant increase in base-to-emitter input resistance, compared to that obtainable from a con- Lventional BIT: 286 k0. versus 1.3 kO. ‘The Darlington pair is most often used in an emitter-follower configuration because of the excellent buffering it provides between a high-impedance source and a low impedance load. With an ac load resistance rz connected to the emitter, the total input resistance to the follower is Pin = Togoe) + Boer 37 ‘When operated as an emitter folower, the current gain from the base of Q, to the emitter of Quis A: = inaligy. Since ig1 = dia, we have 2 (2) B= gi + nm + n~ pit 1.38 ‘The next example illustrates an extreme case of the need for buffering, where the source resistance is 5 kO and the load resistance is 10 0. ["Bxample 11.8, Figure 11.18 shows a common-emitter stage driving a Darlington pair connected as an emitter follower. The B- values forthe silicon transistors are B = 200, Bo = 100, and Bs = 100. 1. Find rs, 2. Find v/v if the Daslington pair is removed and the 10-0 load is capacitor-coupled to the collector of Q). Figure 11.18 (Example 11.8)DIRECT-COUPLED B/T AMPLIFIERS 4417 Solution. ~(B v= 10K is , it a fe + a = la oF GOED] SY 26¥ Ver = Vay ~ 0.7 # 2.6 = 0.72 1.9V fey = Tey = PEt = IN = 19a 0.026 _ 0.026 a Tex 15 mA ~ 13.70 rein stage 1) = Ri Rel Bares = (10 kM) | (47 kM) fj 200(13.7 0) = 2.1 KO Notice that the collector of Qu is direct-coupled to the base of Qe in the Darlington pair, so Veo = Ver = Veo — ter Rer = 15 V ~ (1.9 mA) 3.3 kM) = 8.7 ‘The de emitter voltage of Qs is about 1.4 V less than the base voltage of Qa, since there are tivo forward-biased base-emitter junctions between those two points: Noting that Q, and Qz in our previous analysis of the Darlington pair are now desig- nated Q and Qs, we have, from equation 11.28, 0.026 _ 0.026 rq 2088 = 360 Fama From-enyation 11.36, repr) ~ 28.6 2) = 7.2.9 From equation 11.26, Bor = (100)? + 200 = 10,200 From equation 11.35, TigaoP) ™ 2(100)(100)(3.6) = 72 kD From equation 11.37, the total resistance looking into the Darlington pair, with load ‘connected, is Pig = (72 KM) + (10,200) {(1 kA) | (10. 9)] ~ 174 KO ‘This value of input resistance is so large in comparison to the 3.3 kM collector resis- tance of Q that virtually no loading ovcurs. Thus, ra _ 23.30 7 Ane OB: ta “The voltage gain ofthe emitter-follower stage is (from equation 5.59) tn, 1 ka) § (10 9) taal TIEN + CxO TCO ~ Tape) +1442 MULTISTAGE AMPLIFIERS 1a et lca mel lg i sees Ys ls + rog(stage wl Avon 21k ~ feat ag ams =a 2. With the 10-0 load connected to the collector of Qs, the ac load on Qh is res 1110 0) = 10.0. Therefore, 0 An = =-0.3 ‘The overall gain is then % 21 kO. eeesetiae ee [ae ag] co = -022 3k) Without the buffering provided by the Darlington pair, the output voltage tums out to be less than half the level of the input signal, i.e., we no longer have a voltage amplifier, We see that the Darlington pair increases the voltage gain by a factor of 41,3/0.22 = 187.7, €ascode Amplifier Another important example of direct-coupled transistor i the so-called cascode amplifier (a name derived from vacuura-tube days), in which a common-emitter transistor drives @ Common-base transistor. A simple example of a cascode amplifier is shown in Figure 11.19. Note that Q; is a common-emitter stage that uses Rp, for “fixed” bias. Since Capacitor Cp grounds the base of Q2 to ac signals, Qz is the common-base stage. It serves as the load on the collector of Qy, Recall thatthe input to a common-base stage is at its ‘emitter and the output is taken at its collector. Thus Qy is direct-coupled to the input of Qs and the outpat ofthe cascode amplifier isa the collector of Qs. Resistors R; and Rs form & voltage-divider bias circuit for Qs. ‘The principal advantage of the cascode arrangement is that it has a small input capac- itance, an important consideration in high-frequency amplifiers. The input capacitance is Yee Figure 11.19 An example of a cascode amplifier. Q, is a common-emitter stage that is direct-coupled to the common-base stage formed by Qz.DIRECT-COUPLED BIT AMPLIFIERS 443 small because the voltage gain of Q, is small (near unity), which means that the Miller ‘Sapacitance is minimized. Most ofthe voltage gain is achieved in the common-base stage. ‘The voltage gain of Q, is small because the effective load resistance in its collector ciretit is the small input resistance of the common-base stage. Caleulation of the bias currents and voitages is straightforward: Jor = Voo — Vee (11.39) ta ex = lea * Ica = Bilor (a1.40 R Vea = (e B ee a4 Vou = Veo = Vez ~ Vae (re) Vou = Vee ~leaRee (1.43) Voss = Vea ~ Vex (i.a4y Qr, like any other common-emitter stage, can also be biased using the voltage-divider ‘method and an emitter resistor. Figure 11.20 shows a small signal equivalent circuit of the cascode amplifier. The collector, base, and emitter terminals of each transistor are labeled in the diagram (Cl, BI, ete.) Referring to the equivalent circuit, we see that refstage 1) = Rox I Bret a1.45) Note that the input resistance of Qs isthe small emitter resistance rip of the common-base stage. The parallel combination of rey/B1 and rez form the ac load on the collector of Q,, Since rai/Bi >> rea, Tet = es B1) I tea = Pea (1.46) ‘Thus, An ~-1 aan Ta Ta Equation 11.47 states that the voltage gain of Qy is approximately unity, which follows from the fact that za ~ Tey, making rea ~ re. The ac load on the collector of Qs is seen 0 be ra = Fea Real| Re = Real Re (11.48) a co, Bop Qt fore a BE ng GD obtak ak i t & Figure 11.20 Smal-signal equivalent circuit of a cascode amplifier434 Murmistace AMPuiFieRs igure 11.21 (Example 11.9) ‘Therefore, the voltage gain of the second stage is Ag ~ fw Rol 1.49) Ta Ta The overall voltage gein of the cascode is thus Ay = Anda ™ ~Aa (11.50) Equation 11.50 shows that the common-base stage provides most ofthe voltage gain. The current gain of the cascode amplifier, not including current division atthe input or output, is approxiinately Ay™ Bice * Br since oy ~ 1 ans ‘The output resistance of the amplifier is rastage) = ral] Rex ™ Rea (11.52) TBsanple 11, ‘The siicon wana in Figute 11.21 have be following parameter Qt: Br = 100, rar * ©, Che = 4 DE, Che = 10 PF Qi ag 1 rae Find approximate values for 1, The de currents and voltages Fei Lea.» Vers and Veas 2,_the small-signal voltage gain vz/v5} and 3. the break frequency /A(C,) due to shunt capacitance at the input of Q1. Solution. 1, The base-to-ground divider there: voltage atthe input stage (Qu) is determined by the voltage- 10k Van = la m+ GE Jo V)=28VDIRECT-COUPLED ByT AMPLIFIERS 445. Ver = Ver ~ 0.7 = 2.8 ~ 04 =21V fey toy = Ht = BEM oma = Nea lex ‘The base-to-ground bias voltage of Q» is determined by its voltage divider: naa [roma aon)? Stee Therefore, Ver = Vez = Veo — 0.7 = 6 —0.7=5.3V Veo foo ~ TeaReq = 12 — (2.1 mA)(2 kM) = 7.8 V 2. Since fer ~ Jen. 0.026 026 Tes 2..mA rofstage 1) = (33 kM) I (10 kM) J 100(12.4 9) = 1.07 KO =o = 12. ARM I GOK _ 144 4 ta 12.402 ” [ rofstage 1) Fe ¥ rolstage D. 107 Ka * lao) + 07 a] 49 Sect 3. ‘The Miller eapacitance at the input to Q, is determined by the voltage gain of stage 1 alone: = 1249 ta Tam idee Ca = Coch = An) = (4 pFQ) = 8 pF ‘The total input capacitance is therefore Ca = Cap + Coo = (8 pF) + (10 pF) = 18 pF Then 1 (0 = ae HCD = sates ralstags DI Ca ~ BaTTOT COT 1OHHTE TO) 96.7 Mite ‘Wesse that the Break frequency du td input caatitaiceW quite high. While there may bbe break frequencies elsewhere in the circuit that are smaller than 96.7 MHz (including the fa value of Qu), the cascode amplifier effectively eliminates the most troublesome L source of high-frequency loss—the input Miller capacitance. 11-5 TRANSISTOR ARRAYS ‘Multiple wansistors sharing a common substrate are available in integrated-circuit pack- ages called transistor arrays. Compared to medium- and large-scale integrated circuits446 MULTISTAGE AMPLIFIERS CA3018, CA3018A General-Purpose Transistor Arrays Two Isolated Transistors and 1 Dariington-Connected Transistor Pair For Lon-Power Applications at Frequencies from DC Through the VHF Range eepenary Feature ‘Apiietions 1 Hatched monote gana 1 General vein ipa! poceaing Durporeranars Syutame In OC tun VE rae sf mtcned = 1 Goat designed oan vue Veumutoned 3 2 nV CAIDA elites Soerniontom oc to rows" arpa sid 1 Soar tom Oc 120 ae mers eee 3 Wn opera crt ange 1+ See R04 Appleton Note, 3 CAavied portance crores." SCAM Saxe Rpphalon othe texeonio emg eat fone CA GAN pte Sea 1 Low oie igure 3.2 38 ypcal et ‘Translator ArayTottaggatod er topleatons. (© Ful itary tamparature range cx- pacity 25 to 125°C) ‘Tha CASON8 and CAZOTEA consist of four genera purpo¥e allcon n-p-n" Wansistors on A common menotPle tetra Tagot he ou taraaar ra conraca nthe Duinton {eetiguration. The substrate a connected Yo & seperate rina or maxlnum foxy. i ‘The tansiatora cf the CAZO18 and the CASOI8A are wet ‘ultad 10 4 wide varity of appcatne in low-power aye ams inte OC tough VHE range. They may be used as 0 XO OS & 10H ~ 262 He LSince fi(C2) ~ f(Cs) = 100 Hz, the lower cutoff frequency is f, ~ 1.55(100) = 155 Hz. Direct-Coupled FET Amplifiers Direct-coupled field-effect transistors are widely used in linear integrated circuits. The nest example illstates a 3-tage, drec-couped amplifier that uses complementary JFETs (N channel and P channel), similar in. concept to the direct-coupled, complementary BIT amplifier discussed earlier. Note in particular how the P-channel ‘stage (Q2) is biased. T"Bsample 11.12, ‘The SFETs in Figure 11.25 all have pge= 8 mA and |Vol = 2 V. Find the de values of the drain-to-ground voltage Vp, the source-to-ground voltage Vs, and the drin-o-source voltage, Vos, of each transistor Solution, Note that Qu and Qs are both common-source stages and Qs is a source fol- lower. In the figure, the FETS are drawn with offset gate symbols to help clarify the configurations. (Recall that the gate is offset towards the source.) u Z MCS) rete Faas BF RIC450 _ MULTISTAGE AMPLIFIERS, Figure 11.25 (Example 11.12) ‘The gate-to-ground voltage of Q: is determined by the voltage divider across the input: 1Mo Vou = la May + iS sas) pee From equation 7.13, Vest = Vou ~ Zoi = Uni 4.7 KO) (asa) © Vest ‘The square-law equation for Qs is In = @ aa(t - 1.35) Using the methods described in Chapter 7, we can solve equations 11.54 and 11.55 simultaneously for Jp, and Vast, t0 find Joy = 1.92mA and Vosi = ~1.02V Thea Voy = ToiRot = (1.92 mAYG.7 KO) = 9.02 V : and = Vor = Voo ~ fotos * 20 =. (1.92 mAY(4.1 KA) ‘Therefore, 5 Yost = Vor ~ Voy = 12.1 ~ 9.02 = 3.1 Note that |Vpsi] = 3.1 > IVal ~ [Yost region. ‘Quis e P-channel JFET biesed with its source side connected to the positive supply voltage and its drain side grounded. Writing Kirchhoff’s voltage law from Vpp, through 0.98 V, so Q, is properly biased in its pinch-offMULTISTAGE FET AMPLIFIERS 451 ‘Rez, across the gate-to-source junction, and from the gate of Q to ground, we have Voo ~ Ino: + Voss ~ Vea = 0 1.56) ‘Noting that Veg = Voi = 12.1 V, ‘equation 11.56 becomes 20 = Ipx(4.7 10°) + Vos - 12.1 = 0 Vos. = —7.9 + (4.7 X 10 Yip2 (11.57) ‘The square-law equation for the P-channel JFET is Vose\? tor = 8 ma(t -= } (1.58) Solving (11.57) and (11.58) simultaneously, gives In =19mA and Vase = 1V ‘Therefore, ¥s2 = Voo ~ (p2\4.7 kM) = 20 — (1.9 mA\4.7 kM) = LAV and Vor = IooRo2 = (1.9 mAY(4.1 kM) = 7.8 V Then Vos: = Vor ~ Vq = 7.8 - 11.1 = -3.3.V As an exercise, verify that Qz is also in its pinch-off region. Writing Kirchhotf's voltage law around the gate-to-source loop of Qs, we find Vos = Yor = Vass + InaRss, or 7.8 = Voss + fosl4.7 KO) a1.s9 Solving (11.59) simultaneously with los = 8 may(t - “sy (11.60) ives los = 1.88mA and Vosy = “1V Thus Vex = losBs = (1.88 mAYA,7 KO) = 8.8 V and Yos = Yoo = 20 Lithen Yass = Vos — Vn = 20 = 8.8= 11.2 [Example 11.13, Find the voltage gain v/vs ofthe multistage amplifier shown in Figure 1 : Solution. "To find the voltage gain of each stage, we must find the transconductance gy, of each JFET. Recall from equation 8.3 that 2Ipss_ [To + f= TE Views ann452 [MULTISTAGE AMPLIFIERS ‘Substituting Ip, = 1.92 A, Ipg = 1.9 mA, and Ips = 1.88 mA (from Example 11-12) into (11.61) B¥€S Gi = Ba ~ na = 3.9 THS. Assuming that the rg of each JFET is very large, the ac load resistance at the drain terminal of each of Qi and Qa is simply Ro = 4.1 KA, Therefore, the in-circuit voltage gain of each stage is An = An = ~8eRp = ~(3.9 X 10-41 X 10) = 16 From equation 8.21, the voltage gain of the source follower (Qs) is, neglecting ray = —SmalRss Rd 3.9 X 107°14.7 kM) (10 KOT = = 329X107 TKM TOK g hoo = eR ERS 7 TF 39K TO 1G.T HD) FO KA] “Thus, the overall voltage gain is ve, Tn(stage 1) za 2.5 MO) | (MQ) Wen et tage 5 4249 = GORD = EMO) | MO * L (~16)(—16)(0.93) = 220 A Bifet Amplifier Biferis a coined term meaning a combination of bipolar and FET, and a bifet amplifir is cone thet contains both types of transistors. These arnplifiers are designed to exploit the nost desirable characteristics of each device, such as the very large input impedance ofthe FET and the large voltage gain of the BJT. A good example is the cascode amplifier, the bifet version of which is shown in Figure 11.26. Note that the input stage, Qu, i8 8 JFET connected in a common-source configuration and the second stage is a BJT connected as a common-base amplifier. “The ac equivalent circuit of the bifet cascode is shown in Figure 11.27. The voltage gain of the first stage is An = ~Bnlrall Ro bred) (11.62) Since the common-base input resistance ris quite small, rgl| Ro I 7 Fe and An Bue (1.63) While A,y is usually small (less than 1), the large inpat resistance and small Miller capac- itance of the IFET stage results in bettershigh-frequency response than that found in the Figure 11.26 A bifet cascode amplifierTRANSFORMER COUPLING 453 Figure 11.27 The ac equivalent circuit of the bifet cascode amplifier ‘shown in Figure 11.25 BIT version. As in the BIT cascode, the voltage gain of the amplifier is achieved in the common-base stage: red RoE Ri te Since a BJT amplifier is generally capable of producing more voltage gain than its FET ‘counterpart, we see that the bifet amplifier uses the best features of both kinds of devices. aR (11.64) 11-7 TRANSFORMER COUPLING [Besides blocking de, an important advantage of using a transformer for interstage coupling is that the tums ratio can be designed to achieve impedance matching and therefore (0 maximize power transfer between stages. Recall that the turns ratio of a transformer is defined by tums ratio = Me = Ye (1.65) ny where Np, N, = number of tums in the primary and secondary windings, respectively Yp» ¥s = primary and secondary voltages Figure 11.28 shows a transformer whose primary is driven by a signal source vy hhaving resistance r; and whose secondary has load resistance 7, connected across it, loa a) Figure 11.28 A transformer whose primary winding is driven by the signal source v; and whose secondary winding has load r, connected across it454 [MULTISTAGE AMPLIFIERS Assuming an ideal transformer (zero winding resistance and no power loss), itis easy t0 show that the resistance 7, looking into the primary winding is N,\2 ram (Me) ne (2 ou To achieve maximum power transfer from the source tothe loadin Figure 11.28, itis necessary (by the maximum power transfer theorem) that the resistance 7, seen by the signal source be equal to the source resistance r1. Thus, ftom equation 11.66, we require 2 (2) re aLen ‘Solving (11.67) for Np/N,, we find the turns ratio necessary to achieve maximum power transfer: Mee tt MN, Vn {In multistage transistor amplifiers, the signal source driving the primary winding is often a common-emitter stage having a large output resistance, and the load resistance may be the much smaller value equal to the input resistance of the next stage. In that case, the ratio ir is greater than 1 and therefore, by equation 11.68, the turns ratio Ny/N, is greater than 1. As a consequence, the coupling transformer is typically a step-down transformer, ‘meaning the secondary voltage is less than the primary voltage. Commercially available transformers are often specified in terms of their impedance ratios rather than their tums ratios. In these cases, the tums ratio can be determined using equation 11.68, i.e., by taking the square root of the specified impedance ratio. For example, ifthe specifications on a transformer state that it has primary impedance 16 kf and secondary impedance 16 0. (typical values for matching a transistor output stage to a speaker), then wa ee i610 _ Ne VZ7 Vas 7 3h [Example 11.14, Figure 11.29 shows a transformer used to match a 100-K0) source to a 250-1 load. 1. What should be the tums ratio of the transformer? 2. With the matching transformer in place, what is the rms voltage across the load’ 3. What is the maximum power that can be delivered to the load? (11.68) Ne n= 1 ko avimS) I; Figure 11.29 (Example 11.14) Vz = 3800TRANSFORMER COUPLING 455 Solution, 1, From equation 11.68, N, fry 100 X10 ef 7 io Vi VEE = ‘Thus the primary winding should have 20 times as ‘many tums as the secondary winding, 2, From equation 11.66, Tin = (Np/N,)*r, = (20)7(250) = 100k. We see thatthe resistance looking into the primary winding is 100 kO, as it should be When load and source are matched by the transformer, Since the source resistance and ‘rm form a voltage divider across the 8-V-rms signal source, the voltage across the primary winding is one-half the signal voltage: Tin =o 100 kQ. fae & ee [one + oom )® eee ‘From equation 11.65, = Aa 1 w= (giao ()e= 02 vm We see that the transformer steps the primary voltage down by a factor of 20. (The ‘current is stepped up by a factor of 20.) 3. Maximum power transfer occurs when the source is matched to the load, and with the matching transformer in place, we have 2 2? =P, = = ON Prax = Py = he 350 0.16 mW (When the source and load are matched, the same amount of ‘power is dissipated in the LL source as is delivered to the load; verify that fact inthis example.) Figure 11.30(a) shows a two-stage transformer-coupled amplifier. Note that ther is ‘ho resistor in the collector circuit of either transistor, so the primary of each transformer is Ativen from a source (a collector) having relatively jarge resistance, The secondary wind. ing of the interstage transformer is conriected directly to the base of Q,. The 4.7-K0) base biasing resistor is bypassed with a capacitor, so all of the ac voltage developed in the Secondary winding appears from the base of Q3 to ground. Note that both sides of the 15-KO1 resistor are at ac ground. With the arrangement shown, the Q> bias resistors do not reduce the ac input resistance to the second stage, and the transformer does not short the d= bins current to ground. The 1.25-K02 load is transformer-coupled to the output of Q3. Note thatthe load is shown completely isolated from the rest ofthe cireuit, in the sense that it does not share a common ground reference with Q, and Qz (although it could, if desired). This is another advantage of transformer coupling: individual amplifier stages and loads can be isolated from each other when desired or necessary. In fact, isolation transformers ‘having 1;1 turns ratios are sometimes used specifically for that purpose.456. MULTISTAGE AMPLIFIERS anv (a) Note thatthe 4.740 base lasing elitr of O3 is ‘yas anda the L260 oe late rm tere a ta (0) The a quae cat of (0 Figure 11.30 A two-stage, transformer-coupled amplifier Figure 11.30(b) shows the ac equivalent circuit of the transformer-coupled amplifier. ‘The next example demonstrates that the transformer turns ratios were chosen to achieve impedance matching. [Example 11.15. ‘The transistors in Figure 11.30 have By = 105,'r91 = 20 kf, Ba = 89, and rez = 20 kf. Find the midband voltage gain vz/vs. Solution. Qy and Q, are biased identically, so the following computations for determin apply to both: Ye 47 ko Jee V) = 2.86 V * [G7 + ISK, Ve = Vp - 0.7 = 2.16 tp eo BIO Fo Re 7500 ao ote nooo Te 288mA ‘The ac input resistance at the base of Q2 is rina ~ Bara = (89)(9) = 801 11. Therefore, by equation 11.66, the resistance looking into the primary of transformer Ty is = 2.88 mA __ 9aTRANSFORMER COUPLING 457 ‘aaminan) = My/ NPR, 1 oy 11> Fol Yetrmens Figure 11.31 (Example 11.15) The ac resistance seen at the collector terminalis the parallel combination of Fo and Fingrinan 2 Paprinary of) ®) Tua = S801) ~ 20 kA. Since ra) = 20 KO, we'see that the transformer matches the output of Q, to the input of ” Figure 11.31 shows the ac equivalent circuit of a BIT collector output witha primary ‘winding connected across it. Itis apparent thatthe ac load resistance seen at the collectoris the parallel combination of the transistor’s output resistance r, and the effective resistance Tooking into the primary winding, Piaprinary- ‘The ac load resistance at the collector of Qy is then 111 To Minin apt = (20 KM) || 20 KM) = 10 KO ‘Thus, the voltage gain from base to collector of Q: is ~ An (base-cotecir) ‘When we compute the overall gain of the amplifier, we will take into account the fact that T; steps the voltage down by a factor of N,/Np = 1/5, between the collector of Qy and the base of Q2. ‘The resistance looking into the primary of Ta is Fanrimary of 7) = (& Ry = 41.25 kM) = 20k We see that transformer T; matches the output of Qs to the load. The ac load resistance at the collector of Qs is aa = Fea Pitino of ty = (20 kM) 20 KO) = 10 kA and the voltage gain of Qs is Avzibase-coecton) = ‘Taking into account the voltage division atthe input of Qy and the step-down ratios of the transformers, we find the overall voltage gain to be458 MULTISTAGE AMPLIFIERS: ¥%s Eee toa s)oaeel@) where rig(stage 1) = (4.7 kM) || (15 kM) || (105)(9 9) = 748 2. Then ze (gig) men (2)caunn 3) ‘The sign of the voltage gain, indicating the phase of the output with respect to the input, Lumay be changed by the coupling transformers, depending on how each is wound. 37,849 [Example 11.16. A BASIC Program for Computing Power Transfer versus Trans- former Turns Ratio, Write a BASIC program that prompts a user to enter source resis- tance, load resistance, and rms source voltage, and then computes the transformer tums ratio necessary to achieve maximum power transfer to the load. The program should also print table showing the power dissipated inthe source and the power delivered tothe load for 19 different tums ratios, varying from one-tenth that of the optimum to 10 times that of the optimum, in the sequence 0.1a, 0.24... ,0.9a, a, 2a, 3a, ... ,9a, 10a, where ais the optimum tars ratio. Solution. ‘The solution program prompts the user to enter source resistance (R), load resistance (R,), and source voltage (V). It then computes and prints the optimum turns ratio: A = ‘VRy/R (from equation 11.68). As shown in Figure 11.32, the voltage across Ris cOmputed using the voltage-divider rule: where N is an arbitrary wms ratio. The voltage across the primary of the transformer is therefore V — Vi, and the secondary voltage is the primary voltage divided by the tums ratio: =u The power dissipated in Ry is Py = Vs°/Ri and the power dissipated in the load is Py = V2IR. a weet RR | ¥ Figure 11.32 (Example 11.16)TRANSFORMER COUPLING 459 ‘The foregoing computations are performed in two FOR TO, NEXT loops. The first loop varies the turns ratio from N = 0.LA to N = A, as I ranges from 1 to 10. The second loop varies the tums ratio from N = 2A to N= 10A, as I ranges from 2 t0 10. 10 PALWT “ENTER SOURCE RESISTANCE Di OHMS." Uieveayintese sen) Let vena [220 PRINT wjVIeVI/RV2*V2/R2 ‘Bo wexr 340 END Following this paragraph are the-results of a program run for the case R, = 25 kM, Ry = 1k, and V = 10 V. We see that the power delivered to the load (P2) reaches ‘a maximum value of 1 mW when the tum ratio equals the optimum value 5, The power dissipated in the source is also 1 mW for N = 5. Note that load power diminishes ‘0 0.64 mW at one-half the optimum ratio (N = 2.5) and at twice the optimum ratio W= 10). ANTER SOURCE RESSTANCE DH OHMS, 2503 INTER LOAD RESSTANCE DI OUMS, pies Biter source voutace. 70 ‘OPTIMUM TURKS RATIO® 5 11 nas a. 2 3 Hause. soniseas i Yeenen — Laware is ieee isooroe i Romesmos Greegtb is Har? Giese ; Berar Soesereo4 3s Troe dagaree ‘ iwarares Sateltoos is Laer tated! fo Tero Gatos ‘ % — eas’ aes 2 Pett & Sospes Fa Hosaseet 8 Ssamas & estaire-os s telesseas Ls ‘3.921182-07 — 3.921186-05460 ___ MULTISTAGE AMPLIFIERS ‘multistage amplifier are shown in Figure 11.33. Find 4 The overall voltage gain, vo/¥iq; and . The voltage gain that would be necessary in a fifth stage which, if added to the cascade, would make the overall-voltage gain 100 a 2 Ye incre volage gains ofthe sage in a (°° Pb anes g 133 (The gn of the it sage doesnot oad. ing Oy te signal sure sad tof he forth Sage Cos at ince cing hy ond en tc) The nat eb oe Rt ages 20 ‘kA and the output resistance of the fourth stage is 20 EN. Tw apie ives by 9 signal ‘source having resistance 25 kf and a 12-0 load iscomeced othe oupat ofthe ford age the source voltage is vy = 5 mV ms, find a elo Wlges Othe power pin dB, beweea the put to the it stage ad th fad 13) U6 ded met Sage amplifer ‘hos veal volgen 53.9803 Te Creu otage gun be Bs 2 ager an Be ‘equal, andthe voltage gain of the third stage isto be one-half thet of each ofthe first two, What should be the voltage gain of each stage? 1.4.) The open-circuit (unloaded) voltage gains ofthe sages inthe multistage amplifier shown in Fig- tre 11.34 are Agi = ~42, Apa = =26, and Ay 1.8. Find the overall voltage gain v/s. mulistage amplifiers tobe constructed using identical stages, each of which has lower cutoff frequency 15 Hz and upper cutoff frequency 30 itt. 4. What willbe the lower and upper cutoff fe- ‘quencies of the multistage amplifier? ». Ifthe midband, in-ireuit voltage gain of each stage is 8.2, what willbe the approximate voltage gain ofthe multistage amplifier at 7.5 Hz? At 300 ki? JA multistage amplifier consists of 3 identical ‘stages, cach of which has bandwidth 250 kHz. ‘The bandwidth of the multistage amplifier is 40 ‘iz. What are the lower and upper cutoff fr- quencies of each stage? C7. A multistage amplifier isto be constructed using 6ietical sages, each of which has lower cuaf? frequency 50 kHz and upper cutoff frequency 1 PPP Figure 11.33 (Exercises 11.1 and 11.2) Figure 11.34 (Exercise 11.4)exercises 461 asia @ on: oko nF 330: Figure 11.36 (Exercise 11.9) ‘MHz, What wil be the bandwicth ofthe multi (11.10, Repeat Exercise 11.9 with Ry changed to 100 Ree ani o COS a inna sewage (TTT Bade spot el ey rating thatthe 1+. capacitor shown in Fig- of the multistage amplifier in Exercise ue 11.35 should have? (Assume silicon tran- 118. sistrs and B= 100.) ». Sketch the asymptotic Bode plot the way it >. Ifthe capacitors electrolytic, shoud its pos- would appear if plotted on log-log paper. tive terminal be connecied w the collector of Label all break frequencies and asymptote )_ Q, or the base of Q.7 slopes. ¢ tansstorsth Figure 11:36 have the fotow-" (1 THE approximate lower cut frequency ing parameter values: of the multistage amplifir in Exercise 11.8 Qe et = 12, By = 200, re) = 2 MOD -when Ris changed 10 100 0. 5: 12 = 10, Be = 100 Sketch the asymptotic Bode plo the way it the midband values of ‘would appear if ploted on log-log eraph pa 2. the voltage gain v/v, and pe. Label all break frequencies and asymp- . the current gain i/is, tote slopes.462 MULTISTAGE AMPLIFIERS aoe Figure 11.37 (Exercise 11.14) 11-13, Find the approximate lower cutoff frequency of ‘the multistage amplifier in Figure 11.6 (Example i LB Fin in et ry ‘the 2-stage amplifier shown in Figure 11.37. The silicon transistors have the following parameter values: 100, fo) = | MH2, Coes = 10 9F, Cony = 5 PF ray = = Bz = 100, fgg = 1 MHZ, Coa = 20 BF, Coca = 6.5 DF, Cora = 5 pF, rea = (ine Fist Sind the bias curents Jy a fey in cnderto determine values for re) and ra. Use these to determine stage Snput resistances and ltage gain, The later are necessary to find the Miller capacitance.) 11.15,) The siticon transistors in Figure 11.38 both have 8 = 100, Find Figure 11.38 (Exercise 11.15) 8. Keay Ver» Veer, fear Vea. and Veexi and SZ). the small-signal gain vel, 6? Repeat Exercise 11.15 when a 60-K9 load is direct-coupled to the collector of Qs. Find the de collector eurents cy and dca andthe de colfector-to-ground voltages Voy and Vez in 1.18) Repeat Exercise 11,17 forthe amplifier shown in gue 11.4. 83 3 tasitors in the Dacingon pair shown in Figure 111 have fy = 80 ant Be = 100 In = 1 BA. ‘Using the same approximations used in the textto analyze a Darlington pair (fe = fe and Tr Tea) find Fens Feas fans Fens Leas Hr and Figure 11.39 (Exercise 11.17)Figure 11.40 (Exercise 11.18) Find ry and rz based on the values found in @. ©. Without using the approximations, find fc, dea nas Jets Teas Ir, ad Ven. Find the pe ‘cent error in the computation of Vez eaused by using the approximation. igure 11.43 (Exercise 11.21) exeRaists 463 ag t, | gro In of + Figure 11.41 (Exercise 11.19) 44. Find ray and reg based on the values found in ©. sion vaso Figure 1.42 have By = 120.and B = 110. Find (a) r(stage), (0) vel¥s, and (c) izlis. Gal) tetera age 148 eb dy 20 The eerie cer ane ‘Q) is 10 KA. Find approximate values for (a) (tage) and (b) vi/v. Figure 11.42 (Exercise 11.20)464 __ MULTISTAGE AMPLIFIERS 10x Figure 11.44 (Exercise 11.22) 11.22, Ane silicon transistors in Figure 11.48 have, = 11.24, The silicon transistors in the cascode amplifir in 100 and ey = 1. Assuming that r= rex * Figure 11.45 have B = Bx = 120. Find the de find values Fe1s dea» Vers Vex» Vers and Veen: a. the de currents and voltages fcr, lea. Veet» (Hint: The lozding caused by the base of Q, and and Ven} and (Qron the voltage divider can be neglected; use 3. the small-signal, midband voltage gain v/v. the voltage divider to find each base voltage.) 11.23, Transistor Q, in Exercise 11,22 has Cye = 4.2 11.25. Find the approximate midband voltage gain APF and Cpe = 5.4 pF. The wiring capacitance at vulvs of the cascode amplifier in Exercise the input to Qy is 10 pF. Find the upper break 124, frequency due to input capacitance. Figure 11.45 (Exercise 11.24)EXERCISES’ 465 Figure 11.46 (Exercise 11.26) ‘The JFETS in Figure 11.46 have gaa = 3000 nS, (11-28) The FETs in Figure 11.47 have gt av = 1OOKD, ga = 2000 uS, andrea = 60D. rat = 100KD, Baa = Find the midband voltage gain v/s. Find the midband voltage gain v,/vs. C27.) Find the approximate lower cutoff frequency of (11.29. The FETS in Figure'11.48 have pss the amplifier in Brercise 11.26 Vpi = 2 V, doses = I2-mA, and Vp + Figure 11.48 (Exercise 11,466 __ MULTISTAGE AMPLIFIERS: Figure 11.49 (Exercise 11.30) Find te de vats fps, Vast, Voss loa Vast» av he following parapet values iw tit Vos. ” Bi = 0.5 X 10", Vy = 2 Vs 29 = 75 (€30. The FETs in Figure 11.49 ae the same as those ry in Exerise 11.29 and they ae biased the same Qe:B2= 03 * 10°, Vn =2.6V, n= 100 sway. Assuming that ry = rag = ind he mid a band Voltage gain vz/v5 a in ie mia wos ah 11.31.) The MOSFETS in Figure {7.50 are biased so that transistors in Figure 11.51 have the follow- Vost = 4.8 V and Yo.'= 6 V. The transistors fing parameter values Figure 11.50 (Exercise 11.31) Figure 11.51 (Exercise 11.32)EXERCISES 467 Qi: Bm = 4 mS, rg, = 100 kD delivered to r.. Are source and load matched iby. Qu re 300, ra = 25M 0 the wanstormer? ind the midband voltage gai, »z/vs. AUS, a. ind he tars ratio inBercise 11.36 tht wi bias resistors (those bypassed with ‘capaci result in maximum power delivered to the 5) in Figure 1.51 ar ajsted to make py = loud. 63mA and fg, = 0.3 mA. foam = LDA sad , Using the tans ratio found in (), Sd the Yn = 4 find the midband voltage gain over dissipated in ry and the power eli whe. ered or. A signal sours having resistance 90 LO drived(_ 11.38) a What shold be the tums roof he wan the primary winding of « teaser whose former in Figue 11.53 in oer t éelies tums rao i 61. What vale of ood sesianee maximum power to 72 across the Secondary would result in maximum 5. Using the tums ratio found in), nd she power delivered tothe load? ower dissipated in 1, andthe power di. (3) 8 20.0 on str commend ste ered t0 7. Secondary ofa transformer whose ms rai ie ‘The taasitors in Figure 11.54 have By = Bs = 8620. What signal-souce impedance on he ri SOand ry = ran = 400. Find he volgen may side of the transformer would result in a/v Does the wansfmier match the fst stage maximum power tansfer othe load? tothe second? 11.36, jin the transformer: 11.46. Repeat Exercise 11.39 if the tums ratio of the find the power di transformer i changed t 1 ty, sy 240% na ie ep odne al fae ® Agia 3 el Vem Figure 11.52 (Exercise 11.36) Figure 11.53 (Exercise 11.38) Figure 11.54 (Exercise 11.39)AGB MULTISTAGE AMPLIFIERS Figure 11.55 (Exercise 11.41) soy ska: 1 s00: Tr 103 11,41, ‘The transistors in Figure 11.55 have the follow- ing parameter values: Qu: Br = 100, rey = 20.0, 75) = 20K Qe: Ba = 50, rap = 100, ron = 20k 1, Find the voltage gain, ys, ». Which transformers, if any, match the source 1 the load? 11.42, Repeat Exercise 11.41 when the tums ratios on all transformers are adjusted to obtain maximum power transfer. BASIC Programming Exercises 11.43, Write a BASIC program that prompts a user to center the in-circuit voltage gains f any number ‘of eascaded amplifier stages and then prints the ‘overal voltage gain in dB. Run your program for casceded amplifier stages having gains Ay = Figure 11.56 (Exercise 11.45) 10] 1.44, 114s. 4.2, Ay = “15.9, As = As = 0.61, ‘Write a BASIC program that prompts a user to center the midband voltage gsin of an amplifier and the values of any number of lower break ‘frequencies. The program should then prt the amplifier gain at any user-selected frequency. (int: For each break frequency f,, the mid- band gain is multiplied by the factor 1/{1 + (uf }92.) Using tial-and-error methods (com- piting amplifier gain at various frequencies), find the lower cutoff frequency of an amplifier ‘whose midband gain is 100 and whose lover break frequencies are 6.2 Hz, 10 Hz, 18 Hz, 20 He, and 25 He. ‘Write a BASIC programm that prompts a user to enter values for By, Bz. 15, Ri» Ro» Rev» Rer- Ry, Rey Beas Ren, a Ry it Figure 11.56 and 9.4, Aq = 16, and11.46. 1.47. excises 469 Figure 11.57 (Exercise 11.46)" i Figure 11.58 (Exercise 11.47) ‘then computes the voltage gain vz/¥s. (Neglect re and rein exch transistor.) Run your program for the following set of values: By = 120, Ba = 100, 75 = 1000, ry = 120 KM, Ry = 12 KO, Rex = 7.5 kh, Rey = 20 D, Ry ¥ 270 40, Ry = ASEO, Rez = 100, Rea © 1 kM, and Ry = SOKO. / Write a BASIC program that prompts a user to center values fot Vpis Vpas Iossts Tossa» Ps» Ris Ro, Rots. Re, Rons Bs tox, te Joa i Figure 1.57 and then computes the voltage gain v./¥s. (Neglect the 2 of each FET.) Run your program forthe following set of values: Vpy = ~2.6 V, Vpn = ~19Vs Fossi = 12mA, Ipgia = LOMA, 1= 1OKM,R) = LSMO,Ro = 47040 Roy 2.2 kM, Ry = 470 kM, Ry = 100 KO, Roa = 4M, Ry, = 200, fp) = 4.6 mA, and Joa = Salma. Figure 11.58 shows the equivalent ciruit of 2 ‘transistor amplifier whose output is wansformer- coupled toa load. Write a BASIC program that ‘prompts auser to enter values for vs (rms valve), sy Tow Bs Fox and Ry, ad then comptes and peat 4 the runt rato Np, that ess in maximo power delivered to Ry; and '. a table showing the voltage gxin v/v eu * feat gain iiyy and power gain Py/Py {Or the sequenes of tums ratios 0.52, 0.552, 0.60, - 0.954, a, 1.84, 24, 2.50. «5 Sa, where is the tus rt that results in ‘maximum power 1 the loud. Rn your program forthe following st of val ues: vg 01 Vrms r5 = 500 Oy Fy = 1.5 KD {= 100, r»= SOKA, and = 240. Deserbe the varstion of voltage gain and eurent gins @ function of transformer turns rao