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CHAPTER 6
I/O SYSTEMS
OUTLINE
Overview
I/O Hardware
Application I/O Interface
Kernel I/O Subsystem
Life Cycle of An I/O Request
Performance
OBJECTIVES
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OVERVIEW
Overview
I/O Hardware
Application I/O Interface
Kernel I/O Subsystem
Life Cycle of An I/O Request
Performance
I/O HARDWARE
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A TYPICAL PC BUS STRUCTURE
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I/O HARDWARE (CONT.)
Fibre channel (FC) is complex controller, usually separate circuit board (host-bus
adapter, HBA) plugging into bus
I/O instructions control devices
Devices usually have registers where device driver places commands, addresses, and
data to write, or read data from registers after command execution
Data-in register, data-out register, status register, control register
Typically 1-4 bytes, or FIFO buffer
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HOW CAN THE PROCESSOR GIVE COMMANDS AND DATA TO A
CONTROLLER TO ACCOMPLISH AN I/O TRANSFER?
Devices usually have registers where device driver places commands, addresses, and
data to write, or read data from registers after command execution
The processor communicates with the controller by reading and writing bit patterns
in these registers.
Two ways:
I/O instructions: specify the transfer of a byte or word to an I/O port address
Memory-mapped I/O: Device data and command registers mapped to processor address space
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DEVICE I/O PORT LOCATIONS ON PCS (PARTIAL)
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3 TYPES OF I/O:
1. Polling
2. Interrupts
3. Direct Memory Access (DMA)
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1. POLLING
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1. POLLING (CONT.)
In step 1, the host is busy-waiting or polling: it is in a loop, reading the status register
over and over until the busy bit becomes clear.
If the controller and device are fast, this method is a reasonable one. But if the wait
may be long, the host should probably switch to another task.
For some devices, the host must service the device quickly, or data will be lost.
For instance, when data are streaming in on a serial port or from a keyboard, the small
buffer on the controller will overflow and data will be lost
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1. POLLING (CONT.)
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2. INTERRUPTS
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INTERRUPTS (CONT.)
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INTERRUPT-DRIVEN I/O CYCLE
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INTEL PENTIUM PROCESSOR EVENT-VECTOR TABLE
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POOLING VS INTERRUPTS
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3. DIRECT MEMORY ACCESS (DMA)
Used to avoid programmed I/O (Pooling) (one byte at a time) for large data movement
Transfer data directly between I/O device and memory
OS writes DMA command block into memory
Source and destination addresses
Read or write mode
Count of bytes
Writes location of command block to DMA controller
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SIX STEP PROCESS TO PERFORM DMA TRANSFER
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OUTLINE
Overview
I/O Hardware
Application I/O Interface
Kernel I/O Subsystem
Life Cycle of An I/O Request
Performance
APPLICATION I/O INTERFACE
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CHARACTERISTICS OF I/O DEVICES
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OUTLINE
Overview
I/O Hardware
Application I/O Interface
Kernel I/O Subsystem
Life Cycle of An I/O Request
Performance
A KERNEL I/O STRUCTURE
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CHARACTERISTICS OF I/O DEVICES (CONT.)
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CHARACTERISTICS OF I/O DEVICES
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BLOCK AND CHARACTER DEVICES
DMA
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NETWORK DEVICES
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TWO I/O METHODS
Synchronous Asynchronous
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KERNEL I/O SUBSYSTEM
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SCHEDULING
Device-status table
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COMMON PC AND DATA-CENTER I/O DEVICES AND INTERFACE
SPEEDS
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BUFFERING
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SUN ENTERPRISE 6000 DEVICE-TRANSFER RATES
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KERNEL I/O SUBSYSTEM
Buffer may hold the only existing copy of a data item, whereas a cache holds a copy on
faster storage
Sometimes combined with buffering
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KERNEL I/O SUBSYSTEM (CONT.)
OS can recover from disk read, device unavailable, transient write failures
Retry a read or write, for example
Some systems more advanced – Solaris FMA, AIX
Track error frequencies, stop using device with increasing frequency of retry-able errors
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USE OF A SYSTEM CALL TO PERFORM I/O
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OUTLINE
Overview
I/O Hardware
Application I/O Interface
Kernel I/O Subsystem
Life Cycle of An I/O Request
Performance
LIFE CYCLE OF AN I/O REQUEST
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LIFE CYCLE OF AN I/O REQUEST
1. A process issues a read() system call to a file descriptor of a file that has been opened
2. The system-call code in the kernel checks the parameters for correctness. if the data are already available in the buffer cache, the data are
returned to the process
3. Otherwise, a physical I/O must be performed. The process is removed from the run queue and is placed on the IO queue, and the I/O request
is scheduled.
4. The device driver allocates kernel buffer space to receive the data. The driver sends commands to the device controller by writing into the
device-control registers.
5. The device controller operates the device hardware to perform the data transfer.
6. The driver may poll for status and data, or it may have set up a DMA transfer into kernel memory. An interrupt may be generated when the
transfer completes.
7. The interrupt handler receives the interrupt, stores necessary data, signals the device
8. The device driver receives the signal, determines which I/O request has completed, the request’s status, and signals that the request has been
complede
9. The kernel transfers data or return codes to the address space of the requesting process and moves the process from the wait queue back to
the ready queue.
10. The process resumes execution at the completion of the system call.
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LIFE CYCLE OF AN I/O REQUEST (CONT.)
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OUTLINE
Overview
I/O Hardware
Application I/O Interface
Kernel I/O Subsystem
Life Cycle of An I/O Request
Performance
PERFORMANCE
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INTERCOMPUTER COMMUNICATIONS
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IMPROVING PERFORMANCE
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DEVICE-FUNCTIONALITY PROGRESSION
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I/O PERFORMANCE OF STORAGE (AND NETWORK LATENCY)
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