Computer Architecture and

Organization (ECEG- 3141)

Chapter 5
Input Output

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 Chapter 5 – I/O

• In this chapter:
– Peripheral Devices
– I/O techniques
– DMA

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 I/O Issues
• Why not connect peripherals directly to
system bus?
– Wide variety of peripherals
• Delivering different amounts of data
• At different speeds
• In different formats
– All slower than CPU and RAM
• Need I/O modules

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 I/O Issues
• I/O modules
– Interface to CPU and Memory
– Interface to one or more peripherals
Device
Interface External
I/O sensors
Processor Bus Module Device and
Interface controls

Device
Interface

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 Peripheral Devices
• Provide means of exchanging data b/n
external envt and computer
• Types
– Human readable
• communication with user (monitor, printer, keyboard,
mouse)
– Machine readable
• communication with equipment (hard drive, CDROM,
sensors, and actuators)
– Communication
• communication with remote computers/devices
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(modem, Network Interface Card (NIC))
 Peripheral Devices

• Block diagram of an external device

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 Peripheral Devices
• Control logic
– Is the I/O module's interface to the device
• Data channel
– Passes the data from/to the device
– On the opposite end is the I/O module, but eventually it is the
processor.
• Transducer
– Acts as a converter between the digital data of the I/O module and the
signals of the outside world.
– Keyboard converts motion of key into data representing key pressed or
released
– Temperature sensor converts amount of heat into a digital value
– Disk drive converts magnetic patterns on disk to bits in the device
buffer

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 I/O Modules
• Functions
– Control & Timing
– CPU Communication
– Device Communication
– Data Buffering
– Error Detection

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 I/O Modules
• Control and Timing
– Required because of multiple devices
communicating on the same channel
– Example
• CPU checks I/O module device status
• I/O module returns status
• If ready, CPU requests data transfer
• I/O module gets data from device
• I/O module transfers data to CPU

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 I/O Modules
• CPU Communication
– Commands from processor
• Examples: READ SECTOR, WRITE SECTOR, SEEK track number
– Data
• Passed back and forth over the data bus
– Status reporting
• Request from the processor for the I/O Module's status
• May be as simple as BUSY and READY
– Address recognition
• The I/O module must recognize one unique address for each
device it controls

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 I/O Modules
• Device Communication
– Specific to each device (commands, status, data)
• Data Buffering
– Due to the differences in speed (device is usually orders of
magnitude slower) the I/O module needs to buffer data to
keep from tying up the CPU's bus with slow reads or writes
• Error Detection
− Distribute the error handling to the module
− Malfunctions by device (paper jam)
− Data errors (parity checking at the device level)
− Internal errors to the I/O module such as buffer overruns
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I/O Module Structure

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 I/O Module Operation
• How much control will the CPU be required to
handle?
• How much will the CPU be allowed to handle?
• What will the interface look like?
– e.g., Unix treats everything like a file
• Support multiple or single device?

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 I/O Module Operation
• Types of I/O modules
– I/O channel (I/O processor)
• Responsible for the detailed processing burden
• Presents a high-level interface to CPU
− I/O controller (device controller)
− Quite primitive
− Requires detailed control

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 I/O Techniques
• Programmed I/O
– poll and response
• Interrupt Driven I/O
– module calls for CPU when needed
• Direct Memory Access (DMA)
– I/O module has direct access to specified block of
memory

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I/O Techniques

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 Programmed I/O
• Operation
– CPU fetches I/O instruction from memory
– CPU issues I/O command
– I/O module performs operation
– I/O module sets status bits
– CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later
• Wastes CPU time because typically the processor is
much faster than I/O
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 Programmed I/O
• I/O commands (from CPU to I/O module)
– CPU issues address
• Identifies module (and device if more than one per
module)
– CPU issues command
• Control - telling module what to do
– e.g. spin up disk
• Test - check status
– e.g. powered?, error?
• Read/Write
– Module transfers data via buffer from/to device

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 P ro g ram m ed I/O

 I/O instructions (part of program, fetched by CPU from memory)

 Most important – addressing I/O devices
Under programmed I/O, data transfer is much like memory
access (CPU viewpoint)
Each device given unique identifier
CPU commands contain identifier (address)
Thus, each I/O module must interpret the address lines to
determine if the command is for itself.
When the processor, main memory, and I/O share a common
bus, two modes of addressing are possible
Memory-mapped I/O
Isolated I/O

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 Programmed I/O

 Memory-mapped I/O
 I/O devices and memory share a single address space
 The processor treats the status and data registers of I/O
modules as memory locations
 I/O read/write looks just like memory read/write
 No special commands for I/O
 Isolated I/O
 Same address lines, but separate address spaces
 Need extra lines to select I/O or memory
 Special commands for I/O
Limited set

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 Interrupt Driven I/O

 Overcomes CPU waiting

 Requires setup code and interrupt service routine
 No repeated CPU checking of device
 I/O module interrupts when ready
 Still requires CPU operation for moving data between I/O
module and main memory

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 Interrupt Driven I/O

 Operation (I/O module viewpoint)

 I/O module receives read command from CPU
 I/O module gets data from peripheral
 Once data is in I/O module register, it interrupts CPU
 I/O module waits for CPU to request
 When requested by CPU, I/O module places data on bus

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 Interrupt Driven I/O

 Operation (CPU viewpoint)

 CPU issues read command
 Does other work
 Checks for interrupt at end of each instruction cycle
No code is involved in this
 If interrupted:
Saves context (registers)
Processes interrupt
Fetches data from I/O module & stores it in memory
Restores context

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Interrupt Processing

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 Design Issues

 Resolution of multiple interrupts

 How do you identify the module issuing the interrupt?
 Priority
 How do you deal with multiple interrupts (at the same time
or interrupting in the middle of an interrupt handler)?

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 Identifying Interrupting Module

 Multiple interrupt lines

 Different line for each module
 Limits number of devices
 Even with this method, there still may be multiple interrupts on
a single interrupt line
 Priority
set by hardware

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 Identifying Interrupting Module
 Software poll
 When the processor detects an interrupt:
It branches to an interrupt-service routine whose job it is to
poll each I/O module to
 determine which module caused the interrupt
 Single interrupt line
 CPU asks each module to see who needs attention
 Slow
 Priority
set by the order in which CPU polls the devices

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 Example – Interrupt Controller
 82C59A Interrupt Controller
 Used with 80386 processor
 CPU has one interrupt line
 8259A has 8 interrupt
lines

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 Example:– Interrupt Controller

 Sequence of events
 82C59A accepts interrupts
 82C59A determines priority
Fully nested
IR0 (highest) through IR7 (lowest)
Rotating
after interrupt is serviced, it goes to bottom of priority list
Special mask
allows individual interrupts to be disabled
 82C59A signals CPU (raises INTR line)
 CPU acknowledges (with INTA line)
 82C59A puts correct vector on data bus
 CPU processes interrupt
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 Direct Memory Access

 Motivation
 Both programmed I/O and interrupt driven I/O require active
CPU intervention
 Transfer rate is limited by CPU's ability to service the device
 CPU is tied up managing I/O transfer
 Direct memory access (DMA)
 Additional module (hardware) on bus
 DMA controller takes over bus from CPU for I/O
Waiting for a time when the processor doesn't need the bus
Cycle stealing:– seizing bus from CPU (more common)

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 31
DMA module
 Direct Memory Access

 Operation
 When the processor wishes to read or write a block of data, it
issues a command to the DMA module
 CPU tells DMA controller:
Read/Write
Device address
Starting address of memory block for data
Amount of data to be transferred
 CPU performs other work
 DMA controller performs transfer
 DMA controller sends interrupt when finished

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 Direct Memory Access

 Cycle stealing
 DMA controller takes over bus for a cycle
 Transfer of one word of data
 Not an interrupt
CPU does not switch context
 CPU suspended just before it accesses bus
i.e. before an operand or data fetch or a data write
 Slows down CPU but not as much as CPU doing transfer

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 DMA Configurations

 Single bus, detached DMA controller

 Each transfer uses bus twice
I/O to DMA then DMA to memory
 CPU is suspended twice

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 DMA Configurations

 Single bus, DMA controller integrated into I/O module

 Controller may support one or more devices
 Each transfer uses bus once
DMA to memory
 CPU is suspended once

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 DMA Configurations
 Separate I/O Bus
Reduces number of I/O interfaces in DMA module
to one  expandable configuration
Each transfer uses bus once
 DMA to memory
CPU is suspended once

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 Mode of Transfer
 Data transfer between different components of a computer
takes place through a group of electrical connection lines
called buses.
 A bus can be synchronous, if data transfer over the bus is
controlled by a bus clock i.e. the clock acts as the timing
reference for all bus signals.
 A bus is asynchronous, if data transfer over the bus is based on
the availability of the data not on a clock signal.

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 Capter 6
Introduction to parallel processing
Low level data structure
Introduction to Operating System

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Thank you for your attention !!!

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