Advanced Computer Architecture

CS-522

MS – Computer Science

Credit Hours : 3-0

Dr. Shahid Latif (Associate Professor)

Department of Computer Science & IT

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Sarhad University of Science and Information Technology, Peshawar
Course Details
Course title/code: Adv. Computer Architecture/CS-522

Lecture: 07
Topic: Input/Output (External Devices)
Program: MS – Computer Science (Sem: 1st, 2nd, 3rd & 4th)

Department of Computer Science & IT

Sarhad University of Science and Information Technology, Peshawar 2
Lecture Outlines
• Computer System Modules • Programmed I/O
• Input/output Problems • I/O commands
• I/O Module Function • Addressing I/O Devices
• External Devices • I/O Mapping
• Categories • Memory Mapped I/O
• Block diagram • Isolated I/O
• Keyboard/Monitor • Interrupt Driven I/O
• Disk Drive • Simple Interrupt Processing
• CPU Viewpoint
• I/O Modules
• Identifying Interrupting Module
• Module Function • Multiple Interrupts
• I/O Step
• I/O Module Structure • Direct Memory Access
• Input Output Techniques • Drawbacks of Programmed and
Interrupt-Driven I/O
• DMA Function
• Intel 8237A DMA Controller 3
Computer System modules
• The processor
• Set of memory modules
• Set of I/O modules
– Each I/O module interfaces to the system bus or central switch
– controls one or more peripheral devices

• An I/O module is
– Set of mechanical connectors (that wire an I/O device into the system bus)
– Contains logic/circuit for performing a communication function
between the peripheral and the bus
Input/output Problems
Why I/O module? Why not connect peripherals directly to the system bus …..?

• Wide variety of peripherals with various methods of operation

• Data transfer rate (transfer speed) of peripherals i.e.
– much slower than that of the memory or processor or
– faster than that of the memory or processor
– the mismatch would lead to inefficiencies if not managed properly
• Peripherals often use
– different data formats
– word lengths than the computer to which they are attached

• So an I/O module is required

I/O Module Functions
General I/O module has two major functions:

1. Interface to CPU and Memory (via the system bus or central

switch)
2. Interface to one or more peripheral devices
Generic Model of an I/O Module
External Devices
• External devices: provide mean of exchanging data between
external environment and computer

• Categories
– Human readable (suitable for communicating with computer user)
• Screens, video displays, printer
– Machine readable (suitable for communicating with equipment)
• Magnetic disks, tapes, sensors & actuators (i.e. monitoring and control in
robotics)
– Communication (suitable for communicating with remote devices)
• Modem, another computer
External Device Block Diagram
• Control signals: determines Function the device will perform,
• send data to I/O module (READ), accept data from I/O module
(WRITE)
• report status
• perform some control function of device (e.g., position of a disk
head)
• Data signals: reveals form of a set of bits to be sent to or
received from the I/O module
• Status signals indicate the state of the device
• E.g. READY/NOT-READY (to show whether the device is ready for
data transfer)
• Transducer converts data between electrical and other forms
of energy
External Device Block Diagram
Keyboard/Monitor
• Most common means of computer/user interaction is a
keyboard/monitor arrangement
– user provides input through the keyboard
– This input is then transmitted to the computer and may also be displayed on the
monitor
– In addition, the monitor displays data provided by the computer
• The basic unit of exchange is the character
– Associated with each character is a code, typically 7 or 8 bits in length
– common text code is the International Reference Alphabet (IRA)
– Each character in this code is represented by a unique 7-bit binary code
– thus, 128 different characters can be represented
– Characters are of two types: printable and control
– Printable characters are the alphabetic, numeric, and special characters that can be
printed on paper or displayed on a screen
• Some of the control characters have to do with controlling the printing or displaying of characters
Keyboard/Monitor
• For keyboard input,
– when the user depresses a key,
– this generates an electronic signal that is interpreted by the transducer in the
keyboard
– translated into the bit pattern of the corresponding IRA code
– This bit pattern is then transmitted to the I/O module in the computer
• At the computer, the text can be stored in the same IRA code
• On output,
– IRA code characters are transmitted to an external device from the I/O module
– The transducer at the device interprets this code and
– sends the required electronic signals to the output device either to display the
indicated character or perform the requested control function
Disk Drive
• A disk drive contains
– electronics for exchanging data, control, and status signals with an I/O module
– plus the electronics for controlling the disk read/write mechanism

• In a fixed-head disk, the transducer is capable of converting between the

magnetic patterns on the moving disk surface and bits in the device’s
buffer

• A moving-head disk must also be able to cause the disk arm to move
radially in and out across the disk’s surface.
An I/O Module

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I/O Module Function
• Control & Timing
– to coordinate the flow of traffic between internal resources and external
devices
• CPU Communication
– Involves: command decoding, data, status reporting (not Ready),
address recognition
• Device Communication
– Involves: commands, status information, and data
• Data Buffering
– I/O module must operate at acceptable transfer rate
• Error Detection
– Transmission error (parity), Mechanical/electrical errors (paper jam)
I/O Steps
(traffic between internal resources and external devices)

• CPU checks I/O module device status

• I/O module returns status
• If ready, CPU requests data transfer
• I/O module gets data from device
• I/O module transfers data to CPU

– Remember, there are Variations for output, DMA, etc.

I/O Module Diagram
Input Output Techniques
Three techniques are possible for I/O operations:

– Programmed I/O
– Interrupt driven I/O
– Direct Memory Access (DMA)
 Three Techniques for
Input (reading) of a Block of Data
Programmed I/O
• Data are exchanged between the processor and the I/O module
• CPU has direct control over I/O through program
– Sensing status
– Read/write commands
– Transferring data
• CPU waits for I/O module to complete operation
– Disadvantage: Wastes CPU time
Programmed I/O - detail
• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later
I/O Commands
• CPU issues address
– Identifies module (& device if >1 per module)
• CPU issues command
– Control - telling module what to do
• e.g. spin up disk
– Test - check status
• e.g. power? Error?
– Read/Write
• Module transfers data via buffer from/to device
Addressing I/O Devices
• Under programmed I/O, data transfer is very similar to
memory access

• Each device given unique identifier

• CPU commands contain identifier (address)

I/O Mapping
• Memory mapped I/O
– Devices and memory share an address space
– I/O looks just like memory read/write
– No special commands for I/O
• memory access commands available
• Isolated I/O
– Separate address spaces
– Need I/O or memory select lines
– Special commands for I/O
• Limited set
Memory Mapped and Isolated I/O
Interrupt Driven I/O
• Overcomes CPU waiting
• No repeated CPU checking of device
• I/O module interrupts when ready
Interrupt Driven I/O
Basic Operation
• CPU issues read command
• I/O module gets data from peripheral
whilst (at the same time) CPU does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data
Simple
Interrupt
Processing
CPU Viewpoint
• Issue read command
• Do other work
• Check for interrupt at end of each instruction cycle
• If interrupted:-
– Save context (registers)
– Process interrupt
• Fetch data & store
Changes in Memory and Registers for an Interrupt
Design Issues
• How do you identify, which module is issuing the interrupt?

• How do you deal with multiple interrupts?

– i.e. an interrupt handler being interrupted
Identifying Interrupting Module (1)
• Different line for each I/O module (multiple interrupt lines between
processor and I/O Module)
– Impractical: to dedicate more than a few bus lines or processor pins to
interrupt lines
– If few lines, then it Limits number of devices

• Software poll
– CPU detects an interrupt, it asks each module in turn
– with the help of command TEST I/O
– Reading the Status register of each I/O module
– Slow (time consuming)
Identifying Interrupting Module (2)
• Daisy Chain (a series of interconnected things or events) or Hardware poll or
vectored interrupt
– All modules share a common interrupt request line (INTR pin)
– Interrupt Acknowledge sent down a chain
– Module responsible places vector (word) on bus
– CPU uses this vector to identify the device

• Bus arbitration or Bus Master

– Module must claim the bus before it can raise interrupt
• thus only one module can raise the line at a time
• processor detects the interrupt, it responds on the interrupt acknowledge line
• requesting module then places its vector on the data lines
Multiple Interrupts
• Each interrupt line has a priority
• Higher priority lines can interrupt lower priority lines
 Example - PC Bus

• 80x86 has one interrupt line (INTR)

• 8086 based systems use one 8259A interrupt controller
• 8259A has 8 interrupt lines
Sequence of Events
• 8259A accepts interrupts
• 8259A determines priority
• 8259A signals 8086 (raises INTR line)
• CPU Acknowledges
• 8259A puts correct vector on data bus
• CPU processes interrupt
82C59A Interrupt
Controller
Direct Memory Access
• Interrupt driven and programmed I/O require active CPU
intervention (involvement)
– any data transfer must traverse a path through the processor

– Transfer rate is limited (b/c processor test and service a device)

– CPU is tied up (in managing an I/O transfer; a number of instructions

must be executed for each I/O transfer)

• DMA is the answer

DMA Function
• Additional Module (hardware) on bus

• DMA controller takes over control of the system from CPU for
I/O
Typical DMA Module Diagram
DMA Operation
• CPU tells DMA controller:-
– Read/Write
– Device address
– Starting address of memory block for data
– Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when finished
• Processor is involve only at the begging and at the end of
transfer
DMA Transfer - Cycle Stealing
• DMA controller takes over bus for a cycle
• Transfer of one word of data at a time
• Not an interrupt
– CPU does not switch context
• CPU suspended just before it accesses bus
– i.e. before an operand fetch/data fetch/data write
• Slows down CPU by pausing for a cycle
DMA and Interrupt Breakpoints
During an Instruction Cycle
 DMA Configurations (1)

• Single Bus, Detached DMA controller

• Each transfer uses bus twice
– I/O to DMA then DMA to memory
• CPU is suspended twice
 DMA Configurations (2)

• Single Bus, Integrated DMA controller

• Controller may support >1 device
• Each transfer uses bus once
– DMA to memory
• CPU is suspended once
 DMA Configurations (3)

• Separate I/O Bus

• Bus supports all DMA enabled devices
• Each transfer uses bus once
– DMA to memory
• CPU is suspended once
Intel 8237A DMA Controller
• Interfaces to 80x86 family and DRAM
• When DMA module needs buses it sends HOLD signal to processor
• CPU responds HLDA (hold acknowledge)
– DMA module can use buses
• E.g. transfer data from memory to disk
1. Device requests service of DMA by pulling DREQ (DMA request) high
2. DMA puts high on HRQ (hold request),
3. CPU finishes present bus cycle (not necessarily present instruction) and puts
high on HDLA (hold acknowledge). HOLD remains active for duration of
DMA
4. DMA activates DACK (DMA acknowledge), telling device to start transfer
5. DMA starts transfer by putting address of first byte on address bus and
activating MEMR; it then activates IOW to write to peripheral. DMA
decrements counter and increments address pointer. Repeat until count
reaches zero
6. DMA deactivates HRQ, giving bus back to CPU
8237 DMA Usage of Systems Bus
 Thank you

Dr. Shahid Latif (Associate Professor)

Department of Computer Science & IT
Sarhad University of Science and Information Technology, Peshawar

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