Interrupt(INTR):

In digital computers, an interrupt is a response by the processor to an event

that needs attention from the software. An interrupt condition alerts the
processor and request to interrupt the currently executing code so that the event
can be processed in a timely manner. If the request is accepted, the processor
responds by suspending its current activities, saving its state, and executing a
function called an interrupt service routine(ISR) to deal with the event. Atleast
one of the control lines called interrupt request line is dedicated for this
purpose.This interruption is temporary, and the processor resumes normal
activities after the interrupt Service routine finishes.

What is interrupt hardware? Explain Enabling and Disabling of interrupt

An I/O device request an interrupt by activating a bus line called Interrupt
Request(IR). A single IR Line can be used to serve “n” devices.All devices are
connected to IR Lines via switches to ground.To request an interrupt, a device
closes its associated switch. Thus if all IR signals are inactive the voltage on the
IR Line will be equal to Vdd.When a device request an interrupt , the voltage on
the line drops to 0, causing INTR received by the processor to go to 1
INTR=INTR1+INTR2+.........+INTRn
A special gate known as open collector or open drain are used to drive the
INTR line.

Enabling and Disabling Interrupt

All computers fundamentally should be able to enable and disable interruption

as desired. The problem of infinite loop occurs due to successive interruptions
of active INTR signals.To solve the problem of infinite loop there are 3
mechanisms:
1) The processor hardware must ignore the interrupt request line until the
execution of first instruction of ISR has been completed.
2)The processor should automatically disable interrupts before starting the
execution of the interrupt-service routine.
3)The processor has a special interrupt-request line for which the
interrupt-handling circuit responds only to the leading edge of the signal. Such
a line is said to be edge-triggered.

Assuming that interrupts are enabled, the following steps takes place
1. The device raises an interrupt request.
2. The processor interrupts the program currently being executed.
3. Interrupts are disabled by changing the control bits in the PS .
4. The device is informed that its request has been recognized, and in response,
it deactivates the interrupt-request signal.
5. The action requested by the interrupt is performed by the interrupt-service
routine.
6. Interrupts are enabled and execution of the interrupted program is resumed.

Handling Multiple Devices:

If two devices raise the interrupt request at the same time it must be possible to
break the tie and select one of the two request for service.when the interrupt
service routine for selected device has been completed the second can be
services.The interrupt from multiple devices are handled by the
1) Polling
2) Vectored interrupt
3) interrupt nesting
4)simultaneous request
Polling: Information needed to determine whether the device is requesting
interrupt is available in the status register. When a device raises an interrupt
request, it sets IRQ bit to 1 in its status register.The simplest way to identify the
interrupting device is to have the interrupt service routine poll at all the I/O
devices in the system.The first device with its IRQ bit set to 1 should be
serviced.
The polling scheme is easy to implement. Its main disadvantage is the time
spent interrogating the IRQ bits of devices that may not be requesting any
service. An alternative approach is to use Vectored interrupt.

Vectored interrupt: A device requesting an interrupt identifies itself by

sending a special code to processor over bus.Then the processor starts executing
the ISR. The special code indicates the starting address of ISR and its length
ranges from 4 to 8 bits. The location pointed by the interrupting device is used
to store the starting address to ISR. This starting address to ISR is called the
interrupt vector.
The processor loads interupt vector into PC and execute appropriate ISR.
Interrupting device must wait to put the data on bus only when the processor is
ready to receive it.When the processor is ready to receive the interrupt vector
code it activates INTA line. Then I/O device responds by sending its interrupt
vector code and turning off the INTR signal.

Interrupt nesting: In this method input/output devices are organised according

to a priority structure. This means that interrupt requests from a higher priority
device is recognised where as request from a lower priority is not.
A multiple-priority scheme can be implemented easily by using separate
interrupt-request(INTR) and interrupt-acknowledge(INTA) lines for each
device.Each of the interrupt-request lines is assigned a different priority level.
The priority level of the processor is the priority of the program that is currently
being executed. The processor accepts interrupts only from devices that have
priorities higher than its own.
At the time of execution of ISR for some device priority of processor is raised
to that of the device.Thus interrupt from device at the same level of priority or
lower are disabled.
The processor’s priority is usually encoded in a few bits of the processor
status(PS) word. It can be changed by priviliged instructions that write into the
PS .These privileged instructions can be executed only while the processor is
running in the supervisor mode.The processor is in the supervisor mode only
when executing operating system routines.

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Simultaneous Requests: When there is a problem of simultaneous arrivals of

interrupt requests from two or more devices the processor must have some
means to decide which requests to service first. Using a priority scheme , the
processor simply accepts the requests having the highest priority.
Polling the status registers of the I/O devices is the simplest of such mechanism.
In this case, priority is determined by the order in which the devices are polled.
A widely used scheme is to connect the devices to form a daisy chain, ( Explain
the daisy chain technique)
* The interrupt request lines ,INTR, is common to all devices
*The interrupt-acknowledge line, INTA, is connected in a daisy-chain fashion,
and signal is propogated serially.
*When several devices raise an interrupt request the the processor responds by
setting the INTA line to 1. This signal is received by device 1. Device 1 passes
the signal on to device 2 only if it does not require any service. If device
1 has a pending request for interrupt, it blocks the INTA signal and proceeds to
put its identifying code on the data lines. Therefore, in the daisy-chain
arrangement, the device that is electrically closest to the processor has the
highest priority. The second device along the chain has second highest priority,
and so on.

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Q) Define Exceptions . Explain its types
A) An interrupt is an event that causes the execution of one program to be
suspended and the execution of another program to begin .The term exception
is often used to refer to any event that causes an interrupt. I/O interrupt is one
example of exception.
Recovery from errors: Computers use variety of techniques to ensure that all
hardware components are operating properly. For eg. Many computers include
an error checking code in main memory which allows the detection of errors in
stored data. If error occurs, control hardware detects it and inform processor by
raising an interrupt.The processor suspends program being executed and starts
an ESR(Exception Service Routine). This routine takes appropriate action to
recover from the error and inform the user about it.
Debugging: System software usually includes a program called debugger
which helps the programmer to find an error in a program. The debugger uses
exceptions to provide two important facilities called trace mode and
breakpoints.
Trace mode: when a processor is operating in a trace mode, an interrupt occurs
after the execution of every instruction. An interrupt service routine in the
debugger program is invoked each time this interrupt occurs. Debugging
program enables user to examine contents of registers and memory locations
and so on. After returning from the debugging program next instruction in the
program beig debugged is executed. And then debugging program is activated
again.
Breakpoints: This is similar to trace mode except that the program which is
being debugged is interrupted only at specific points selected by the user.An
instruction called Trap or softerware interrupt is usually provided for this
purpose.
Privilege Exception :To protect OS of computer from being corrupted by user
programs certain instructions can be executed only when the processor is in the
supervisor mode .These are called privileged instructions.An attempt to
execute such an instructions will produce a privilage exception.As a result
processor switches to superwise mode and begin to execute the required action.

Q) Explain Direct Memory Access(DMA)

or
Explain DMA controller with a neat diagram
A) To transfer large blocks of data at high speed, between an external device
and main memory without continuous intervention by the processor is called as
Direct memory Access.. The .DMA transfers are performed by special control
unit called DMA controller.This DMA controller performs the functions that
would normally be carried out by the processor.In controller, three registers are
accessed by processor to initiate transfer operations.
First register are used for storing starting address
second register are used for storing word count
Third register contains status & control flags
The R/W bit determines the direction of transfer.
When R/W=1 the controller performs a read operation i.e transfers data from
memory to I/O. Otherwise it performs write operation i.e transfers data from
I/O device to memory.
When Done=1 , controller completes transferring a block of data and gets
ready to receive another command.
When IE(Interrupt Enable)=1, controller raises an interrupt after it has
completed transferring a block of data.
Finally when IRQ=1, controller requests an interrupt.( Request by DMA device
for using a bus is always given higher priority than a request by processor).
There are two ways in which DMA operations are carried out.
In one method, processor originates most memory access cycles.DMA
controller is said to “steal” memory cycles from processor.Hence this technique
is called cycle stealing
In second method DMA controller is given exclusive access to main memory to
transfer a block of data without any interruption This is known as block mode or
burst mode
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Bus Arbitration:
Bus arbitration is the process by which next device to become the
bus master is selected and bus mastership is transferred to it.The
device that is allowed to initiate data transfer on bus at any given
time is called bus master.There can be only one bus master at any
given time
There are two approaches to bus arbitration
1) centralized bus arbitration:- Single bus arbiter performs the
required arbitration
2) distributed bus arbitration:-All devices participate in the
selectio of next bus master.
Centralized Arbitration:
*The arbiter may be the processor or a seperate unit connected to
the bus. The processor is normally the bus master unless it grants
bus mastership to one of theDMA controllers.
* The DMA controller indicates that it needs to become the bus
master by activating the Bus Request Line BR.The signal on Bus
Request Line is logical OR of bus request from all devices
connected to it.
* When Bus Request Line is activated, Processor activates Bus
Grant Signal BG1 indicating to DMA controllers that they may
use bus when it becomes free.This signal is connected to all DMA
controllers using Daisy chain arrangement.
* Thus if DMA controller 1 is requesting the bus it blocks
propogation of grant signal to other devices. Otherwise it passes
the grant downstream by asserting BG2.
* Current bus master indicates to all devices that it is using bus by
activating Bus-Busy Line (BBSY).Hence after receiving the Bus
Grant signal DMA controller waits for the Bus Busy to become
inactive, then assumes mastership of the bus..At this time it
activates the Bus -Busy to prevent the other devices from using
the bus at the same time
* Arbiter circuit ensures that only one request is granted at ny
given time according to predefined priority scheme. For example,
if there are four bus request lines BR1 through BR4, according to
fixed priority scheme BR1 is given top priority and BR4 is given
lowest priority.Alternatively a rotating priority scheme may be
used to give all devices an equal chance of being served.

Distributed Arbitration:
In distributed arbitration, all devices participate in the selection of the next bus
master.
In this scheme each device on the bus is assigned a 4-bit identification number.
when one or more devices request bus they assert the start-arbitration signal
and place their 4-bit ID numbers on arbitration lines, ARB0 through ARB3.
These four arbitration lines are all open-collector. Therefore, more than one
device can place their 4-bit ID number to indicate that they need to control of
bus. If one device puts 1 on the bus line and another device puts 0 on the same
bus line, the bus line status will be 0. Device reads the status of all lines through
inverters buffers so device reads bus status 0 as logic 1. The device having
highest ID number has highest priority.When two or more devices place their
ID number on bus lines then it is necessary to identify the highest ID number on
bus lines .A winner is selected as a result of interaction among signals
transmittedover these lines by all contenders Net outcome is tha the code on
four lines represents request that has highest ID number
Advantage: This approach offers higher reliability since operation of bus is not
dependent on any single device