`timescale 1ns / 1ps

module BoothMultiplierradix4 (my_ce_1,my_clk_1,Ld,M,R,Valid,P);

input my_ce_1; // ce
input my_clk_1; // Clock
input Ld; //Load Reg and Start Multiplier
input [15:0] M; // Multiplicand
input [15:0] R; // Multiplier
output reg Valid; // Product Valid
output reg [31:0] P; // Product <= M * R

//
// Declarations
//

reg [4:0] Cntr; // Operation Counter

reg [2:0] Booth; // Booth Recoding Field
reg Guard; // Shift Bit for Booth Recoding
reg [17:0] Hi; // Upper Half of Product w/ guards
reg [17:0] A; // Multiplicand w/ guards
reg [17:0] S; // Adder w/ guards
reg [33:0] Prod; // Double Length Product w/ guards
// Implementation
// Multiplicand Register
// Includes 2 bits to guard sign of multiplicand in the event the most
//negative value is provided as the input.
always @(posedge my_clk_1)
begin
if(my_ce_1) begin
Cntr <=0;
A <=0;
end else if(Ld) begin
Cntr <= 8;
A <={{2{M[15]}}, M};
end else if(|Cntr) begin
Cntr <=(Cntr - 1);
end
end
always @(*)
begin
Booth <= {Prod[1:0], Guard}; // Booth's Multiplier Recoding fld

Hi <= Prod[33:16]; // Upper Half of the Product Register

case(Booth)
4'b0000 : S <= Hi; // Prod <= (Prod + 0*A) >> 2;
4'b0001 : S <= Hi + A; // Prod <= (Prod + 1*A) >> 2;
4'b0010 : S <= Hi + A; // Prod <= (Prod + 1*A) >> 2;
4'b0011 : S <= Hi + {A, 1'b0}; // Prod <= (Prod + 2*A) >> 2;
4'b0100 : S <= Hi - {A, 1'b0}; // Prod <= (Prod - 2*A) >> 2;
4'b0101 : S <= Hi - A; // Prod <= (Prod - 1*A) >> 2;
4'b0110 : S <= Hi - A; // Prod <= (Prod - 1*A) >> 2;
4'b0111 : S <= Hi; // Prod <= (Prod - 0*A) >> 2;
 4'b1000 : S <= Hi; // Prod <= (Prod + 0*A) >> 2;
4'b1001 : S <= Hi + A; // Prod <= (Prod + 1*A) >> 2;
4'b1010 : S <= Hi + A; // Prod <= (Prod + 1*A) >> 2;
4'b1011 : S <= Hi + {A, 1'b0}; // Prod <= (Prod + 2*A) >> 2;
4'b1100 : S <= Hi - {A, 1'b0}; // Prod <= (Prod - 2*A) >> 2;
4'b1101 : S <= Hi - A; // Prod <= (Prod - 1*A) >> 2;
4'b1110 : S <= Hi - A; // Prod <= (Prod - 1*A) >> 2;
4'b1111 : S <= Hi; // Prod <= (Prod - 0*A) >> 2;

endcase
end
// Double Length Product Register
// Multiplier, R, is loaded into the least significant half on
load, Ld.
// Shifted right two places as the product is computed
iteratively.

always @(posedge my_clk_1)

begin
if(my_ce_1)
begin
Prod <= 0;
end else if(Ld) begin
Prod <= R;
end else if(|Cntr) begin
// Shift right two bits
Prod <= {{2{S[17]}}, S, Prod[15:2]};
end
end
always @(posedge my_clk_1)
begin
if(my_ce_1) begin
Guard <= 0; end
else if(Ld) begin
Guard <= 0; end
else if(|Cntr) begin
Guard <=Prod[1];
end
end
// Assign the product less the two guard bits to the output port
// A double right shift is required since the output product is
stored
// into a synchronous register on the last cycle of the multiply.

always @(posedge my_clk_1)

begin
if(my_ce_1) begin
P <= 0; end
else if(Cntr == 1) begin
P <= {S, Prod[15:2]}; end
end
// Count the number of shifts
// This implementation does not use any optimizations to perform
multiple
// bit shifts to skip over runs of 1s or 0s.

always @(posedge my_clk_1)

begin
if(my_ce_1) begin
Valid <= 0; end
else begin
Valid <= !(Cntr);
end
end
endmodule